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More Cleanup.

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This commit is contained in:
Ross Thompson 2022-08-31 11:21:02 -05:00
parent 68e54977fe
commit 1663f571ed
2 changed files with 19 additions and 8 deletions
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12
pipelined/src/ifu/ifu.sv
View File

@ -209,7 +209,10 @@ module ifu (
logic [`PA_BITS-1:0] ICacheBusAdr; logic [`PA_BITS-1:0] ICacheBusAdr;
logic ICacheBusAck; logic ICacheBusAck;
logic SelUncachedAdr; logic SelUncachedAdr;
logic [1:0] CacheRW, RW;
assign CacheRW = {ICacheFetchLine, 1'b0} & ~{ITLBMissF, ITLBMissF};
assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF};
cache #(.LINELEN(`ICACHE_LINELENINBITS), cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
@ -230,12 +233,12 @@ module ifu (
AHBCachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) AHBCachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
cachedp(.HCLK(clk), .HRESETn(~reset), cachedp(.HCLK(clk), .HRESETn(~reset),
.HRDATA, .HRDATA,
.CacheRW({ICacheFetchLine, 1'b0} & ~{ITLBMissF, ITLBMissF}), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .CacheRW, .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
.WordCount(), .SelUncachedAdr, .SelBusWord(), .WordCount(), .SelUncachedAdr, .SelBusWord(),
.CacheBusAck(ICacheBusAck), .CacheBusAck(ICacheBusAck),
.FetchBuffer, .PAdr(PCPF), .FetchBuffer, .PAdr(PCPF),
.RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF}), .CPUBusy, .RW, .CPUBusy,
.BusStall, .BusCommitted()); .BusStall, .BusCommitted());
mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]), mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),
@ -243,11 +246,12 @@ module ifu (
end else begin : passthrough end else begin : passthrough
assign IFUHADDR = PCPF; assign IFUHADDR = PCPF;
logic CaptureEn; logic CaptureEn;
logic [1:0] RW;
assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF};
flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0])); flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0]));
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), .CaptureEn, AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, .CaptureEn,
.BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE)); .BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
assign IFUHBURST = 3'b0; assign IFUHBURST = 3'b0;

13
pipelined/src/lsu/lsu.sv
View File

@ -243,6 +243,10 @@ module lsu (
logic SelBusWord; logic SelBusWord;
logic [`XLEN-1:0] LSUHWDATA_noDELAY; //*** change name logic [`XLEN-1:0] LSUHWDATA_noDELAY; //*** change name
logic [`XLEN/8-1:0] ByteMaskMDelay; logic [`XLEN/8-1:0] ByteMaskMDelay;
logic [1:0] CacheRW, UnCacheRW;
assign CacheRW = {DCacheFetchLine, DCacheWriteLine} & ~{IgnoreRequest, IgnoreRequest};
assign UnCacheRW = LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM};
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
@ -260,9 +264,9 @@ module lsu (
.HRDATA, .HRDATA,
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
.WordCount, .SelBusWord, .WordCount, .SelBusWord,
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheRW({DCacheFetchLine, DCacheWriteLine} & ~{IgnoreRequest, IgnoreRequest}), .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheRW,
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM),
.SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM}), .CPUBusy, .SelUncachedAdr, .RW(UnCacheRW), .CPUBusy,
.BusStall, .BusCommitted(BusCommittedM)); .BusStall, .BusCommitted(BusCommittedM));
mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }), mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0] }),
@ -282,6 +286,9 @@ module lsu (
end else begin : passthrough // just needs a register to hold the value from the bus end else begin : passthrough // just needs a register to hold the value from the bus
logic CaptureEn; logic CaptureEn;
logic [1:0] RW;
assign RW = LSURWM & ~{IgnoreRequest, IgnoreRequest};
assign LSUHADDR = LSUPAdrM; assign LSUHADDR = LSUPAdrM;
assign LSUHSIZE = LSUFunct3M; assign LSUHSIZE = LSUFunct3M;
@ -290,7 +297,7 @@ module lsu (
flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB); flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB);
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW,
.BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS),
.HWRITE(LSUHWRITE)); .HWRITE(LSUHWRITE));