From 15bdf5680ed3d1d05c28a58c43d813d02b7e9a05 Mon Sep 17 00:00:00 2001
From: Noah Limpert <nlimpert@g.hmc.edu>
Date: Wed, 8 Dec 2021 00:24:27 -0800
Subject: [PATCH] removed .* instantiation from ieu.sv and datapth.sv in ieu
folder
---
wally-pipelined/src/ieu/datapath.sv | 2 +-
wally-pipelined/src/ieu/ieu.sv | 66 +++++++++++++++++++++++++++--
2 files changed, 64 insertions(+), 4 deletions(-)
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index 838d83a79..0679f8c35 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -96,7 +96,7 @@ module datapath (
//Mux for writting floating point
regfile regf(clk, reset, {RegWriteW | FWriteIntW}, Rs1D, Rs2D, RdW, WriteDataW, RD1D, RD2D);
- extend ext(.InstrD(InstrD[31:7]), .*);
+ extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
// Execute stage pipeline register and logic
flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, RD1D, RD1E);
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index e9c6d1174..068495220 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -90,9 +90,69 @@ module ieu (
logic MemReadE, CSRReadE;
logic JumpE;
- controller c(.*);
- datapath dp(.*);
- forward fw(.*);
+ controller c(
+ .clk, .reset,
+ // Decode stage control signals
+ .StallD, .FlushD, .InstrD, .ImmSrcD,
+ .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
+ // Execute stage control signals
+ .StallE, .FlushE, .FlagsE,
+ .PCSrcE, // for datapath and Hazard Unit
+ .ALUControlE, .ALUSrcAE, .ALUSrcBE,
+ .TargetSrcE,
+ .MemReadE, .CSRReadE, // for Hazard Unit
+ .Funct3E, .MulDivE, .W64E,
+ .JumpE,
+ // Memory stage control signals
+ .StallM, .FlushM, .MemRWM,
+ .CSRReadM, .CSRWriteM, .PrivilegedM,
+ .SCE, .AtomicE, .AtomicM, .Funct3M,
+ .RegWriteM, // for Hazard Unit
+ .InvalidateICacheM, .FlushDCacheM, .InstrValidM,
+ // Writeback stage control signals
+ .StallW, .FlushW,
+ .RegWriteW, // for datapath and Hazard Unit
+ .ResultSrcW,
+ // Stall during CSRs
+ .CSRWritePendingDEM,
+ .StoreStallD
+ );
+
+ datapath dp(
+ .clk, .reset,
+ // Decode stage signals
+ .ImmSrcD, .InstrD,
+ // Execute stage signals
+ .StallE, .FlushE, .ForwardAE, .ForwardBE,
+ .ALUControlE, .ALUSrcAE, .ALUSrcBE,
+ .TargetSrcE, .JumpE, .IllegalFPUInstrE,
+ .FWriteDataE, .PCE, .PCLinkE, .FlagsE,
+ .PCTargetE,
+ .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+ .SrcAE, .SrcBE,
+ // Memory stage signals
+ .StallM, .FlushM, .FWriteIntM, .FIntResM,
+ .SrcAM, .WriteDataM, .MemAdrM, .MemAdrE,
+ // Writeback stage signals
+ .StallW, .FlushW, .FWriteIntW, .RegWriteW,
+ .SquashSCW, .ResultSrcW, .ReadDataW,
+ // input logic [`XLEN-1:0] PCLinkW,
+ .CSRReadValW, .ReadDataM, .MulDivResultW,
+ // Hazard Unit signals
+ .Rs1D, .Rs2D, .Rs1E, .Rs2E,
+ .RdE, .RdM, .RdW
+ );
+
+ forward fw(
+ .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
+ .MemReadE, .MulDivE, .CSRReadE,
+ .RegWriteM, .RegWriteW,
+ .FWriteIntE, .FWriteIntM, .FWriteIntW,
+ .SCE,
+ // Forwarding controls
+ .ForwardAE, .ForwardBE,
+ .FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD
+ );
endmodule