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https://github.com/openhwgroup/cvw
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Implemented mhpmevent[3:31] as read-only zero rather than illegal
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@ -8,7 +8,6 @@
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// See RISC-V Privileged Mode Specification 20190608 3.1.10-11
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//
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// Documentation: RISC-V System on Chip Design
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// MHPMEVENT is not supported
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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@ -66,7 +65,8 @@ module csrc import cvw::*; #(parameter cvw_t P) (
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localparam MTIME = 12'hB01; // this is a memory-mapped register; no such CSR exists, and access should faul;
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localparam MHPMCOUNTERHBASE = 12'hB80;
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localparam MTIMEH = 12'hB81; // this is a memory-mapped register; no such CSR exists, and access should fault
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localparam MHPMEVENTBASE = 12'h320;
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localparam MHPMEVENTBASE = 12'h323;
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localparam MHPMEVENTLAST = 12'h33F;
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localparam HPMCOUNTERBASE = 12'hC00;
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localparam HPMCOUNTERHBASE = 12'hC80;
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localparam TIME = 12'hC01;
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@ -156,6 +156,9 @@ module csrc import cvw::*; #(parameter cvw_t P) (
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if (PrivilegeModeW == P.M_MODE |
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MCOUNTEREN_REGW[CounterNumM] & (!P.S_SUPPORTED | PrivilegeModeW == P.S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
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IllegalCSRCAccessM = 1'b0;
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if (CSRAdrM >= MHPMEVENTBASE & CSRAdrM <= MHPMEVENTLAST) begin
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CSRCReadValM = '0; // mphmevent[3:31] tied to read-only zero
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end else begin
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if (P.XLEN==64) begin // 64-bit counter reads
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// Veri lator doesn't realize this only occurs for XLEN=64
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/* verilator lint_off WIDTH */
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@ -188,6 +191,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
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IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist
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end
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end
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end
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end else begin
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CSRCReadValM = '0;
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IllegalCSRCAccessM = 1'b1; // no privileges for this csr
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