From 15042fc856ac3c39e70bcc474d5704ce252340c0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 14:50:01 -0600 Subject: [PATCH] Updated fpga constraints. --- fpga/constraints/debug2.xdc | 2 +- fpga/generator/Makefile | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 07eab1ae5..480575aa6 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -316,7 +316,7 @@ connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IF create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe61] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] -connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]] +connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe62] diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 8dff84a49..f39a9bce9 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,13 +1,13 @@ dst := IP # vcu118 -#export XILINX_PART := xcvu9p-flga2104-2L-e -#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 -#export board := vcu118 +export XILINX_PART := xcvu9p-flga2104-2L-e +export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 +export board := vcu118 # vcu108 -export XILINX_PART := xcvu095-ffva2104-2-e -export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 -export board := vcu108 +#export XILINX_PART := xcvu095-ffva2104-2-e +#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 +#export board := vcu108 all: FPGA