From 14cde0d59cd72ec08b6271bc464560a0c32add1f Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 4 Feb 2021 22:03:45 +0000 Subject: [PATCH] Change CSR reset and available bits to conform to OVPsim Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay. --- wally-pipelined/regression/wally-busybear.do | 9 ++++++++- wally-pipelined/src/privileged/csrm.sv | 5 +++-- wally-pipelined/src/privileged/csrs.sv | 2 +- wally-pipelined/src/privileged/csrsr.sv | 18 +++++++++--------- 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 1099676e3..bafc1b5b8 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -31,7 +31,7 @@ vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt +acc work.testbench_busybear -o workopt -vsim workopt +vsim workopt -suppress 8852 view wave @@ -48,6 +48,13 @@ add wave /testbench_busybear/lastInstrF add wave /testbench_busybear/speculative add wave /testbench_busybear/lastPC2 add wave -divider +#add wave -hex /testbench_busybear/dut/priv/csr/MTVEC_REG +#add wave -hex /testbench_busybear/dut/priv/csr/MSTATUS_REG +#add wave -hex /testbench_busybear/dut/priv/csr/SCOUNTEREN_REG +#add wave -hex /testbench_busybear/dut/priv/csr/MIE_REG +#add wave -hex /testbench_busybear/dut/priv/csr/MIDELEG_REG +#add wave -hex /testbench_busybear/dut/priv/csr/MEDELEG_REG +add wave -divider # registers! add wave -hex /testbench_busybear/regExpected add wave -hex /testbench_busybear/regNumExpected diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index 6e56c079b..0ef268638 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -108,7 +108,8 @@ module csrm #(parameter assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT); // CSRs - flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, `RESET_VECTOR, MTVEC_REGW); + //flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, `RESET_VECTOR, MTVEC_REGW); + flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, `XLEN'b0, MTVEC_REGW); generate if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, zero, MEDELEG_REGW); @@ -125,7 +126,7 @@ module csrm #(parameter flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); - flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], allones, MCOUNTEREN_REGW); + flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW); flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], allones, MCOUNTINHIBIT_REGW); flopenr #(`XLEN) PMPADDR0reg(clk, reset, WritePMPADDR0M, CSRWriteValM, PMPADDR0_REGW); // PMPCFG registers are a pair of 64-bit in RV64 and four 32-bit in RV32 diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv index 9de3723a5..e8520320d 100644 --- a/wally-pipelined/src/privileged/csrs.sv +++ b/wally-pipelined/src/privileged/csrs.sv @@ -83,7 +83,7 @@ module csrs #(parameter flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, zero, SCAUSE_REGW); flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); - flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW); + flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW); if (`N_SUPPORTED) begin flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, zero, SEDELEG_REGW); flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, zero, SIDELEG_REGW); diff --git a/wally-pipelined/src/privileged/csrsr.sv b/wally-pipelined/src/privileged/csrsr.sv index 6db96dcc5..66f3eb91a 100644 --- a/wally-pipelined/src/privileged/csrsr.sv +++ b/wally-pipelined/src/privileged/csrsr.sv @@ -109,15 +109,15 @@ module csrsr ( if (reset) begin STATUS_SUM_INT <= 0; STATUS_MPRV_INT <= 0; // Per Priv 3.3 - STATUS_FS_INT <= 2'b01; // initial - STATUS_MPP <= `M_MODE; - STATUS_SPP <= 1'b1; - STATUS_MPIE <= 1; - STATUS_SPIE <= `S_SUPPORTED; - STATUS_UPIE <= `U_SUPPORTED; + STATUS_FS_INT <= 0; //2'b01; // initial + STATUS_MPP <= 0; //`M_MODE; + STATUS_SPP <= 0; //1'b1; + STATUS_MPIE <= 0; //1; + STATUS_SPIE <= 0; //`S_SUPPORTED; + STATUS_UPIE <= 0; // `U_SUPPORTED; STATUS_MIE <= 0; // Per Priv 3.3 - STATUS_SIE <= `S_SUPPORTED; - STATUS_UIE <= `U_SUPPORTED; + STATUS_SIE <= 0; // `S_SUPPORTED; + STATUS_UIE <= 0; // `U_SUPPORTED; end else begin if (WriteMSTATUSM) begin STATUS_SUM_INT <= CSRWriteValM[18]; @@ -179,4 +179,4 @@ module csrsr ( // *** add code to track STATUS_FS_INT for dirty floating point registers end end -endmodule \ No newline at end of file +endmodule