Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #91 from davidharrishmc/dev

Browse Source 
Synthesis updates
This commit is contained in:
Ross Thompson 2023-02-18 00:54:56 -06:00 committed by GitHub
commit 1448ef1c6d
5 changed files with 29 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
README.md
View File

@ -209,6 +209,12 @@ It is most convenient if the sysadmin installs riscof into the server’s Python
However, riscof can also be installed and run locally by individual users. However, riscof can also be installed and run locally by individual users.
### Other Python libraries
While a sysadmin is installing Python libraries, it's worth doing some more that will be needed by visualization scripts.
$ sudo pip3 install matplotlib scipy sklearn adjustText lief
### Install Verilator ### Install Verilator
Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code. It is needed to run regression. Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code. It is needed to run regression.

14
src/generic/mem/ram1p1rwbe.sv
View File

@ -34,7 +34,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) ( module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
input logic clk, input logic clk,
input logic ce, input logic ce,
input logic [$clog2(DEPTH)-1:0] addr, input logic [$clog2(DEPTH)-1:0] addr,
@ -69,7 +69,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) (
.A(addr), .D(din), .A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout)); .BWEB(~BitWriteMask), .Q(dout));
end else if (`USE_SRAM == 1 & WIDTH == 22 & DEPTH == 32) begin // RV32 cache tag end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag
genvar index; genvar index;
// 64 x 22-bit SRAM // 64 x 22-bit SRAM
logic [WIDTH-1:0] BitWriteMask; logic [WIDTH-1:0] BitWriteMask;
@ -86,8 +86,14 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=128) (
integer i; integer i;
// Read // Read
always_ff @(posedge clk) logic [$clog2(DEPTH)-1:0] addrd;
if(ce) dout <= #1 RAM[addr]; flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
assign dout = RAM[addrd];
/* // Read
always_ff @(posedge clk)
if(ce) dout <= #1 mem[addr]; */
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.

17
src/generic/mem/ram2p1r1wbe.sv
View File

@ -33,7 +33,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
input logic clk, input logic clk,
input logic ce1, ce2, input logic ce1, ce2,
input logic [$clog2(DEPTH)-1:0] ra1, input logic [$clog2(DEPTH)-1:0] ra1,
@ -52,7 +52,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
// TRUE Smem macro // TRUE Smem macro
// *************************************************************************** // ***************************************************************************
if (`USE_SRAM == 1 & WIDTH == 68 & DEPTH == 1024) begin if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk),
.CEBA(~ce1), .CEBB(~ce2), .CEBA(~ce1), .CEBB(~ce2),
@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
.QA(rd1), .QA(rd1),
.QB()); .QB());
end else if (`USE_SRAM == 1 & WIDTH == 36 & DEPTH == 1024) begin end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin
ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk),
.CEBA(~ce1), .CEBB(~ce2), .CEBA(~ce1), .CEBB(~ce2),
@ -76,7 +76,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
.QA(rd1), .QA(rd1),
.QB()); .QB());
end else if (`USE_SRAM == 1 & WIDTH == 2 & DEPTH == 1024) begin end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin
logic [SRAMWIDTH-1:0] SRAMReadData; logic [SRAMWIDTH-1:0] SRAMReadData;
logic [SRAMWIDTH-1:0] SRAMWriteData; logic [SRAMWIDTH-1:0] SRAMWriteData;
@ -113,9 +113,14 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
// *************************************************************************** // ***************************************************************************
integer i; integer i;
// Read // Read
logic [$clog2(DEPTH)-1:0] ra1d;
flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d);
assign rd1 = mem[ra1d];
/* // Read
always_ff @(posedge clk) always_ff @(posedge clk)
if(ce1) rd1 <= #1 mem[ra1]; if(ce1) rd1 <= #1 mem[ra1]; */
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
if(WIDTH >= 8) if(WIDTH >= 8)

2
synthDC/Makefile
View File

@ -20,7 +20,7 @@ export MAXCORES ?= 1
# The output netlist is hard to interpret, but significantly better PPA # The output netlist is hard to interpret, but significantly better PPA
export MAXOPT ?= 0 export MAXOPT ?= 0
export DRIVE ?= FLOP export DRIVE ?= FLOP
export USESRAM ?= 1 export USESRAM ?= 0
export USETOPO ?= 0 export USETOPO ?= 0
time := $(shell date +%F-%H-%M) time := $(shell date +%F-%H-%M)

2
testbench/common/wallyTracer.sv
View File

@ -35,12 +35,10 @@ module wallyTracer(rvviTrace rvvi);
// wally specific signals // wally specific signals
logic reset; logic reset;
logic clk; logic clk;
logic InstrValidD, InstrValidE; logic InstrValidD, InstrValidE;
logic StallF, StallD; logic StallF, StallD;
logic STATUS_SXL, STATUS_UXL; logic STATUS_SXL, STATUS_UXL;
logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW;
logic [`XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; logic [`XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
logic InstrValidM, InstrValidW; logic InstrValidM, InstrValidW;