diff --git a/.gitignore b/.gitignore index 26cfe6b84..a01f1c07d 100644 --- a/.gitignore +++ b/.gitignore @@ -184,3 +184,4 @@ sim/cfi/* sim/branch/* sim/obj_dir examples/verilog/fulladder/obj_dir +config/deriv diff --git a/README.md b/README.md index b9d378fc3..f0b1a9f4b 100644 --- a/README.md +++ b/README.md @@ -24,18 +24,18 @@ New users may wish to do the following setup to access the server via a GUI and Terminal on Mac, cmd on Windows, xterm on Linux See A.1 about ssh -Y login from a terminal -Then clone the repo, source setup, make the tests and run regression +Then fork and clone the repo, source setup, make the tests and run regression If you don't already have a Github account, create one In a web browser, visit https://github.com/openhwgroup/cvw In the upper right part of the screen, click on Fork - Create a fork, choosing the owner as your github account and the repository as cvw. + Create a fork, choosing the owner as your github account + and the repository as cvw. On the Linux computer where you will be working, log in Clone your fork of the repo and run the setup script. Change to your github id. - $ cd $ git clone --recurse-submodules https://github.com//cvw $ cd cvw $ git remote add upstream https://github.com/openhwgroup/cvw diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index c955abf75..8a52b016d 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit c955abf757df98cf38809e40a62d2a6b448ea507 +Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh index 479340eb2..20a65bf98 100755 --- a/bin/CModelBTBAccuracy.sh +++ b/bin/CModelBTBAccuracy.sh @@ -9,6 +9,7 @@ ## Computes the geometric mean for btb accuracy ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/CModelBranchAccuracy.sh b/bin/CModelBranchAccuracy.sh index 8253891bb..2fb7b164a 100755 --- a/bin/CModelBranchAccuracy.sh +++ b/bin/CModelBranchAccuracy.sh @@ -9,6 +9,7 @@ ## Computes the geometric mean. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 24857837b..f6b2cb7e1 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -10,6 +10,7 @@ ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh index c81ba32c9..87648589f 100755 --- a/bin/SeparateBranch.sh +++ b/bin/SeparateBranch.sh @@ -12,6 +12,7 @@ ## separated by benchmark application. Example names are aha-mot64bd_sizeopt_speed_branch.log ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/derivgen.pl b/bin/derivgen.pl new file mode 100755 index 000000000..630962ca8 --- /dev/null +++ b/bin/derivgen.pl @@ -0,0 +1,133 @@ +#!/bin/perl -W + +########################################### +## derivgen.pl +## +## Written: David_Harris@hmc.edu +## Created: 29 January 2024 +## Modified: +## +## Purpose: Read config/derivlist.txt and generate config/deriv/*/config.vh +## derivative configurations from the base configurations +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + + +use strict; +use warnings; +import os; +use Data::Dumper; + +my $curderiv = ""; +my @derivlist = (); +my %derivs; +my %basederiv; +my @derivnames = (); + +if ($#ARGV != -1) { + die("Usage: $0") +} +my $derivlist = "$ENV{WALLY}/config/derivlist.txt"; +open(my $fh, $derivlist) or die "Could not open file '$derivlist' $!"; +foreach my $line (<$fh>) { + chomp $line; + my @tokens = split('\s+', $line); + if ($#tokens < 0 || $tokens[0] =~ /^#/) { # skip blank lines and comments + next; + } + if ($tokens[0] =~ /deriv/) { # start of a new derivative + &terminateDeriv(); + $curderiv = $tokens[1]; + $basederiv{$curderiv} = $tokens[2]; + @derivlist = (); + if ($#tokens > 2) { + my $inherits = $derivs{$tokens[3]}; + @derivlist = @{$inherits}; + } + } else { # add to the current derivative + $line =~ /\s*(\S+)\s*(.*)/; + my @entry = ($1, $2); + push(@derivlist, \@entry); + } +} +&terminateDeriv(); +close($fh); +#foreach my $key (keys %derivs) { +foreach my $key (@derivnames) { + my $dir = "$ENV{WALLY}/config/deriv/$key"; + system("rm -rf $dir"); + system("mkdir -p $dir"); + my $configunmod = "$dir/config_unmod.vh"; + my $config = "$dir/config.vh"; + my $base = "$ENV{WALLY}/config/$basederiv{$key}/config.vh"; + if (! -e $base) { + $base = "$ENV{WALLY}/config/deriv/$basederiv{$key}/config.vh"; + #if (! -e $base) { + # die("Unable to find base config $base for $key\n"); + #} + } + system("cp $base $configunmod"); + open(my $unmod, $configunmod) or die "Could not open file '$configunmod' $!"; + open(my $fh, '>>', $config) or die "Could not open file '$config' $!"; + + my $datestring = localtime(); + my %hit = (); + print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring usubg derivgen.pl\n"; + foreach my $line (<$unmod>) { + foreach my $entry (@{$derivs{$key}}) { + my @ent = @{$entry}; + my $param = $ent[0]; + my $value = $ent[1]; + if ($line =~ s/$param\s*=\s*.*;/$param = $value;/) { + $hit{$param} = 1; +# print("Hit: new line in $config for $param is $line"); + } + } + print $fh $line; + } + close($fh); + close($unmod); + foreach my $entry (@{$derivs{$key}}) { + my @ent = @{$entry}; + my $param = $ent[0]; + if (!exists($hit{$param})) { + print("Unable to find $param in $key\n"); + } + } + system("rm -f $dir/config_unmod.vh"); +} + +sub terminateDeriv { + if ($curderiv ne "") { # close out the previous derivative + my @dl = @derivlist; + $derivs{$curderiv} = \@dl; + push(@derivnames, $curderiv); + } +}; + +sub printref { + my $ref = shift; + my @array = @{$ref}; + foreach my $entry (@array) { + print join('_', @{$entry}), ', '; + } + print("\n"); +} \ No newline at end of file diff --git a/bin/elf2hex.sh b/bin/elf2hex.sh index 56f286135..d36678e9c 100755 --- a/bin/elf2hex.sh +++ b/bin/elf2hex.sh @@ -9,6 +9,7 @@ ## Imperas and riscv-arch-test benchmarks ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/exe2memfile.pl b/bin/exe2memfile.pl index 2af665bbd..4f04ff512 100755 --- a/bin/exe2memfile.pl +++ b/bin/exe2memfile.pl @@ -11,6 +11,7 @@ ## to read into a Verilog simulation with $readmemh ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/fparchtest.sh b/bin/fparchtest.sh new file mode 100755 index 000000000..7ea690e96 --- /dev/null +++ b/bin/fparchtest.sh @@ -0,0 +1,21 @@ +#!/usr/bin/bash +# +# fparchtest.sh +# David_Harris@hmc.edu 26 December 2023 +# +# Drive the riscv-isac and riscv-ctg tools to generate floating-point tests + +# Set up with (not retested) +# cd ~/repos +# git clone https://github.com/riscv/riscv-ctg.git +# git clone https://github.com/riscv/riscv-isac.git +# pip3 install git+https://github.com/riscv/riscv-ctg.git +# pip3 install git+https://github.com/riscv/riscv-isac.git +# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg + +RISCVCTG=/home/harris/repos/riscv-ctg + +#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32 +#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32 +riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug +#riscv_ctg -cf $RISCVCTG/sample_cgfs/dataset.cgf -cf $RISCVCTG/sample_cgfs/rv32im.cgf -d $RISCVCTG/tests --base-isa rv32i # --verbose debug diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh index 404636d7c..339b4c74f 100755 --- a/bin/imperas-one-time.sh +++ b/bin/imperas-one-time.sh @@ -9,6 +9,7 @@ ## Purpose: One time setup script for running imperas. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/libppa.pl b/bin/libppa.pl index ccf4f1548..9f1e8515d 100755 --- a/bin/libppa.pl +++ b/bin/libppa.pl @@ -13,6 +13,7 @@ ## and for TSMC change the $cellname to the actual name of the inverter. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/nightly_build.py b/bin/nightly_build.py new file mode 100755 index 000000000..21d0ce025 --- /dev/null +++ b/bin/nightly_build.py @@ -0,0 +1,693 @@ +#!/usr/bin/python3 +""" +Python Regression Build Automation Script + +This Python script serves the purpose of automating nightly regression builds for a software project. +The script is designed to handle the setup, execution, and reporting aspects of the regression testing process. + +Features: + + 1. Nightly Regression Builds: The script is scheduled to run on a nightly basis, making and executing the regression builds. + + 2. Markdown Report Generation: Upon completion of the regression tests, the script generates detailed reports in Markdown format. + These reports provide comprehensive insights into the test results, including test cases executed, pass/fail status, and any encountered issues. + + 3. Email Notification: The script is configured to send out email notifications summarizing the regression test results. + These emails serve as communication channels for stakeholders, providing them with timely updates on the software's regression status. + +Usage: + +- The script is designed to be scheduled and executed automatically on a nightly basis using task scheduling tools such as Cronjobs. To create a cronjob do the following: + 1) Open Terminal: + + Open your terminal application. This is where you'll enter the commands to create and manage cron jobs. + + 2) Access the Cron Table: + + Type the following command and press Enter: + + crontab -e + + This command opens the crontab file in your default text editor. If it's your first time, you might be prompted to choose a text editor. + + 3) Edit the Cron Table: + The crontab file will open in your text editor. Each line in this file represents a cron job. You can now add your new cron job. + + 4) Syntax: + + Our cron job has the following syntax: + 0 3 * * * BASH_ENV=~/.bashrc bash -l -c "*WHERE YOUR CVW IS MUST PUT FULL PATH*/cvw/bin/wrapper_nightly_runs.sh > *WHERE YOU WANT TO STORE LOG FILES/cron.log 2>&1" + + This cronjob sources the .bashrc file and executes the wrapper script as a user. + + 5) Double check: + + Execute the following command to see your cronjobs: + + crontab -l + +Dependencies: + Python: + - os + - shutil + - datetime from datetime + - re + - markdown + - subprocess + + Bash: + - mutt (email sender) + +Conclusion: + +In summary, this Python script facilitates the automation of nightly regression builds, providing comprehensive reporting and email notification capabilities to ensure effective communication and monitoring of regression test results. +""" + +import os +import shutil +from datetime import datetime +import re +import markdown +import subprocess + + + +class FolderManager: + """A class for managing folders and repository cloning.""" + + def __init__(self): + """ + Initialize the FolderManager instance. + + Args: + base_dir (str): The base directory where folders will be managed and repository will be cloned. + """ + env_extract_var = 'WALLY' + print(f"The environemntal variable is {env_extract_var}") + self.base_dir = os.environ.get(env_extract_var) + print(f"The base directory is: {self.base_dir}") + self.base_parent_dir = os.path.dirname(self.base_dir) + + # print(f"The new WALLY vairable is: {os.environ.get('WALLY')}") + # print(f"The Base Directory is now : {self.base_dir}") + # print(f"The Base Parent Directory is now : {self.base_parent_dir}") + + def create_preliminary_folders(self, folders): + """ + Create preliminary folders if they do not exist. + These folders are: + nightly_runs/repos/ + nightly_runs/results/ + + Args: + folders (list): A list of folder names to be created. + + Returns: + None + """ + + for folder in folders: + folder_path = os.path.join(self.base_parent_dir, folder) + if not os.path.exists(folder_path): + os.makedirs(folder_path) + + def create_new_folder(self, folders): + """ + Create a new folder based on the current date if it does not already exist. + + Args: + folder_name (str): The base name for the new folder. + + Returns: + str: The path of the newly created folder if created, None otherwise. + """ + + todays_date = datetime.now().strftime("%Y-%m-%d") + return_folder_path = [] + for folder in folders: + folder_path = os.path.join(self.base_parent_dir, folder, todays_date) + if not os.path.exists(folder_path): + os.makedirs(folder_path) + return_folder_path.append(folder_path) + else: + return_folder_path.append(None) # Folder already exists + + return return_folder_path + + def clone_repository(self, folder, repo_url): + """ + Clone a repository into the 'cvw' folder if it does not already exist. + + Args: + repo_url (str): The URL of the repository to be cloned. + + Returns: + None + """ + todays_date = datetime.now().strftime("%Y-%m-%d") + repo_folder = os.path.join(self.base_parent_dir, folder, todays_date, 'cvw') + tmp_folder = os.path.join(repo_folder, "tmp") # temprorary files will be stored in here + + if not os.path.exists(repo_folder): + os.makedirs(repo_folder) + os.system(f"git clone --recurse-submodules {repo_url} {repo_folder}") + os.makedirs(tmp_folder) + + +class TestRunner: + """A class for making, running, and formatting test results.""" + + def __init__(self): + self.base_dir = os.environ.get('WALLY') + self.base_parent_dir = os.path.dirname(self.base_dir) + self.current_datetime = datetime.now() + #self.temp_dir = self.base_parent_dir + #print(f"Base Directory: {self.base_parent_dir}") + + def copy_setup_script(self, folder): + """ + Copy the setup script to the destination folder. + + The setup script will be copied from the base directory to a specific folder structure inside the base directory. + + Args: + folder: the "nightly_runs/repos/" + + Returns: + bool: True if the script is copied successfully, False otherwise. + """ + # Get today's date in YYYY-MM-DD format + todays_date = datetime.now().strftime("%Y-%m-%d") + + # Define the source and destination paths + source_script = os.path.join(self.base_dir, "setup_host.sh") + destination_folder = os.path.join(self.base_parent_dir, folder, todays_date, 'cvw') + + # Check if the source script exists + if not os.path.exists(source_script): + print(f"Error: Source script '{source_script}' not found.") + return False + + + # Check if the destination folder exists, create it if necessary + if not os.path.exists(destination_folder): + print(f"Error: Destination folder '{destination_folder}' not found.") + return False + + # Copy the script to the destination folder + try: + shutil.copy(source_script, destination_folder) + #print(f"Setup script copied to: {destination_folder}") + return True + except Exception as e: + print(f"Error copying setup script: {e}") + return False + + + def set_env_var(self, folder): + """ + Source a shell script. + + Args: + script_path (str): Path to the script to be sourced. + + Returns: + None + """ + # find the new repository made + todays_date = datetime.now().strftime("%Y-%m-%d") + wally_path = os.path.join(self.base_parent_dir, folder, todays_date, 'cvw') + + # set the WALLY environmental variable to the new repository + os.environ["WALLY"] = wally_path + + self.base_dir = os.environ.get('WALLY') + self.base_parent_dir = os.path.dirname(self.base_dir) + self.temp_dir = self.base_parent_dir + + # print(f"The new WALLY vairable is: {os.environ.get('WALLY')}") + # print(f"The Base Directory is now : {self.base_dir}") + # print(f"The Base Parent Directory is now : {self.base_parent_dir}") + + def execute_makefile(self, target=None): + """ + Execute a Makefile with optional target. + + Args: + makefile_path (str): Path to the Makefile. + target (str, optional): Target to execute in the Makefile. + + Returns: + True if the tests were made + False if the tests didnt pass + """ + # Prepare the command to execute the Makefile + make_file_path = os.path.join(self.base_dir, "sim") + os.chdir(make_file_path) + + output_file = os.path.join(self.base_dir, "tmp", "make_output.log") + + command = ["make"] + + # Add target to the command if specified + if target: + command.append(target) + #print(f"The command is: {command}") + + # Execute the command using subprocess and save the output into a file + with open(output_file, "w") as f: + formatted_datetime = self.current_datetime.strftime("%Y-%m-%d %H:%M:%S") + f.write(formatted_datetime) + f.write("\n\n") + result = subprocess.run(command, stdout=f, stderr=subprocess.STDOUT, text=True) + + # Execute the command using a subprocess and not save the output + #result = subprocess.run(command, text=True) + + # Check the result + if result.returncode == 0: + #print(f"Makefile executed successfully{' with target ' + target if target else ''}.") + return True + else: + #print("Error executing Makefile.") + return False + + def run_tests(self, test_type=None, test_name=None, test_exctention=None): + """ + Run a script through the terminal and save the output to a file. + + Args: + test_name (str): The test name will allow the function to know what test to execute in the sim directory + test_type (str): The type such as python, bash, etc + Returns: + True and the output file location + """ + + # Prepare the function to execute the simulation + test_file_path = os.path.join(self.base_dir, "sim") + + output_file = os.path.join(self.base_dir, "tmp", f"{test_name}-output.log") + os.chdir(test_file_path) + + if test_exctention: + command = [test_type, test_name, test_exctention] + else: + command = [test_type, test_name] + + # Execute the command using subprocess and save the output into a file + with open(output_file, "w") as f: + formatted_datetime = self.current_datetime.strftime("%Y-%m-%d %H:%M:%S") + f.write(formatted_datetime) + f.write("\n\n") + result = subprocess.run(command, stdout=f, stderr=subprocess.STDOUT, text=True) + + # Check if the command executed successfully + if result.returncode or result.returncode == 0: + return True, output_file + else: + print("Error:", result.returncode) + return False, output_file + + + def clean_format_output(self, input_file, output_file=None): + """ + Clean and format the output from tests. + + Args: + input_file (str): Path to the input file with raw test results. + output_file (str): Path to the file where cleaned and formatted output will be saved. + + Returns: + None + """ + # Implement cleaning and formatting logic here + + # Open up the file with only read permissions + with open(input_file, 'r') as input_file: + unlceaned_output = input_file.read() + + # use something like this function to detect pass and fail + passed_configs = [] + failed_configs = [] + + lines = unlceaned_output.split('\n') + index = 0 + + while index < len(lines): + # Remove ANSI escape codes + line = re.sub(r'\x1b\[[0-9;]*[mGK]', '', lines[index]) + #print(line) + if "Success" in line: + passed_configs.append(line.split(':')[0].strip()) + elif "passed lint" in line: + #print(line) + passed_configs.append(line.split(' ')[0].strip()) + #passed_configs.append(line) # potentially use a space + elif "failed lint" in line: + failed_configs.append(line.split(' ')[0].strip(), "no log file") + #failed_configs.append(line) + + elif "Failures detected in output" in line: + try: + config_name = line.split(':')[0].strip() + log_file = os.path.abspath("logs/"+config_name+".log") + #print(f"The log file saving to: {log_file} in the current working directory: {os.getcwd()}") + failed_configs.append((config_name, log_file)) + except: + failed_configs.append((config_name, "Log file not found")) + + + index += 1 + + # alphabetically sort the configurations + if len(passed_configs) != 0: + passed_configs.sort() + + if len(failed_configs) != 0: + failed_configs.sort() + #print(f"The passed configs are: {passed_configs}") + #print(f"The failed configs are {failed_configs}") + return passed_configs, failed_configs + + def rewrite_to_markdown(self, test_name, passed_configs, failed_configs): + """ + Rewrite test results to markdown format. + + Args: + input_file (str): Path to the input file with cleaned and formatted output. + markdown_file (str): Path to the markdown file where test results will be saved. + + Returns: + None + """ + # Implement markdown rewriting logic here + timestamp = datetime.now().strftime("%Y-%m-%d") + + output_directory = os.path.join(self.base_parent_dir, "../../results", timestamp) + os.chdir(output_directory) + current_directory = os.getcwd() + output_file = os.path.join(current_directory, f"{test_name}.md") + #print("Current directory:", current_directory) + #print("Output File:", output_file) + + with open(output_file, 'w') as md_file: + + # Title + md_file.write(f"\n\n# Regression Test Results - {timestamp}\n\n") + #md_file.write(f"\n\n
\n# Regression Test Results - {timestamp}\n
\n\n") + + # File Path + md_file.write(f"\n**File:** {output_file}\n\n") + + if failed_configs: + md_file.write("## Failed Configurations\n\n") + for config, log_file in failed_configs: + md_file.write(f"- {config} ({log_file})\n") + md_file.write("\n") + else: + md_file.write("## Failed Configurations\n") + md_file.write(f"No Failures\n") + + md_file.write("\n## Passed Configurations\n") + for config in passed_configs: + md_file.write(f"- {config}\n") + + def combine_markdown_files(self, passed_tests, failed_tests, test_list, total_number_failures, total_number_success, test_type="default", markdown_file=None): + """ + First we want to display the server properties like: + - Server full name + - Operating System + + Combine the markdown files and format them to display all of the failures at the top categorized by what kind of test it was + Then display all of the successes. + + Args: + passed_tests (list): a list of successful tests + failed_tests (list): a list of failed tests + test_list (list): a list of the test names. + markdown_file (str): Path to the markdown file where test results will be saved. + + Returns: + None + """ + timestamp = datetime.now().strftime("%Y-%m-%d") + + output_directory = os.path.join(self.base_parent_dir, "../../results", timestamp) + os.chdir(output_directory) + current_directory = os.getcwd() + output_file = os.path.join(current_directory, "results.md") + + + with open(output_file, 'w') as md_file: + # Title + md_file.write(f"\n\n# Nightly Test Results - {timestamp}\n\n") + # Host information + try: + # Run hostname command + hostname = subprocess.check_output(['hostname', '-A']).strip().decode('utf-8') + md_file.write(f"**Host name:** {hostname}") + md_file.write("\n") + # Run uname command to get OS information + os_info = subprocess.check_output(['uname', '-a']).strip().decode('utf-8') + md_file.write(f"\n**Operating System Information:** {os_info}") + md_file.write("\n") + except subprocess.CalledProcessError as e: + # Handle if the command fails + md_file.write(f"Failed to identify host and Operating System information: {str(e)}") + + # Which tests did we run + md_file.write(f"\n**Tests made:** `make {test_type}`\n") + + # File Path + md_file.write(f"\n**File:** {output_file}\n\n") # *** needs to be changed + md_file.write(f"**Total Successes: {total_number_success}**\n") + md_file.write(f"**Total Failures: {total_number_failures}**\n") + + # Failed Tests + md_file.write(f"\n\n## Failed Tests") + md_file.write(f"\nTotal failed tests: {total_number_failures}") + for (test_item, item) in zip(test_list, failed_tests): + md_file.write(f"\n\n### {test_item[1]} test") + md_file.write(f"\n**General Information**\n") + md_file.write(f"\n* Test type: {test_item[0]}\n") + md_file.write(f"\n* Test name: {test_item[1]}\n") + md_file.write(f"\n* Test extension: {test_item[2]}\n\n") + md_file.write(f"**Failed Tests:**\n") + + + + if len(item) == 0: + md_file.write("\n") + md_file.write(f"* No failures\n") + md_file.write("\n") + else: + for failed_test in item: + config = failed_test[0] + log_file = failed_test[1] + + md_file.write("\n") + md_file.write(f"* {config} ({log_file})\n") + md_file.write("\n") + # Successfull Tests + + md_file.write(f"\n\n## Successfull Tests") + md_file.write(f"\n**Total successfull tests: {total_number_success}**") + for (test_item, item) in zip(test_list, passed_tests): + md_file.write(f"\n\n### {test_item[1]} test") + md_file.write(f"\n**General Information**\n") + md_file.write(f"\n* Test type: {test_item[0]}") + md_file.write(f"\n* Test name: {test_item[1]}") + md_file.write(f"\n* Test extension: {test_item[2]}\n\n") + md_file.write(f"\n**Successfull Tests:**\n") + + + + if len(item) == 0: + md_file.write("\n") + md_file.write(f"* No successes\n") + md_file.write("\n") + else: + for passed_tests in item: + config = passed_tests + + md_file.write("\n") + md_file.write(f"* {config}\n") + md_file.write("\n") + + + + def convert_to_html(self, markdown_file="results.md", html_file="results.html"): + """ + Convert markdown file to HTML. + + Args: + markdown_file (str): Path to the markdown file. + html_file (str): Path to the HTML file where converted output will be saved. + + Returns: + None + """ + # Implement markdown to HTML conversion logic here + todays_date = self.current_datetime.strftime("%Y-%m-%d") + markdown_file_path = os.path.join(self.base_parent_dir, "../../results", todays_date) + os.chdir(markdown_file_path) + + with open(markdown_file, 'r') as md_file: + md_content = md_file.read() + html_content = markdown.markdown(md_content) + + with open(html_file, 'w') as html_file: + html_file.write(html_content) + + + + def send_email(self, sender_email=None, receiver_emails=None, subject="Nightly Regression Test"): + """ + Send email with HTML content. + + Args: + self: The instance of the class. + sender_email (str): The sender's email address. Defaults to None. + receiver_emails (list[str]): List of receiver email addresses. Defaults to None. + subject (str, optional): Subject of the email. Defaults to "Nightly Regression Test". + + Returns: + None + """ + + # check if there are any emails + if not receiver_emails: + print("No receiver emails provided.") + return + # grab thge html file + todays_date = self.current_datetime.strftime("%Y-%m-%d") + html_file_path = os.path.join(self.base_parent_dir, "../../results", todays_date) + os.chdir(html_file_path) + html_file = "results.html" + + with open(html_file, 'r') as html_file: + body = html_file.read() + + + + + for receiver_email in receiver_emails: + # Compose the mutt command for each receiver email + command = [ + 'mutt', + '-s', subject, + '-e', 'set content_type=text/html', + '-e', 'my_hdr From: James Stine ', + '--', receiver_email + ] + + # Open a subprocess to run the mutt command + process = subprocess.Popen(command, stdin=subprocess.PIPE) + + # Write the email body to the subprocess + process.communicate(body.encode('utf-8')) + + +############################################# +# SETUP # +############################################# +folder_manager = FolderManager() # creates the object + +# setting the path on where to clone new repositories of cvw +path = folder_manager.create_preliminary_folders(["nightly_runs/repos/", "nightly_runs/results/"]) +new_folder = folder_manager.create_new_folder(["nightly_runs/repos/", "nightly_runs/results/"]) + +# clone the cvw repo +folder_manager.clone_repository("nightly_runs/repos/", "https://github.com/openhwgroup/cvw.git") + + + +############################################# +# SETUP # +############################################# + +test_runner = TestRunner() # creates the object +test_runner.set_env_var("nightly_runs/repos/") # ensures that the new WALLY environmental variable is set correctly + + +############################################# +# MAKE TESTS # +############################################# + + +# target = "wally-riscv-arch-test" +target = "all" +if test_runner.execute_makefile(target = target): + print(f"The {target} tests were made successfully") + +############################################# +# RUN TESTS # +############################################# + + +test_list = [["python", "regression-wally", "-nightly"], ["bash", "lint-wally", "-nightly"], ["bash", "coverage", "--search"]] +output_log_list = [] # a list where the output markdown file lcoations will be saved to +total_number_failures = 0 # an integer where the total number failures from all of the tests will be collected +total_number_success = 0 # an integer where the total number of sucess will be collected + +total_failures = [] +total_success = [] + +for test_type, test_name, test_exctention in test_list: + print("--------------------------------------------------------------") + print(f"Test type: {test_type}") + print(f"Test name: {test_name}") + print(f"Test extenction: {test_exctention}") + + check, output_location = test_runner.run_tests(test_type=test_type, test_name=test_name, test_exctention=test_exctention) + print(check) + print(output_location) + if check: # this checks if the test actually ran successfully + output_log_list.append(output_location) + + # format tests to markdown + try: + passed, failed = test_runner.clean_format_output(input_file = output_location) + except: + print("There was an error cleaning the data") + + print(f"The # of failures are for {test_name}: {len(failed)}") + total_number_failures+= len(failed) + total_failures.append(failed) + + print(f"The # of sucesses are for {test_name}: {len(passed)}") + total_number_success += len(passed) + total_success.append(passed) + test_runner.rewrite_to_markdown(test_name, passed, failed) + +print(f"The total sucesses are: {total_number_success}") +print(f"The total failures are: {total_number_failures}") + + + + + + +############################################# +# FORMAT TESTS # +############################################# + +# Combine multiple markdown files into one file + +test_runner.combine_markdown_files(passed_tests = total_success, failed_tests = total_failures, test_list = test_list, total_number_failures = total_number_failures, total_number_success = total_number_success, test_type=target, markdown_file=None) + + +############################################# +# WRITE MD TESTS # +############################################# +test_runner.convert_to_html() + + + +############################################# +# SEND EMAIL # +############################################# + +sender_email = 'james.stine@okstate.edu' +receiver_emails = ['thomas.kidd@okstate.edu', 'james.stine@okstate.edu', 'harris@g.hmc.edu', 'rose.thompson10@okstate.edu'] +test_runner.send_email(sender_email=sender_email, receiver_emails=receiver_emails) \ No newline at end of file diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 7e8eb7cde..73535c430 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -8,6 +8,7 @@ ## Purpose: Parses the performance counters from a modelsim trace. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/testcount.pl b/bin/testcount.pl index e801ed0e4..139902dd3 100755 --- a/bin/testcount.pl +++ b/bin/testcount.pl @@ -12,6 +12,7 @@ ## and count how many tests are in each ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/testlist.pl b/bin/testlist.pl index 655cdd6f8..c72b96961 100755 --- a/bin/testlist.pl +++ b/bin/testlist.pl @@ -11,6 +11,7 @@ ## and generate a list of tests and signature addresses for tests.vh ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/vclean.pl b/bin/vclean.pl index f947ed9d0..294d1d435 100755 --- a/bin/vclean.pl +++ b/bin/vclean.pl @@ -11,6 +11,7 @@ ## verilator should do this, but it also reports partially used signals ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7ccb1a138..74157bffa 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -10,6 +10,7 @@ ## Purpose: Open source tool chain installation script ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## @@ -68,9 +69,6 @@ fi cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain -# Temporarily use the following commands until gcc-13 is part of riscv-gnu-toolchain (issue #1249) -#git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13 -#./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13 ./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} @@ -110,14 +108,15 @@ cd riscv-isa-sim/build make -j ${NUM_THREADS} make install cd ../arch_test_target/spike/device -sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include -sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include +# dh 2/5/24: these should be obsolete +#sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include +#sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include # Wally needs Verilator 5.021 or later. # Verilator needs to be built from scratch to get the latest version # apt-get install verilator installs version 4.028 as of 6/8/23 sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g -sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error) +sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g cd $RISCV git clone https://github.com/verilator/verilator # Only first time # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash @@ -172,6 +171,8 @@ sudo make install cd $RISCV opam init -y --disable-sandboxing +opam update +opam upgrade opam switch create 5.1.0 opam install sail -y diff --git a/bin/wrapper_nightly_runs.sh b/bin/wrapper_nightly_runs.sh new file mode 100755 index 000000000..219e765df --- /dev/null +++ b/bin/wrapper_nightly_runs.sh @@ -0,0 +1,28 @@ +#!/bin/bash +date + + +# Variables +LOG=$HOME/nightly_runs/logs/from_wrapper.log # you can store your log file where you would like +PYTHON_SCRIPT=$HOME/nightly_runs/cvw/bin/ # cvw can be anywhere you would like it. Make sure to point your variable there +SETUP_SCRIPT=$HOME/nightly_runs/cvw/ # cvw can be anywhere you would like it. Make sure to point your variable there + + + +date > $LOG 2>&1 + +echo "Current directory" +pwd + +cd $SETUP_SCRIPT +echo "Current directory" +pwd + +echo "Sourcing setup_host" +source ./setup_host.sh >> $LOG 2>&1 +echo "Sourcing setup_tools" + +cd $PYTHON_SCRIPT +pwd +echo "Running python file" +python nightly_build.py >> $LOG 2>&1 diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh deleted file mode 100644 index de6e4800d..000000000 --- a/config/buildroot/config.vh +++ /dev/null @@ -1,180 +0,0 @@ -////////////////////////////////////////// -// config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "BranchPredictorType.vh" - -// RV32 or RV64: XLEN = 32 or 64 -localparam XLEN = 32'd64; - -// IEEE 754 compliance -localparam IEEE754 = 0; - -localparam MISA = (32'h0014112D); -localparam ZICSR_SUPPORTED = 1; -localparam ZIFENCEI_SUPPORTED = 1; -localparam ZICNTR_SUPPORTED = 1; -localparam ZIHPM_SUPPORTED = 1; -localparam COUNTERS = 12'd32; -localparam ZFH_SUPPORTED = 1; -localparam ZFA_SUPPORTED = 0; -localparam SSTC_SUPPORTED = 1; -localparam ZICBOM_SUPPORTED = 1; -localparam ZICBOZ_SUPPORTED = 1; -localparam ZICBOP_SUPPORTED = 1; -localparam ZICCLSM_SUPPORTED = 1; -localparam ZICOND_SUPPORTED = 1; -localparam SVPBMT_SUPPORTED = 1; -localparam SVNAPOT_SUPPORTED = 1; -localparam SVINVAL_SUPPORTED = 1; - -// LSU microarchitectural Features -localparam BUS_SUPPORTED = 1; -localparam DCACHE_SUPPORTED = 1; -localparam ICACHE_SUPPORTED = 1; -localparam VIRTMEM_SUPPORTED = 1; -localparam VECTORED_INTERRUPTS_SUPPORTED = 1; -localparam BIGENDIAN_SUPPORTED = 1; - -// TLB configuration. Entries should be a power of 2 -localparam ITLB_ENTRIES = 32'd32; -localparam DTLB_ENTRIES = 32'd32; - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -localparam DCACHE_NUMWAYS = 32'd4; -localparam DCACHE_WAYSIZEINBYTES = 32'd4096; -localparam DCACHE_LINELENINBITS = 32'd512; -localparam ICACHE_NUMWAYS = 32'd4; -localparam ICACHE_WAYSIZEINBYTES = 32'd4096; -localparam ICACHE_LINELENINBITS = 32'd512; -localparam CACHE_SRAMLEN = 32'd128; - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -localparam IDIV_BITSPERCYCLE = 32'd4; -localparam IDIV_ON_FPU = 1; - -// Legal number of PMP entries are 0, 16, or 64 -localparam PMP_ENTRIES = 32'd16; - -// Address space -localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000; - -// WFI Timeout Wait -localparam WFI_TIMEOUT_BIT = 32'd16; - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -localparam DTIM_SUPPORTED = 1'b0; -localparam logic [63:0] DTIM_BASE = 64'h80000000; -localparam logic [63:0] DTIM_RANGE = 64'h00001FFF; -localparam IROM_SUPPORTED = 1'b0; -localparam logic [63:0] IROM_BASE = 64'h80000000; -localparam logic [63:0] IROM_RANGE = 64'h00001FFF; -localparam BOOTROM_SUPPORTED = 1'b1; -localparam logic [63:0] BOOTROM_BASE = 64'h00001000 ; -localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b1; -localparam UNCORE_RAM_SUPPORTED = 1'b1; -localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h0FFFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b1; -localparam EXT_MEM_SUPPORTED = 1'b0; -localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; -localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; -localparam CLINT_SUPPORTED = 1'b1; -localparam logic [63:0] CLINT_BASE = 64'h02000000; -localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; -localparam GPIO_SUPPORTED = 1'b1; -localparam logic [63:0] GPIO_BASE = 64'h10060000; -localparam logic [63:0] GPIO_RANGE = 64'h000000FF; -localparam UART_SUPPORTED = 1'b1; -localparam logic [63:0] UART_BASE = 64'h10000000; -localparam logic [63:0] UART_RANGE = 64'h00000007; -localparam PLIC_SUPPORTED = 1'b1; -localparam logic [63:0] PLIC_BASE = 64'h0C000000; -localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; -localparam SDC_SUPPORTED = 1'b0; -localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; -localparam SPI_SUPPORTED = 1'b1; -localparam logic [63:0] SPI_BASE = 64'h10040000; -localparam logic [63:0] SPI_RANGE = 64'h00000FFF; - -// Bus Interface width -localparam AHBW = 32'd64; - -// Test modes - -// Tie GPIO outputs back to inputs -localparam GPIO_LOOPBACK_TEST = 0; -localparam SPI_LOOPBACK_TEST = 0; - -// Hardware configuration -localparam UART_PRESCALE = 32'd0; - -// Interrupt configuration -localparam PLIC_NUM_SRC = 32'd53; -localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); -localparam PLIC_UART_ID = 32'd10; -localparam PLIC_GPIO_ID = 32'd3; -localparam PLIC_SPI_ID = 32'd6; -localparam PLIC_SDC_ID = 32'd20; - -localparam BPRED_SUPPORTED = 1; -localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -localparam BPRED_SIZE = 32'd10; -localparam BPRED_NUM_LHR = 32'd6; -localparam BTB_SIZE = 32'd10; -localparam RAS_SIZE = 32'd16; - - -localparam SVADU_SUPPORTED = 1; -localparam ZMMUL_SUPPORTED = 0; - -// FPU division architecture -localparam RADIX = 32'h4; -localparam DIVCOPIES = 32'h4; - -// bit manipulation -localparam ZBA_SUPPORTED = 1; -localparam ZBB_SUPPORTED = 1; -localparam ZBC_SUPPORTED = 1; -localparam ZBS_SUPPORTED = 1; - -// New compressed instructions -localparam ZCB_SUPPORTED = 1; -localparam ZCA_SUPPORTED = 0; -localparam ZCF_SUPPORTED = 0; -localparam ZCD_SUPPORTED = 0; - -// Memory synthesis configuration -localparam USE_SRAM = 0; - -`include "config-shared.vh" diff --git a/config/derivlist.txt b/config/derivlist.txt new file mode 100644 index 000000000..279fbd3c5 --- /dev/null +++ b/config/derivlist.txt @@ -0,0 +1,1077 @@ +########################################### +## derivlist.txt +## Wally Derivative Configuration List +## +## Written: David_Harris@hmc.edu, kekim@hmc.edu +## Created: 29 January 2024 +## Modified: +## +## Purpose: Used by sim/make deriv to generate derivative configurations +## in config/deriv that are variants of the base configurations. +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# Format: +# begin a derivative with "deriv +# Followed by a list of parameters and their new value in the derivative configuration +# All other parameter values are inherited from the original configuration +# If is not empty, all the list of parameter changes in the inherited +# configuration are also applied to this configuration + +# buildroot is used for the Linux boot +deriv buildroot rv64gc +RESET_VECTOR 64'h1000 +UNCORE_RAM_RANGE 64'h0FFFFFFF +UNCORE_RAM_PRELOAD 1 +GPIO_LOOPBACK_TEST 0 +SPI_LOOPBACK_TEST 0 +UART_PRESCALE 32'd0 +PLIC_NUM_SRC 32'd53 + +# fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM) +deriv fpga buildroot +BOOTROM_PRELOAD 1 +UNCORE_RAM_BASE 64'h2000 +UNCORE_RAM_RANGE 64'hFFF +EXT_MEM_SUPPORTED 1 +EXT_MEM_BASE 64'h80000000 +EXT_MEM_RANGE 64'h0FFFFFFF +SDC_SUPPORTED 1 +PLIC_SDC_ID 32'd20 +BPRED_SIZE 32'd12 + +# The syn configurations are trimmed down for faster synthesis. +deriv syn_rv32e rv32e +DTIM_RANGE 64'h1FF +IROM_RANGE 64'h1FF +BOOTROM_RANGE 64'h1FF +UNCORE_RAM_RANGE 64'h1FF +WAYSIZEINBYTES 32'd512 +NUMWAYS 32'd1 +BPRED_SIZE 32'd5 +BTB_SIZE 32'd5 + +# The other syn configurations have the same trimming +deriv syn_rv32i rv32i syn_rv32e +deriv syn_rv32imc rv32imc syn_rv32e +deriv syn_rv32gc syn_rv32e +deriv syn_rv64i rv64i syn_rv32e +deriv syn_rv64gc rv64gc syn_rv32e + +# The syn_sram configurations use SRAM macros +deriv syn_sram_rv32e rv32e +DTIM_RANGE 64'h1FF +IROM_RANGE 64'h1FF +USE_SRAM 1 + +# The other syn configurations have the same trimming +deriv syn_sram_rv32i rv32i syn_sram_rv32e +deriv syn_sram_rv32imc rv32imc syn_sram_rv32e +deriv syn_sram_rv32gc syn_sram_rv32e +deriv syn_sram_rv64i rv64i syn_sram_rv32e +deriv syn_sram_rv64gc rv64gc syn_sram_rv32e + +# The following syn configurations gradually turn off features +deriv syn_pmp0_rv64gc syn_rv64gc +PMP_ENTRIES 32'd0 +deriv syn_sram_pmp0_rv64gc syn_sram_rv64gc +PMP_ENTRIES 32'd0 + +deriv syn_noPriv_rv64gc syn_pmp0_rv64gc +ZICSR_SUPPORTED 0 +deriv syn_sram_noPriv_rv64gc syn_sram_pmp0_rv64gc +ZICSR_SUPPORTED 0 + +deriv syn_noFPU_rv64gc syn_noPriv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +deriv syn_sram_noFPU_rv64gc syn_sram_noPriv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) + +deriv syn_noMulDiv_rv64gc syn_noFPU_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) +deriv syn_sram_noMulDiv_rv64gc syn_sram_noFPU_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) + +deriv syn_noAtomic_rv64gc syn_noMulDiv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20) +deriv syn_sram_noAtomic_rv64gc syn_sram_noMulDiv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20) + +# Divider variants to check logical correctness + +deriv div_2_1_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd1 +IDIV_ON_FPU 0 + +deriv div_2_2_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd2 +IDIV_ON_FPU 0 + +deriv div_2_4_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd4 +IDIV_ON_FPU 0 + +deriv div_4_1_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd1 +IDIV_ON_FPU 0 + +deriv div_4_2_rv32gc rv32gc +RADIX 32'd4 +IDIV_ON_FPU 0 +DIVCOPIES 32'd2 +IDIV_ON_FPU 0 + +deriv div_4_4_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd4 +IDIV_ON_FPU 0 + +deriv div_2_1i_rv32gc div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_2i_rv32gc div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_4i_rv32gc div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_1i_rv32gc div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_2i_rv32gc div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_4i_rv32gc div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_1_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd1 +IDIV_ON_FPU 0 + +deriv div_2_2_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd2 +IDIV_ON_FPU 0 + +deriv div_2_4_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd4 +IDIV_ON_FPU 0 + +deriv div_4_1_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd1 +IDIV_ON_FPU 0 + +deriv div_4_2_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd2 +IDIV_ON_FPU 0 + +deriv div_4_4_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd4 +IDIV_ON_FPU 0 + +deriv div_2_1i_rv64gc div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv div_2_2i_rv64gc div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv div_2_4i_rv64gc div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_1i_rv64gc div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_2i_rv64gc div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_4i_rv64gc div_4_4_rv64gc +IDIV_ON_FPU 1 + +# RAM latency and Burst mode for bus stress testing + +deriv ram_0_0_rv64gc rv64gc +RAM_LATENCY 32'd0 +BURST_EN 0 + +deriv ram_1_0_rv64gc rv64gc +RAM_LATENCY 32'd1 +BURST_EN 0 + +deriv ram_2_0_rv64gc rv64gc +RAM_LATENCY 32'd2 +BURST_EN 0 + +deriv ram_1_1_rv64gc rv64gc +RAM_LATENCY 32'd1 +BURST_EN 1 + +deriv ram_2_1_rv64gc rv64gc +RAM_LATENCY 32'd2 +BURST_EN 1 + +# Branch predictor simulations + +deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc +BPRED_SIZE 32'd6 + +deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc +BPRED_SIZE 32'd8 + +deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc +BPRED_SIZE 32'd10 + +deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc +BPRED_SIZE 32'd12 + +deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc +BPRED_SIZE 32'd14 + +deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc +BPRED_SIZE 32'd16 + +deriv bpred_TWOBIT_6_16_10_1_rv32gc bpred_GSHARE_6_16_10_1_rv32gc +BPRED_TYPE `BP_TWOBIT + +deriv bpred_TWOBIT_8_16_10_1_rv32gc bpred_GSHARE_8_16_10_1_rv32gc +BPRED_TYPE `BP_TWOBIT + +deriv bpred_TWOBIT_10_16_10_1_rv32gc bpred_GSHARE_10_16_10_1_rv32gc +BPRED_TYPE `BP_TWOBIT + +deriv bpred_TWOBIT_12_16_10_1_rv32gc bpred_GSHARE_12_16_10_1_rv32gc +BPRED_TYPE `BP_TWOBIT + +deriv bpred_TWOBIT_14_16_10_1_rv32gc bpred_GSHARE_14_16_10_1_rv32gc +BPRED_TYPE `BP_TWOBIT + +deriv bpred_TWOBIT_16_16_10_1_rv32gc bpred_GSHARE_16_16_10_1_rv32gc +BPRED_TYPE `BP_TWOBIT + +deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc +RAS_SIZE 32'd2 + +deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc +RAS_SIZE 32'd3 + +deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc +RAS_SIZE 32'd4 + +deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc +RAS_SIZE 32'd6 + +deriv bpred_GSHARE_10_10_10_1_rv32gc rv32gc +RAS_SIZE 32'd10 + +deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc +RAS_SIZE 32'd16 + +deriv bpred_GSHARE_10_16_6_1_rv32gc rv32gc +BTB_SIZE 32'd6 + +deriv bpred_GSHARE_10_16_8_1_rv32gc rv32gc +BTB_SIZE 32'd8 + +deriv bpred_GSHARE_10_16_12_1_rv32gc rv32gc +BTB_SIZE 32'd12 + +deriv bpred_GSHARE_10_16_14_1_rv32gc rv32gc +BTB_SIZE 32'd14 + +deriv bpred_GSHARE_10_16_16_1_rv32gc rv32gc +BTB_SIZE 32'd16 + + + + +deriv bpred_GSHARE_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_TWOBIT_6_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_TWOBIT_8_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_TWOBIT_10_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_TWOBIT_12_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_TWOBIT_14_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_TWOBIT_16_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_3_10_0_rv32gc bpred_GSHARE_10_3_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_4_10_0_rv32gc bpred_GSHARE_10_4_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_6_10_0_rv32gc bpred_GSHARE_10_6_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_10_10_0_rv32gc bpred_GSHARE_10_10_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_16_6_0_rv32gc bpred_GSHARE_10_16_6_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_16_8_0_rv32gc bpred_GSHARE_10_16_8_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_16_12_0_rv32gc bpred_GSHARE_10_16_12_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_16_14_0_rv32gc bpred_GSHARE_10_16_14_1_rv32gc +INSTR_CLASS_PRED 0 + +deriv bpred_GSHARE_10_16_16_0_rv32gc bpred_GSHARE_10_16_16_1_rv32gc +INSTR_CLASS_PRED 0 + +# Cache configurations + +deriv noicache_rv32gc rv32gc +ICACHE_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 + +deriv nodcache_rv32gc rv32gc +DCACHE_SUPPORTED 0 + +deriv nocache_rv32gc rv32gc +ICACHE_SUPPORTED 0 +DCACHE_SUPPORTED 0 + +deriv noicache_rv64gc rv64gc +ICACHE_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 +SVPBMT_SUPPORTED 0 +SVNAPOT_SUPPORTED 0 + +deriv nodcache_rv64gc rv64gc +DCACHE_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 +ZICBOM_SUPPORTED 0 +ZICBOZ_SUPPORTED 0 +SVPBMT_SUPPORTED 0 +SVNAPOT_SUPPORTED 0 +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12) + +deriv nocache_rv64gc rv64gc +ICACHE_SUPPORTED 0 +DCACHE_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 +ZICBOM_SUPPORTED 0 +ZICBOZ_SUPPORTED 0 +SVPBMT_SUPPORTED 0 +SVNAPOT_SUPPORTED 0 +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12) + +deriv way_1_4096_512_rv32gc rv32gc +DCACHE_NUMWAYS 32'd1 +DCACHE_WAYSIZEINBYTES 32'd4096 +DCACHE_LINELENINBITS 32'd512 +ICACHE_NUMWAYS 32'd1 +ICACHE_WAYSIZEINBYTES 32'd4096 +ICACHE_LINELENINBITS 32'd512 + +deriv way_2_4096_512_rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 32'd1 +ICACHE_NUMWAYS 32'd1 + +deriv way_4_4096_512_rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 32'd4 +ICACHE_NUMWAYS 32'd4 + +deriv way_8_4096_512_rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 32'd8 +ICACHE_NUMWAYS 32'd8 + +deriv way_4_2048_512_rv32gc way_4_4096_512_rv32gc +DCACHE_WAYSIZEINBYTES 32'd2048 +ICACHE_WAYSIZEINBYTES 32'd2048 + +deriv way_4_4096_256_rv32gc way_4_4096_512_rv32gc +DCACHE_LINELENINBITS 32'd256 +ICACHE_LINELENINBITS 32'd256 + +deriv way_1_4096_512_rv64gc rv64gc +DCACHE_NUMWAYS 32'd1 +DCACHE_WAYSIZEINBYTES 32'd4096 +DCACHE_LINELENINBITS 32'd512 +ICACHE_NUMWAYS 32'd1 +ICACHE_WAYSIZEINBYTES 32'd4096 +ICACHE_LINELENINBITS 32'd512 + +deriv way_2_4096_512_rv64gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 32'd1 +ICACHE_NUMWAYS 32'd1 + +deriv way_4_4096_512_rv64gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 32'd4 +ICACHE_NUMWAYS 32'd4 + +deriv way_8_4096_512_rv64gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 32'd8 +ICACHE_NUMWAYS 32'd8 + +deriv way_4_2048_512_rv64gc way_4_4096_512_rv64gc +DCACHE_WAYSIZEINBYTES 32'd2048 +ICACHE_WAYSIZEINBYTES 32'd2048 + +deriv way_4_4096_256_rv64gc way_4_4096_512_rv64gc +DCACHE_LINELENINBITS 32'd256 +ICACHE_LINELENINBITS 32'd256 + +deriv way_4_4096_1024_rv64gc way_4_4096_512_rv64gc +DCACHE_LINELENINBITS 32'd1024 +ICACHE_LINELENINBITS 32'd1024 + +# TLB Size variants + +deriv tlb2_rv32gc rv32gc +ITLB_ENTRIES 32'd2 +DTLB_ENTRIES 32'd2 + +deriv tlb16_rv32gc rv32gc +ITLB_ENTRIES 32'd16 +DTLB_ENTRIES 32'd16 + +deriv tlb2_rv64gc rv64gc +ITLB_ENTRIES 32'd2 +DTLB_ENTRIES 32'd2 + +deriv tlb16_rv64gc rv64gc +ITLB_ENTRIES 32'd16 +DTLB_ENTRIES 32'd16 + +# Feature variants + +deriv misaligned_rv32gc rv32gc +ZICCLSM_SUPPORTED 1 + +deriv nomisaligned_rv64gc rv64gc +ZICCLSM_SUPPORTED 0 + +deriv nobigendian_rv32gc rv32gc +BIGENDIAN_SUPPORTED 0 + +deriv nobigendian_rv64gc rv64gc +BIGENDIAN_SUPPORTED 0 + +# Floating-point modes supported + +deriv f_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fd_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdq_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdqh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv f_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fh_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fd_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdqh_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +# IEEE compatible variants for TestFloat + +deriv f_ieee_rv32gc f_rv32gc +IEEE754 1 + +deriv fh_ieee_rv32gc fh_rv32gc +IEEE754 1 + +deriv fd_ieee_rv32gc fd_rv32gc +IEEE754 1 + +deriv fdh_ieee_rv32gc fdh_rv32gc +IEEE754 1 + +deriv fdq_ieee_rv32gc fdq_rv32gc +IEEE754 1 + +deriv fdqh_ieee_rv32gc fdqh_rv32gc +IEEE754 1 + +deriv f_ieee_rv64gc f_rv64gc +IEEE754 1 + +deriv fh_ieee_rv64gc fh_rv64gc +IEEE754 1 + +deriv fd_ieee_rv64gc fd_rv64gc +IEEE754 1 + +deriv fdq_ieee_rv64gc fdq_rv64gc +IEEE754 1 + +deriv fdqh_ieee_rv64gc fdqh_rv64gc +IEEE754 1 + +#### MORE DIVIDER variants + +#### F_only, RK variable +deriv f_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + + +#### FH_only, RK variable +deriv fh_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +# FD only , rk variable + +deriv fd_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + + +# FDH only , rk variable + +deriv fdh_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +# FDQ only , rk variable + +deriv fdq_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +# FDQH only , rk variable + +deriv fdqh_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +#### DIVIDER VARIANTS WITH IEEE + +deriv f_ieee_div_2_1_rv32gc f_div_2_1_rv32gc +IEEE754 1 + +deriv f_ieee_div_2_2_rv32gc f_div_2_2_rv32gc +IEEE754 1 + +deriv f_ieee_div_2_4_rv32gc f_div_2_4_rv32gc +IEEE754 1 + +deriv f_ieee_div_4_1_rv32gc f_div_4_1_rv32gc +IEEE754 1 + +deriv f_ieee_div_4_2_rv32gc f_div_4_2_rv32gc +IEEE754 1 + +deriv f_ieee_div_2_1_rv64gc f_div_2_1_rv64gc +IEEE754 1 + +deriv f_ieee_div_2_2_rv64gc f_div_2_2_rv64gc +IEEE754 1 + +deriv f_ieee_div_2_4_rv64gc f_div_2_4_rv64gc +IEEE754 1 + +deriv f_ieee_div_4_1_rv64gc f_div_4_1_rv64gc +IEEE754 1 + +deriv f_ieee_div_4_2_rv64gc f_div_4_2_rv64gc +IEEE754 1 + +deriv f_ieee_div_4_4_rv64gc f_div_4_4_rv64gc +IEEE754 1 + +#### FH_only, RK variable +deriv fh_ieee_div_2_1_rv32gc fh_div_2_1_rv32gc +IEEE754 1 + +deriv fh_ieee_div_2_2_rv32gc fh_div_2_2_rv32gc +IEEE754 1 + +deriv fh_ieee_div_2_4_rv32gc fh_div_2_4_rv32gc +IEEE754 1 + +deriv fh_ieee_div_4_1_rv32gc fh_div_4_1_rv32gc +IEEE754 1 + +deriv fh_ieee_div_4_2_rv32gc fh_div_4_2_rv32gc +IEEE754 1 + +deriv fh_ieee_div_2_1_rv64gc fh_div_2_1_rv64gc +IEEE754 1 + +deriv fh_ieee_div_2_2_rv64gc fh_div_2_2_rv64gc +IEEE754 1 + +deriv fh_ieee_div_2_4_rv64gc fh_div_2_4_rv64gc +IEEE754 1 + +deriv fh_ieee_div_4_1_rv64gc fh_div_4_1_rv64gc +IEEE754 1 + +deriv fh_ieee_div_4_2_rv64gc fh_div_4_2_rv64gc +IEEE754 1 + +deriv fh_ieee_div_4_4_rv64gc fh_div_4_4_rv64gc +IEEE754 1 +# FD only , rk variable + +deriv fd_ieee_div_2_1_rv32gc fd_div_2_1_rv32gc +IEEE754 1 + +deriv fd_ieee_div_2_2_rv32gc fd_div_2_2_rv32gc +IEEE754 1 + +deriv fd_ieee_div_2_4_rv32gc fd_div_2_4_rv32gc +IEEE754 1 + +deriv fd_ieee_div_4_1_rv32gc fd_div_4_1_rv32gc +IEEE754 1 + +deriv fd_ieee_div_4_2_rv32gc fd_div_4_2_rv32gc +IEEE754 1 + +deriv fd_ieee_div_2_1_rv64gc fd_div_2_1_rv64gc +IEEE754 1 + +deriv fd_ieee_div_2_2_rv64gc fd_div_2_2_rv64gc +IEEE754 1 + +deriv fd_ieee_div_2_4_rv64gc fd_div_2_4_rv64gc +IEEE754 1 + +deriv fd_ieee_div_4_1_rv64gc fd_div_4_1_rv64gc +IEEE754 1 + +deriv fd_ieee_div_4_2_rv64gc fd_div_4_2_rv64gc +IEEE754 1 + +deriv fd_ieee_div_4_4_rv64gc fd_div_4_4_rv64gc +IEEE754 1 + +# FDH only , rk variable + +deriv fdh_ieee_div_2_1_rv32gc fdh_div_2_1_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_2_2_rv32gc fdh_div_2_2_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_2_4_rv32gc fdh_div_2_4_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_4_1_rv32gc fdh_div_4_1_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_4_2_rv32gc fdh_div_4_2_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_2_1_rv64gc fdh_div_2_1_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_2_2_rv64gc fdh_div_2_2_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_2_4_rv64gc fdh_div_2_4_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_4_1_rv64gc fdh_div_4_1_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_4_2_rv64gc fdh_div_4_2_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_4_4_rv64gc fdh_div_4_4_rv64gc +IEEE754 1 +# FDQ only , rk variable + +deriv fdq_ieee_div_2_1_rv32gc fdq_div_2_1_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_2_2_rv32gc fdq_div_2_2_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_2_4_rv32gc fdq_div_2_4_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_4_1_rv32gc fdq_div_4_1_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_4_2_rv32gc fdq_div_4_2_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_2_1_rv64gc fdq_div_2_1_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_2_2_rv64gc fdq_div_2_2_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_2_4_rv64gc fdq_div_2_4_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_4_1_rv64gc fdq_div_4_1_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_4_2_rv64gc fdq_div_4_2_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_4_4_rv64gc fdq_div_4_4_rv64gc +IEEE754 1 + +# FDQH only , rk variable + +deriv fdqh_ieee_div_2_1_rv32gc fdqh_div_2_1_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_2_2_rv32gc fdqh_div_2_2_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_2_4_rv32gc fdqh_div_2_4_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_4_1_rv32gc fdqh_div_4_1_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_4_2_rv32gc fdqh_div_4_2_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_2_1_rv64gc fdqh_div_2_1_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_2_2_rv64gc fdqh_div_2_2_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_2_4_rv64gc fdqh_div_2_4_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_4_1_rv64gc fdqh_div_4_1_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_4_2_rv64gc fdqh_div_4_2_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_4_4_rv64gc fdqh_div_4_4_rv64gc +IEEE754 1 + + diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 70d455b4e..9f0056fad 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -132,6 +132,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 0; @@ -154,6 +158,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 4baef0075..843f55530 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -133,6 +133,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -150,22 +154,12 @@ localparam PLIC_SPI_ID = 32'd6; localparam PLIC_SDC_ID = 32'd9; localparam BPRED_SUPPORTED = 1; -// this is an annoying hack for the branch predictor parameterization override. -`ifdef BPRED_OVERRIDE -localparam BPRED_TYPE = `BPRED_TYPE; -localparam BPRED_SIZE = `BPRED_SIZE; -`else localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT localparam BPRED_SIZE = 32'd10; -`endif localparam BPRED_NUM_LHR = 32'd6; -`ifdef BTB_OVERRIDE -localparam BTB_SIZE = `BTB_SIZE; -localparam RAS_SIZE = `RAS_SIZE; -`else localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -`endif +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 6e5d08803..81b25bc2b 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -132,6 +132,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -155,6 +159,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index a32dc3bd6..931725cc4 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -131,6 +131,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -153,6 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh deleted file mode 100644 index 09885808f..000000000 --- a/config/rv64fpquad/config.vh +++ /dev/null @@ -1,182 +0,0 @@ -////////////////////////////////////////// -// config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "BranchPredictorType.vh" - -// RV32 or RV64: XLEN = 32 or 64 -localparam XLEN = 32'd64; - -// IEEE 754 compliance -localparam IEEE754 = 1; - -// MISA RISC-V configuration per specification -localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ); -localparam ZICSR_SUPPORTED = 1; -localparam ZIFENCEI_SUPPORTED = 1; -localparam COUNTERS = 12'd32; -localparam ZICNTR_SUPPORTED = 1; -localparam ZIHPM_SUPPORTED = 1; -localparam ZFH_SUPPORTED = 1; -localparam ZFA_SUPPORTED = 0; -localparam SSTC_SUPPORTED = 0; -localparam ZICBOM_SUPPORTED = 0; -localparam ZICBOZ_SUPPORTED = 0; -localparam ZICBOP_SUPPORTED = 0; -localparam ZICCLSM_SUPPORTED = 0; -localparam ZICOND_SUPPORTED = 0; -localparam SVPBMT_SUPPORTED = 0; -localparam SVNAPOT_SUPPORTED = 0; -localparam SVINVAL_SUPPORTED = 1; - -// LSU microarchitectural Features -localparam BUS_SUPPORTED = 1; -localparam DCACHE_SUPPORTED = 1; -localparam ICACHE_SUPPORTED = 1; -localparam VIRTMEM_SUPPORTED = 1; -localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ; -localparam BIGENDIAN_SUPPORTED = 1; - -// TLB configuration. Entries should be a power of 2 -localparam ITLB_ENTRIES = 32'd32; -localparam DTLB_ENTRIES = 32'd32; - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -localparam DCACHE_NUMWAYS = 32'd4; -localparam DCACHE_WAYSIZEINBYTES = 32'd4096; -localparam DCACHE_LINELENINBITS = 32'd512; -localparam ICACHE_NUMWAYS = 32'd4; -localparam ICACHE_WAYSIZEINBYTES = 32'd4096; -localparam ICACHE_LINELENINBITS = 32'd512; -localparam CACHE_SRAMLEN = 32'd128; - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -localparam IDIV_BITSPERCYCLE = 32'd4; -localparam IDIV_ON_FPU = 1; - -// Legal number of PMP entries are 0, 16, or 64 -localparam PMP_ENTRIES = 32'd16; - -// Address space -localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; - -// Bus Interface width -localparam AHBW = 32'd64; - -// WFI Timeout Wait -localparam WFI_TIMEOUT_BIT = 32'd16; - -// Peripheral Physiccal Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -localparam DTIM_SUPPORTED = 1'b0; -localparam logic [63:0] DTIM_BASE = 64'h80000000; -localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; -localparam IROM_SUPPORTED = 1'b0; -localparam logic [63:0] IROM_BASE = 64'h80000000; -localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; -localparam BOOTROM_SUPPORTED = 1'b1; -localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; -localparam UNCORE_RAM_SUPPORTED = 1'b1; -localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; -localparam EXT_MEM_SUPPORTED = 1'b0; -localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; -localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; -localparam CLINT_SUPPORTED = 1'b1; -localparam logic [63:0] CLINT_BASE = 64'h02000000; -localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; -localparam GPIO_SUPPORTED = 1'b1; -localparam logic [63:0] GPIO_BASE = 64'h10060000; -localparam logic [63:0] GPIO_RANGE = 64'h000000FF; -localparam UART_SUPPORTED = 1'b1; -localparam logic [63:0] UART_BASE = 64'h10000000; -localparam logic [63:0] UART_RANGE = 64'h00000007; -localparam PLIC_SUPPORTED = 1'b1; -localparam logic [63:0] PLIC_BASE = 64'h0C000000; -localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; -localparam SDC_SUPPORTED = 1'b0; -localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; -localparam SPI_SUPPORTED = 1'b1; -localparam logic [63:0] SPI_BASE = 64'h10040000; -localparam logic [63:0] SPI_RANGE = 64'h00000FFF; - -// Test modes - -// Tie GPIO outputs back to inputs -localparam GPIO_LOOPBACK_TEST = 1; -localparam SPI_LOOPBACK_TEST = 1; - -// Hardware configuration -localparam UART_PRESCALE = 32'd1; - -// Interrupt configuration -localparam PLIC_NUM_SRC = 32'd10; -// comment out the following if >=32 sources -localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); -localparam PLIC_GPIO_ID = 32'd3; -localparam PLIC_UART_ID = 32'd10; -localparam PLIC_SPI_ID = 32'd6; -localparam PLIC_SDC_ID = 32'd9; - -localparam BPRED_SUPPORTED = 1; -localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -localparam BPRED_SIZE = 32'd10; -localparam BPRED_NUM_LHR = 32'd6; -localparam BTB_SIZE = 32'd10; -localparam RAS_SIZE = 32'd16; - -localparam SVADU_SUPPORTED = 0; -localparam ZMMUL_SUPPORTED = 0; - -// FPU division architecture -localparam RADIX = 32'h4; -localparam DIVCOPIES = 32'h4; - -// bit manipulation -localparam ZBA_SUPPORTED = 0; -localparam ZBB_SUPPORTED = 0; -localparam ZBC_SUPPORTED = 0; -localparam ZBS_SUPPORTED = 0; - -// New compressed instructions -localparam ZCB_SUPPORTED = 0; -localparam ZCA_SUPPORTED = 0; -localparam ZCF_SUPPORTED = 0; -localparam ZCD_SUPPORTED = 0; - -// Memory synthesis configuration -localparam USE_SRAM = 0; - -`include "config-shared.vh" diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index bb3e79659..7f038d87e 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -41,7 +41,7 @@ localparam COUNTERS = 12'd32; localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; localparam ZFH_SUPPORTED = 1; -localparam ZFA_SUPPORTED = 0; +localparam ZFA_SUPPORTED = 1; localparam SSTC_SUPPORTED = 1; localparam ZICBOM_SUPPORTED = 1; localparam ZICBOZ_SUPPORTED = 1; @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6; localparam BPRED_SIZE = 32'd10; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; @@ -180,3 +185,4 @@ localparam ZCD_SUPPORTED = 0; localparam USE_SRAM = 0; `include "config-shared.vh" + diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 609a50f97..4dd540a9f 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 5dfb4b1ba..dd766f2fd 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -94,7 +94,7 @@ localparam LOGR = $clog2(RADIX); // r = log(R localparam RK = LOGR*DIVCOPIES; // r*k bits per cycle generated // intermediate division parameters not directly used in fdivsqrt hardware -localparam FPDIVMINb = NF + 3; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right +localparam FPDIVMINb = NF + 2; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right //localparam FPDIVMINb = NF + 2 + (RADIX == 2); // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit for preshifting radix2 square root right, if radix4 doesn't use a right shift. This version saves one cycle on double-precision with R=4,k=4. However, it doesn't work yet because C is too short, so k is incorrectly calculated as a 1 in the lsb after the last step. localparam DIVMINb = ((FPDIVMINb(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6))); +localparam NORMSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6))); // max(CVTLEN+NF+1, DIVb + 1 + NF + 1, 3*NF+6) localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); -localparam CORRSHIFTSZ = NORMSHIFTSZ-2; +localparam CORRSHIFTSZ = (NORMSHIFTSZ-2 > (DIVMINb + 1 + NF)) ? NORMSHIFTSZ-2 : (DIVMINb+1+NF); // max(NORMSHIFTSZ-2, DIVMINb + 1 + NF) // Disable spurious Verilator warnings diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 7dc0a0bcf..464e3c0f9 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -8,6 +8,8 @@ localparam cvw_t P = '{ IEEE754 : IEEE754, MISA : MISA, AHBW : AHBW, + RAM_LATENCY : RAM_LATENCY, + BURST_EN : BURST_EN, ZICSR_SUPPORTED : ZICSR_SUPPORTED, ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED, COUNTERS : COUNTERS, @@ -100,6 +102,7 @@ localparam cvw_t P = '{ BPRED_NUM_LHR : BPRED_NUM_LHR, BTB_SIZE : BTB_SIZE, RAS_SIZE : RAS_SIZE, + INSTR_CLASS_PRED : INSTR_CLASS_PRED, RADIX : RADIX, DIVCOPIES : DIVCOPIES, ZBA_SUPPORTED : ZBA_SUPPORTED, diff --git a/docs/Dockerfile b/docs/Dockerfile index b06f9ad67..8df933363 100755 --- a/docs/Dockerfile +++ b/docs/Dockerfile @@ -7,6 +7,7 @@ ## Purpose: Dockerfile for Wally docker container creation ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 179926218..e6807a6a6 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -48,29 +48,14 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \ PreProcessFiles: + $(MAKE) -C ../../sim deriv rm -rf ../src/CopiedFiles_do_not_add_to_repo/ cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/ mkdir ../src/CopiedFiles_do_not_add_to_repo/config/ - cp ../../config/rv64gc/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/ + cp ../../config/deriv/fpga/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/ ./insert_debug_comment.sh # modify config *** RT: eventually setup for variably defined sized memory - sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 64'h00000FFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/UNCORE_RAM_PRELOAD.*/UNCORE_RAM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/EXT_MEM_SUPPORTED.*/EXT_MEM_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/SDC_SUPPORTED.*/SDC_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/SPI_SUPPORTED.*/SPI_SUPPORTED = 1'b0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # *** RT: Add SPI when ready - sed -i "s/GPIO_LOOPBACK_TEST.*/GPIO_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/SPI_LOOPBACK_TEST.*/SPI_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/UART_PRESCALE.*/UART_PRESCALE = 32'd0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/PLIC_NUM_SRC = .*/PLIC_NUM_SRC = 32'd53;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/PLIC_SDC_ID.*/PLIC_SDC_ID = 32'd20;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/BPRED_SIZE.*/BPRED_SIZE = 32'd12;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh - sed -i "s/$\$readmemh.*/$\$readmemh(\"..\/..\/..\/fpga\/src\/boot.mem\", ROM, 0);/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv + #sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # This line allows the Bootloader to be loaded in a Block RAM on the FPGA sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh index 66c232e16..35fa05a02 100755 --- a/fpga/generator/insert_debug_comment.sh +++ b/fpga/generator/insert_debug_comment.sh @@ -7,6 +7,7 @@ ## Modified: 20 January 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/probe b/fpga/probe index 21e5d8240..1cf1104c1 100755 --- a/fpga/probe +++ b/fpga/probe @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/proberange b/fpga/proberange index 715cba46e..73bfc3383 100755 --- a/fpga/proberange +++ b/fpga/proberange @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/probes b/fpga/probes index 83c2ddf7c..1ea571057 100755 --- a/fpga/probes +++ b/fpga/probes @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/tests/custom/zsbl/Makefile b/fpga/zsbl/Makefile similarity index 98% rename from tests/custom/zsbl/Makefile rename to fpga/zsbl/Makefile index 6dec9c797..bd30033fc 100644 --- a/tests/custom/zsbl/Makefile +++ b/fpga/zsbl/Makefile @@ -21,7 +21,7 @@ ROOT := .. LIBRARY_DIRS := LIBRARY_FILES := -MARCH :=-march=rv64imfdc +MARCH :=-march=rv64imfdc_zifencei MABI :=-mabi=lp64d LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles LINKER :=linker.x diff --git a/tests/custom/zsbl/bios.s b/fpga/zsbl/bios.s similarity index 97% rename from tests/custom/zsbl/bios.s rename to fpga/zsbl/bios.s index ebeadcf59..7954eab7a 100644 --- a/tests/custom/zsbl/bios.s +++ b/fpga/zsbl/bios.s @@ -94,5 +94,5 @@ end_of_bios: .globl _dtb .align 4, 0 _dtb: -.incbin "wally-vcu118.dtb" +#.incbin "wally-vcu118.dtb" diff --git a/tests/custom/zsbl/copyFlash.c b/fpga/zsbl/copyFlash.c similarity index 100% rename from tests/custom/zsbl/copyFlash.c rename to fpga/zsbl/copyFlash.c diff --git a/tests/custom/zsbl/gpt.c b/fpga/zsbl/gpt.c similarity index 100% rename from tests/custom/zsbl/gpt.c rename to fpga/zsbl/gpt.c diff --git a/tests/custom/zsbl/gpt.h b/fpga/zsbl/gpt.h similarity index 100% rename from tests/custom/zsbl/gpt.h rename to fpga/zsbl/gpt.h diff --git a/tests/custom/zsbl/main.c b/fpga/zsbl/main.c similarity index 100% rename from tests/custom/zsbl/main.c rename to fpga/zsbl/main.c diff --git a/tests/custom/zsbl/sdcDriver.c b/fpga/zsbl/sdcDriver.c similarity index 98% rename from tests/custom/zsbl/sdcDriver.c rename to fpga/zsbl/sdcDriver.c index edbe0677d..45caa42fa 100644 --- a/tests/custom/zsbl/sdcDriver.c +++ b/fpga/zsbl/sdcDriver.c @@ -1,7 +1,7 @@ /////////////////////////////////////////// // SDC.sv // -// Written: Ross Thompson September 25, 2021 +// Written: Rose Thompson September 25, 2021 // Modified: // // Purpose: driver for sdc reader. diff --git a/tests/custom/zsbl/sdcDriver.h b/fpga/zsbl/sdcDriver.h similarity index 100% rename from tests/custom/zsbl/sdcDriver.h rename to fpga/zsbl/sdcDriver.h diff --git a/tests/custom/zsbl/smp.h b/fpga/zsbl/smp.h similarity index 100% rename from tests/custom/zsbl/smp.h rename to fpga/zsbl/smp.h diff --git a/tests/custom/zsbl/uart.c b/fpga/zsbl/uart.c similarity index 100% rename from tests/custom/zsbl/uart.c rename to fpga/zsbl/uart.c diff --git a/tests/custom/zsbl/uart.h b/fpga/zsbl/uart.h similarity index 100% rename from tests/custom/zsbl/uart.h rename to fpga/zsbl/uart.h diff --git a/gitflow.txt b/gitflow.txt index 57300830a..f6f70de74 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -1,5 +1,6 @@ ########################################### ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/linux/sdcard/flash-sd.sh b/linux/sdcard/flash-sd.sh index 73c9e1b9e..a636f3d60 100755 --- a/linux/sdcard/flash-sd.sh +++ b/linux/sdcard/flash-sd.sh @@ -72,6 +72,13 @@ if [ ! -e "$SDCARD" ] ; then exit 1 fi +# Prefix partition with "p" for non-SCSI disks (mmcblk, nvme) +if [[ $SDCARD == "/dev/sd"* ]]; then + $PART_PREFIX="" +else + $PART_PREFIX="p" +fi + # If no images directory, images have not been built if [ ! -d $IMAGES ] ; then echo -e "$ERRORTEXT Buildroot images directory does not exist" @@ -155,18 +162,18 @@ if [[ $REPLY =~ ^[Yy]$ ]] ; then DD_FLAGS="bs=4k iflag=fullblock oflag=direct conv=fsync status=progress" echo -e "$NAME Copying device tree" - sudo dd if=$DEVICE_TREE of="$SDCARD"1 $DD_FLAGS + sudo dd if=$DEVICE_TREE of="$SDCARD""$PART_PREFIX"1 $DD_FLAGS echo -e "$NAME Copying OpenSBI" - sudo dd if=$FW_JUMP of="$SDCARD"2 $DD_FLAGS + sudo dd if=$FW_JUMP of="$SDCARD""$PART_PREFIX"2 $DD_FLAGS echo -e "$NAME Copying Kernel" - sudo dd if=$LINUX_KERNEL of="$SDCARD"3 $DD_FLAGS + sudo dd if=$LINUX_KERNEL of="$SDCARD""$PART_PREFIX"3 $DD_FLAGS - sudo mkfs.ext4 "$SDCARD"4 + sudo mkfs.ext4 "$SDCARD""$PART_PREFIX"4 sudo mkdir /mnt/$MNT_DIR - sudo mount -v "$SDCARD"4 /mnt/$MNT_DIR + sudo mount -v "$SDCARD""$PART_PREFIX"4 /mnt/$MNT_DIR sudo umount -v /mnt/$MNT_DIR diff --git a/sim/Makefile b/sim/Makefile index 5889d1df9..b23d1cb47 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,5 +1,5 @@ -all: riscoftests memfiles coveragetests +all: riscoftests memfiles coveragetests deriv benchmarks # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired @@ -54,9 +54,19 @@ riscoftests: wallyriscoftests: # Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions make -C ../tests/riscof/ wally-riscv-arch-test - + memfiles: make -f makefile-memfile wally-sim-files --jobs coveragetests: make -C ../tests/coverage/ --jobs + +deriv: + derivgen.pl + +benchmarks: + $(MAKE) -C ../benchmarks/embench build + $(MAKE) -C ../benchmarks/embench size + $(MAKE) -C ../benchmarks/embench modelsim_build_memfile + $(MAKE) -C ../benchmarks/coremark + diff --git a/sim/bp-results/branch-list.txt b/sim/bp-results/branch-list.txt index 956fc9847..10827b3b9 100644 --- a/sim/bp-results/branch-list.txt +++ b/sim/bp-results/branch-list.txt @@ -1,12 +1,12 @@ -../logs/rv32gc_gshare6.log gshare 6 -../logs/rv32gc_gshare8.log gshare 8 -../logs/rv32gc_gshare10.log gshare 10 -../logs/rv32gc_gshare12.log gshare 12 -../logs/rv32gc_gshare14.log gshare 14 -../logs/rv32gc_gshare16.log gshare 16 -../logs/rv32gc_twobit6.log twobit 6 -../logs/rv32gc_twobit8.log twobit 8 -../logs/rv32gc_twobit10.log twobit 10 -../logs/rv32gc_twobit12.log twobit 12 -../logs/rv32gc_twobit14.log twobit 14 -../logs/rv32gc_twobit16.log twobit 16 +../logs/bpred_GSHARE_6_16_10_0_rv32gc_embench.log gshare 6 +../logs/bpred_GSHARE_8_16_10_0_rv32gc_embench.log gshare 8 +../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log gshare 10 +../logs/bpred_GSHARE_12_16_10_0_rv32gc_embench.log gshare 12 +../logs/bpred_GSHARE_14_16_10_0_rv32gc_embench.log gshare 14 +../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log gshare 16 +../logs/bpred_TWOBIT_6_16_10_0_rv32gc_embench.log twobit 6 +../logs/bpred_TWOBIT_8_16_10_0_rv32gc_embench.log twobit 8 +../logs/bpred_TWOBIT_10_16_10_0_rv32gc_embench.log twobit 10 +../logs/bpred_TWOBIT_12_16_10_0_rv32gc_embench.log twobit 12 +../logs/bpred_TWOBIT_14_16_10_0_rv32gc_embench.log twobit 14 +../logs/bpred_TWOBIT_16_16_10_0_rv32gc_embench.log twobit 16 diff --git a/sim/bp-results/btb-list.txt b/sim/bp-results/btb-list.txt index 30811459e..a4671ba9f 100644 --- a/sim/bp-results/btb-list.txt +++ b/sim/bp-results/btb-list.txt @@ -1,6 +1,6 @@ -../logs/rv32gc_BTB6.log btb 6 -../logs/rv32gc_BTB8.log btb 8 -../logs/rv32gc_BTB10.log btb 10 -../logs/rv32gc_BTB12.log btb 12 -../logs/rv32gc_BTB14.log btb 14 -../logs/rv32gc_BTB16.log btb 16 +../logs/bpred_GSHARE_16_16_6_0_rv32gc_embench.log btb 6 +../logs/bpred_GSHARE_16_16_8_0_rv32gc_embench.log btb 8 +../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log btb 10 +../logs/bpred_GSHARE_16_16_12_0_rv32gc_embench.log btb 12 +../logs/bpred_GSHARE_16_16_14_0_rv32gc_embench.log btb 14 +../logs/bpred_GSHARE_16_16_16_0_rv32gc_embench.log btb 16 diff --git a/sim/bp-results/class-list.txt b/sim/bp-results/class-list.txt index 3926af969..0be63e91a 100644 --- a/sim/bp-results/class-list.txt +++ b/sim/bp-results/class-list.txt @@ -1,6 +1,6 @@ -../logs/rv32gc_class6.log class 6 -../logs/rv32gc_class8.log class 8 -../logs/rv32gc_class10.log class 10 -../logs/rv32gc_class12.log class 12 -../logs/rv32gc_class14.log class 14 -../logs/rv32gc_class16.log class 16 +../logs/bpred_GSHARE_16_16_6_1_rv32gc_embench.log btb 6 +../logs/bpred_GSHARE_16_16_8_1_rv32gc_embench.log btb 8 +../logs/bpred_GSHARE_16_16_10_1_rv32gc_embench.log btb 10 +../logs/bpred_GSHARE_16_16_12_1_rv32gc_embench.log btb 12 +../logs/bpred_GSHARE_16_16_14_1_rv32gc_embench.log btb 14 +../logs/bpred_GSHARE_16_16_16_1_rv32gc_embench.log btb 16 diff --git a/sim/bp-results/ras-list.txt b/sim/bp-results/ras-list.txt index c7628ffaa..c9246b14d 100644 --- a/sim/bp-results/ras-list.txt +++ b/sim/bp-results/ras-list.txt @@ -1,5 +1,5 @@ -../logs/rv32gc_RAS3.log ras 3 -../logs/rv32gc_RAS4.log ras 4 -../logs/rv32gc_RAS6.log ras 6 -../logs/rv32gc_RAS10.log ras 10 -../logs/rv32gc_RAS16.log ras 16 +../logs/bpred_GSHARE_10_3_10_0_rv32gc_embench.log ras 3 +../logs/bpred_GSHARE_10_4_10_0_rv32gc_embench.log ras 4 +../logs/bpred_GSHARE_10_6_10_0_rv32gc_embench.log ras 6 +../logs/bpred_GSHARE_10_10_10_0_rv32gc_embench.log ras 10 +../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log ras 16 diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index b9c20eead..36098d90d 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -7,6 +7,7 @@ #// For example, signals hardwired to 0 should not be checked for toggle coverage #// #// A component of the CORE-V-WALLY configurable RISC-V project. +#// https://github.com/openhwgroup/cvw #// #// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University #// @@ -34,21 +35,39 @@ do GetLineNum.do # DH 4/22/23: Exclude all LZAs coverage exclude -srcfile lzc.sv +################# +# FPU Exclusions +################# # DH 4/22/23: FDIVSQRT can't go directly from done to busy again coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY # DH 4/22/23: The busy->idle transition only occurs if a FlushE occurs while the divider is busy. The flush is caused by a trap or return, # which won't happen while the divider is busy. coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state BUSY->IDLE +# All Memory-stage stalls have resolved by time fdivsqrt finishes regular operation in this configuration, so can't test StallM +coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ../src/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item b 1 +coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ../src/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item s 1 +# Division by zero never sets sticky/guard/overflow/round to cause inexact or underflow result, but check out of paranoia +coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign FpInexact"] -item e 1 -fecexprrow 15 +coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22 +# Convert int to fp will never underflow +coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ../src/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4 + +################## +# Cache Exclusions +################## ### Exclude D$ states and logic for the I$ instance # This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too) # Also exclude the write line to ready transition for the I$ since we can't get a flush during this operation. coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY STATE_FETCH->STATE_READY # exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work. coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1 +# I$ does not flush +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FlushCache"] -item e 1 -fecexprrow 2 # exclude branch/condition coverage: LineDirty if statement coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FLUSHStatement"] -item bs 1 # exclude the unreachable logic set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache case"] set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache case"] @@ -67,7 +86,9 @@ set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache flushdir coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"] coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrTag"] -item e 1 -fecexprrow 8 coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12 + # cache.sv AdrSelMuxData and AdrSelMuxTag and CacheBusAdrMux, excluding unhit Flush branch coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxData -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxTag -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 @@ -79,7 +100,33 @@ for {set i 0} {$i < $numcacheways} {incr i} { coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6 # below: flushD can't go high during an icache write b/c of pipeline stall coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4 + # No CMO to clear valid bits of I$ + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"] + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1 + # No dirty ways in read-only I$ + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1 } +# I$ buscachefsm does not perform atomics or write/writeback; HREADY is always 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicReadData"] +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicPhase"] +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item bs 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item b 2 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item s 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"] +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback2"] -item bs 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item bs 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item bs 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADYread"] -item c 1 -feccondrow 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item c 1 -feccondrow 1,2,3,4,6 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item c 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item c 1 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign HTRANS"] -item c 1 -feccondrow 5 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BeatCntEn"] -item e 1 -fecexprrow 4 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheAccess"] -item e 1 -fecexprrow 4 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BusStall"] -item e 1 -fecexprrow 10,12,18 +coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 3 ## D$ Exclusions. # InvalidateCache is I$ only: @@ -90,13 +137,17 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get set numcacheways 4 for {set i 0} {$i < $numcacheways} {incr i} { coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4 + # InvalidateCacheDelay is always 0 for D$ because it is flushed, not invalidated + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2 # FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before # going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW. coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4 +# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6 } # D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush -coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY +coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY #################### # Unused / illegal peripheral accesses @@ -112,7 +163,13 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/iromdec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec -# PMA Regions 8, 9, and 10 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage +# PMA Regions 1, 2, and 3 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 @@ -121,11 +178,17 @@ coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$lin coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8 # Excluding so far un-used instruction sources for the ifu -# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec -# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/spidec -#Excluding the bootrom, uncoreran, and clint as sources for the lsu -# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec +# The following peripherals are always supported +set line [GetLineNum ../src/mmu/adrdec.sv "exclusion-tag: adrdecSel"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec -linerange $line-$line -item e 1 -fecexprrow 3,7 +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3 +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3 +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -linerange $line-$line -item e 1 -fecexprrow 3 +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/spidec -linerange $line-$line -item e 1 -fecexprrow 3 #Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] @@ -134,22 +197,15 @@ set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5 # set line [GetLineNum ../src/mmu/adrdec.sv "& Supported"] -# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/dtimdec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/iromdec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec -linerange $line-$line -item e 1 -fecexprrow 3 -# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec -linerange $line-$line -item e 1 -fecexprrow 3 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec +# No DTIM or IROM +coverage exclude -scope /dut/core/ifu/bus/icache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 +coverage exclude -scope /dut/core/lsu/bus/dcache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 + #################### # Unused access types due to sharing IFU and LSU logic #################### @@ -192,6 +248,10 @@ set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4 set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4 +set line [GetLineNum ../src/mmu/mmu.sv "assign AmoAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 +set line [GetLineNum ../src/mmu/mmu.sv "assign AmoMisalignedCausesAccessFaultM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] @@ -224,6 +284,44 @@ coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1 coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1 +# IMMU never disables translations +coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign Translate"] -item e 1 -fecexprrow 2 +coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign UpdateDA"] -item e 1 -fecexprrow 5 +# never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first +coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18 + + + + +############### +# HPTW exclusions +############### + +# RV64GC HPTW never starts at L1_ADR +set line [GetLineNum ../src/mmu/hptw.sv "InitialWalkerState == L1_ADR"] +coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item c 1 -feccondrow 2 + +# Never possible to get a page fault when neither reading nor writing +set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWLoadPageFault"] +coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 7 + +# Never possible to get a store page fault from an ITLB walk +set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWStoreAmoPageFault"] +coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3 + +# Never possible to get Access = 0 on a nonleaf PTE with no OtherPageFault (because InvalidRead/Write will be 1 on the nonleaf) +set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWUpdateDA"] +coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3 + +############### +# Other exclusions +############### + +# IMMU PMP does not support CBO instructions +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"] + # No irom set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"] coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6 @@ -246,6 +344,56 @@ coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item set line [GetLineNum ../src/ebu/ebufsmarb.sv "FinalBeatReg\\("] coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1 +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1 + +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1 + +# The WritebackWriteback and FetchWriteback support back to back pipelined cache writebacks and fetch then +# writebacks. The cache never issues these type of requests. +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2 + +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2 + +# FetchWait never occurs because HREADY is never 0. +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1 + +# all of these HREADY exclusions occur because HREADY is always 1. The ram_ahb module never stalls. +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 + +#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"] +#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 + +#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"] +#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 + +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 4 + +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 3 + +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 + +set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1 +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 5 + +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 5 + +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1 +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item s 1 + +# these transitions will not happen +coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -ftrans CurrState DATA_PHASE->ADR_PHASE ATOMIC_READ_DATA_PHASE->ADR_PHASE ATOMIC_PHASE->ADR_PHASE + # TLB not recently used never has all RU bits = 1 because it will then clear all to 0 # This is a blunt instrument; perhaps there is a more graceful exclusion coverage exclude -srcfile priorityonehot.sv @@ -254,9 +402,20 @@ coverage exclude -srcfile priorityonehot.sv coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1 +#################### +# Privileged +#################### + +# Instruction Misaligned never asserted because compresssed instructions are accepted +coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ../src/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2 + #################### # EBU #################### -# Exclude EBU Beat Counter because it is only idle when bus has multicycle latency, but rv64gc has single cycle latency -coverage exclude -scope /core/ebu/ebu/ebufsmarb/BeatCounter +# Exclude EBU Beat Counter flop because it is only idle when bus has multicycle latency, but rv64gc has single cycle latency +coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb/BeatCounter/cntrflop + + + + diff --git a/sim/imperas.ic b/sim/imperas.ic index b35166429..51344b75a 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -11,6 +11,7 @@ --override cpu/mvendorid=0x602 --override cpu/marchid=0x24 --override refRoot/cpu/tvec_align=64 +--override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written # bit manipulation --override cpu/add_Extensions=B @@ -21,6 +22,7 @@ --override cpu/Zcb=T --override cpu/Zicond=T --override cpu/Zfh=T +--override cpu/Zfa=T # Cache block operations --override cpu/Zicbom=T @@ -95,6 +97,7 @@ --callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0 error - 0x10000000 - 0x100000FF --callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO error - 0x10069000 - 0x100600FF --callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI error - 0x10040000 - 0x10040FFF +#--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwxaA- 1248 " # UNCORE_RAM --callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM # Enable the Imperas instruction coverage diff --git a/sim/lint-wally b/sim/lint-wally index eb6ad62b0..5964d20ed 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -1,19 +1,48 @@ #!/bin/bash # check for warnings in Verilog code -# The verilator lint tool is faster and better than Modelsim so it is best to run this first. +# The verilator lint tool is faster and better than Questa so it is best to run this first. + export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do -#for config in rv64gc; do - echo "$config linting..." - if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then - echo "Exiting after $config lint due to errors or warnings" - exit 1 +RED='\033[0;31m' +GREEN='\033[0;32m' +NC='\033[0m' # No Color +fails=0 + +if [ "$1" == "-nightly" ]; then + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc + derivconfigs=`ls $WALLY/config/deriv` + for entry in $derivconfigs + do + if [[ $entry != *"syn_sram"* ]]; then # ignore syn_sram* configs that contain undefined module + configs[${#configs[@]}]=$entry + fi + done +else + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i div_2_1i_rv64gc ) # add fdqh_rv64gc when working +fi + +for config in ${configs[@]}; do +# echo "$config linting..." + if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if [ "$1" == "-nightly" ]; then + echo -e "${RED}$config failed lint${NC}" + fails=$((fails+1)) + else + echo -e "${RED}$config fails with lint errors or warnings" + exit 1 + fi + else + echo -e "${GREEN}$config passed lint${NC}" fi done -echo "All lints run with no errors or warnings" +if [ $fails -gt 0 ]; then + echo -e "${RED}Linting failed for $fails of ${#configs[@]} configurations" + exit 1 +fi +echo -e "${GREEN}All ${#configs[@]} lints run with no errors or warnings" # --lint-only just runs lint rather than trying to compile and simulate # -I points to the include directory where files such as `include config.vh are found diff --git a/sim/regression-wally b/sim/regression-wally index ea453d2c9..26543d067 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -11,6 +11,9 @@ # ################################## import sys,os,shutil +import multiprocessing + + class bcolors: HEADER = '\033[95m' @@ -29,6 +32,8 @@ os.chdir(regressionDir) coverage = '-coverage' in sys.argv fp = '-fp' in sys.argv +nightly = '-nightly' in sys.argv +softfloat = '-softfloat' in sys.argv TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # name: the name of this test configuration (used in printing human-readable @@ -40,14 +45,20 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # be any pattern grep accepts, see `man 1 grep` for more info). # edit this list to add more test cases -configs = [ - TestCase( - name="lints", - variant="all", - cmd="./lint-wally | tee {}", - grepstr="All lints run with no errors or warnings" - ) -] +if (nightly): + nightMode = "-nightly"; + configs = [] +else: + nightMode = ""; + configs = [ + TestCase( + name="lints", + variant="all", + cmd="./lint-wally " + nightMode + " | tee {}", + grepstr="lints run with no errors or warnings" + ) + ] + def getBuildrootTC(boot): INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. @@ -62,7 +73,7 @@ def getBuildrootTC(boot): BRcmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c < XLEN +# ["nodcache_rv32gc", ["ahb32"]], +# ["nocache_rv32gc", ["ahb32"]], + ["noicache_rv64gc", ["ahb64"]], + ["nodcache_rv64gc", ["ahb64"]], + ["nocache_rv64gc", ["ahb64"]], + + ### add misaligned tests + + ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + + ### branch predictor simulation + + # ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + + # ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + + # # btb + # ["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + + # # ras + # ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + +# enable floating-point tests when lint is fixed + ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], + ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma"]], + ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]], + ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed + ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], + ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma"]], + ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "wally64q"]], + + + ] + for test in derivconfigtests: + config = test[0]; + tests = test[1]; + if(len(test) >= 4 and test[2] == "configOptions"): + configOptions = test[3] + cmdPrefix = "vsim > {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < $argc} break + set arg [expr "$$x"] + lappend lst $arg +} + if {$argc >= 3} { if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} { set coverage 1 + set CoverageVoptArg "+cover=sbecf" + set CoverageVsimArg "-coverage" + } elseif {$3 eq "configOptions"} { + set configOptions $lst + puts $configOptions } } @@ -58,91 +65,20 @@ if {$argc >= 3} { # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32imc rv32imc -if {$2 eq "buildroot"} { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation - if { $coverage } { - echo "wally-batch buildroot coverage" - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt +cover=sbecf - vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 -cover - } else { - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt - vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 - } - run -all - run -all - exec ./slack-notifier/slack-notifier.py -} elseif {$2 eq "buildroot-no-trace"} { - vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 +vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 - #-- Run the Simulation - echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" - echo "Don't forget to change DEBUG_LEVEL = 0." - echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" - run -all - run -all - exec ./slack-notifier/slack-notifier.py +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg} +vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg} -} elseif {$2 eq "ahb"} { - vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 - # start and run simulation - # remove +acc flag for faster sim during regressions if there is no need to access internal signals - vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt - vsim -lib wkdir/work_${1}_${2}_${3}_${4} testbenchopt -fatal 7 - # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time - #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf - #vsim -coverage -lib work_$2 workopt_$2 - - # power add generates the logging necessary for said generation. - # power add -r /dut/core/* - run -all - # power off -r /dut/core/* - -} elseif {$2 eq "configOptions"} { - # set arguments " " - # for {set i 5} {$i <= $argc} {incr i} { - # append arguments "\$$i " - # } - # puts $arguments - # set options eval $arguments - # **** fix this so we can pass any number of +defines. - # only allows 3 right now - - vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7 - # start and run simulation - # remove +acc flag for faster sim during regressions if there is no need to access internal signals - vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt - vsim -lib wkdir/work_${1}_${3}_${4} testbenchopt -fatal 7 -suppress 3829 - # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time - #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf - #vsim -coverage -lib work_$2 workopt_$2 - # power add generates the logging necessary for said generation. - # power add -r /dut/core/* - run -all - # power off -r /dut/core/* - -} else { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 - # start and run simulation - # remove +acc flag for faster sim during regressions if there is no need to access internal signals - if {$coverage} { -# vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbectf - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbecf - vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 -coverage - } else { - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt - vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 - } # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 - # power add generates the logging necessary for said generation. - # power add -r /dut/core/* - run -all - # power off -r /dut/core/* -} +# power add generates the logging necessary for said generation. +# power add -r /dut/core/* +run -all +# power off -r /dut/core/* + if {$coverage} { echo "Saving coverage to ${1}_${2}.ucdb" diff --git a/sim/wally-linux-imperas.do b/sim/wally-linux-imperas.do index e9bad30d5..1165676a0 100644 --- a/sim/wally-linux-imperas.do +++ b/sim/wally-linux-imperas.do @@ -32,25 +32,10 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { - vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation - vopt work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 - - #-- Run the Simulation - #run -all - run 7000 ms - add log -recursive /* - do linux-wave.do - run -all - - exec ./slack-notifier/slack-notifier.py - -} elseif {$2 eq "buildroot-no-trace"} { +if {$2 eq "buildroot"} { vlog -lint -work work_${1}_${2} \ +define+USE_IMPERAS_DV \ - +incdir+../config/$1 \ + +incdir+../config/deriv/$1 \ +incdir+../config/shared \ +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ @@ -64,7 +49,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \ ../src/cvw.sv \ - ../testbench/testbench-linux-imperas.sv \ + ../testbench/testbench.sv \ ../testbench/common/*.sv ../src/*/*.sv \ ../src/*/*/*.sv -suppress 2583 @@ -76,7 +61,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { # visualizer -fprofile+perf+dir=fprofile # eval vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \ - -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt + -G TEST=$2 -o testbenchopt eval vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 \ -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ $env(OTHERFLAGS) @@ -96,60 +81,4 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { exec ./slack-notifier/slack-notifier.py -} elseif {$2 eq "fpga"} { - echo "hello" - vlog -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286 - vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt - vsim workopt +nowarn3829 -fatal 7 - - do fpga-wave.do - add log -r /* - run 20 ms - -} else { - if {$2 eq "ahb"} { - vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 - } else { - # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. - vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 - } - vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt - - vsim workopt +nowarn3829 -fatal 7 - - view wave - #-- display input and output signals as hexidecimal values - #do ./wave-dos/peripheral-waves.do - add log -recursive /* - do wave.do - #do wave-bus.do - - # power add generates the logging necessary for saif generation. - #power add -r /dut/core/* - #-- Run the Simulation - - run -all - #power off -r /dut/core/* - #power report -all -bsaif power.saif - noview ../testbench/testbench.sv - view wave } - - - -#elseif {$2 eq "buildroot-no-trace""} { -# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation -# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt -# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 - - #-- Run the Simulation -# run 100 ns -# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa -# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000 -# add log -recursive /* -# do linux-wave.do -# run -all - -# exec ./slack-notifier/slack-notifier.py -#} diff --git a/sim/wally.do b/sim/wally.do index bc987e3d3..4c1a22074 100644 --- a/sim/wally.do +++ b/sim/wally.do @@ -77,12 +77,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { run 20 ms } else { - if {$2 eq "ahb"} { - vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 - } else { - # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. - vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 - } + vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt vsim workopt +nowarn3829 -fatal 7 diff --git a/src/cache/cache.sv b/src/cache/cache.sv index c8f707904..2edf867e2 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -81,7 +82,7 @@ module cache import cvw::*; #(parameter cvw_t P, logic ClearDirty, SetDirty, SetValid, ClearValid; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; logic [NUMWAYS-1:0] HitWay, ValidWay; - logic CacheHit; + logic Hit; logic [NUMWAYS-1:0] VictimWay, DirtyWay, HitDirtyWay; logic LineDirty, HitLineDirty; logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0]; @@ -97,7 +98,7 @@ module cache import cvw::*; #(parameter cvw_t P, logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache; logic SelFetchBuffer; logic CacheEn; - logic SelWay; + logic SelVictim; logic [LINELEN/8-1:0] LineByteMask; logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; genvar index; @@ -119,7 +120,7 @@ module cache import cvw::*; #(parameter cvw_t P, // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( - .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelWay, + .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay, .FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache); @@ -131,7 +132,7 @@ module cache import cvw::*; #(parameter cvw_t P, end else assign VictimWay = 1'b1; // one hot. - assign CacheHit = |HitWay; + assign Hit = |HitWay; assign LineDirty = |DirtyWay; assign HitLineDirty = |HitDirtyWay; @@ -175,18 +176,18 @@ module cache import cvw::*; #(parameter cvw_t P, logic [LINELEN/8-1:0] BlankByteMask; assign BlankByteMask[WORDLEN/8-1:0] = ByteMask; - assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = '0; + assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = 0; assign DemuxedByteMask = BlankByteMask << ((MUXINTERVAL/8) * WordOffsetAddr); - assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1. + assign FetchBufferByteSel = SetDirty ? ~DemuxedByteMask : '1; // If load miss set all muxes to 1. // Merge write data into fetched cache line for store miss for(index = 0; index < LINELEN/8; index++) begin mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]), .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index] & ~CMOpM[3]), .y(LineWriteData[8*index+7:8*index])); end - assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0; + assign LineByteMask = SetDirty ? DemuxedByteMask : '1; end else begin:WriteSelLogic @@ -199,7 +200,7 @@ module cache import cvw::*; #(parameter cvw_t P, // Flush logic ///////////////////////////////////////////////////////////////////////////////////////////// - if (!READ_ONLY_CACHE) begin:flushlogic + if (!READ_ONLY_CACHE) begin:flushlogic // D$ can be flushed // Flush address (line number) assign ResetOrFlushCntRst = reset | FlushCntRst; flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr); @@ -213,7 +214,8 @@ module cache import cvw::*; #(parameter cvw_t P, else assign NextFlushWay = FlushWay[NUMWAYS-1]; assign FlushWayFlag = FlushWay[NUMWAYS-1]; end // block: flushlogic - else begin:flushlogic + else begin:flushlogic // I$ is never flushed because it is never dirty + assign FlushWay = 0; assign FlushWayFlag = 0; assign FlushAdrFlag = 0; end @@ -224,8 +226,8 @@ module cache import cvw::*; #(parameter cvw_t P, cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, .FlushStage, .CacheRW, .Stall, - .CacheHit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted, - .CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelWay, + .Hit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted, + .CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelVictim, .ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback, .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index b593f2ae6..865ebc74d 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cacheLRU.sv // -// Written: Ross Thompson ross1728@gmail.com +// Written: Rose Thompson ross1728@gmail.com // Created: 20 July 2021 // Modified: 20 January 2023 // @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -35,8 +36,8 @@ module cacheLRU input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag - input logic [SETLEN-1:0] CacheSetData, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr - input logic [SETLEN-1:0] CacheSetTag, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr + input logic [SETLEN-1:0] CacheSetData, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr + input logic [SETLEN-1:0] CacheSetTag, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [SETLEN-1:0] PAdr, // Physical address input logic LRUWriteEn, // Update the LRU state input logic SetValid, // Set the dirty bit in the selected way and set @@ -50,23 +51,27 @@ module cacheLRU logic [NUMWAYS-2:0] LRUMemory [NUMLINES-1:0]; logic [NUMWAYS-2:0] CurrLRU; logic [NUMWAYS-2:0] NextLRU; - logic [NUMWAYS-1:0] Way; - logic [LOGNUMWAYS-1:0] WayEncoded; + logic [LOGNUMWAYS-1:0] HitWayEncoded, Way; logic [NUMWAYS-2:0] WayExpanded; logic AllValid; genvar row; /* verilator lint_off UNOPTFLAT */ - // Ross: For some reason verilator does not like this. I checked and it is not a circular path. + // Rose: For some reason verilator does not like this. I checked and it is not a circular path. logic [NUMWAYS-2:0] LRUUpdate; logic [LOGNUMWAYS-1:0] Intermediate [NUMWAYS-2:0]; /* verilator lint_on UNOPTFLAT */ + logic [NUMWAYS-1:0] FirstZero; + logic [LOGNUMWAYS-1:0] FirstZeroWay; + logic [LOGNUMWAYS-1:0] VictimWayEnc; + + binencoder #(NUMWAYS) hitwayencoder(HitWay, HitWayEncoded); + assign AllValid = &ValidWay; ///// Update replacement bits. - // coverage off // Excluded from coverage b/c it is untestable without varying NUMWAYS. function integer log2 (integer value); @@ -79,8 +84,7 @@ module cacheLRU // coverage on // On a miss we need to ignore HitWay and derive the new replacement bits with the VictimWay. - mux2 #(NUMWAYS) WayMux(HitWay, VictimWay, SetValid, Way); - binencoder #(NUMWAYS) encoder(Way, WayEncoded); + mux2 #(LOGNUMWAYS) WayMuxEnc(HitWayEncoded, VictimWayEnc, SetValid, Way); // bit duplication // expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ... @@ -88,7 +92,7 @@ module cacheLRU localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1); localparam StartIndex = NUMWAYS-2 - DuplicationFactor + 1; localparam EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2; - assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}}; + assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{Way[row]}}; end genvar node; @@ -101,14 +105,14 @@ module cacheLRU localparam r = LOGNUMWAYS - ctr_depth; // the child node will be updated if its parent was updated and - // the WayEncoded bit was the correct value. + // the Way bit was the correct value. // The if statement is only there for coverage since LRUUpdate[root] is always 1. if (node == NUMWAYS-2) begin - assign LRUUpdate[lchild] = ~WayEncoded[r]; - assign LRUUpdate[rchild] = WayEncoded[r]; + assign LRUUpdate[lchild] = ~Way[r]; + assign LRUUpdate[rchild] = Way[r]; end else begin - assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r]; - assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r]; + assign LRUUpdate[lchild] = LRUUpdate[node] & ~Way[r]; + assign LRUUpdate[rchild] = LRUUpdate[node] & Way[r]; end end @@ -128,30 +132,26 @@ module cacheLRU assign Intermediate[node] = CurrLRU[node] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0]; end - logic [NUMWAYS-1:0] FirstZero; - logic [LOGNUMWAYS-1:0] FirstZeroWay; - logic [LOGNUMWAYS-1:0] VictimWayEnc; priorityonehot #(NUMWAYS) FirstZeroEncoder(~ValidWay, FirstZero); binencoder #(NUMWAYS) FirstZeroWayEncoder(FirstZero, FirstZeroWay); mux2 #(LOGNUMWAYS) VictimMux(FirstZeroWay, Intermediate[NUMWAYS-2], AllValid, VictimWayEnc); - //decoder #(LOGNUMWAYS) decoder (Intermediate[NUMWAYS-2], VictimWay); decoder #(LOGNUMWAYS) decoder (VictimWayEnc, VictimWay); // LRU storage must be reset for modelsim to run. However the reset value does not actually matter in practice. // This is a two port memory. // Every cycle must read from CacheSetData and each load/store must write the new LRU. + + // note: Verilator lint doesn't like <= for array initialization (https://verilator.org/warn/BLKLOOPINIT?v=5.021) + // Move to = to keep Verilator happy and simulator running fast always_ff @(posedge clk) begin - if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; - if(CacheEn) begin - if(ClearValid & ~FlushStage) - LRUMemory[PAdr] <= '0; - else if(LRUWriteEn) - LRUMemory[PAdr] <= NextLRU; - if(LRUWriteEn & (PAdr == CacheSetTag)) - CurrLRU <= #1 NextLRU; - else - CurrLRU <= #1 LRUMemory[CacheSetTag]; + if (reset | (InvalidateCache & ~FlushStage)) + for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize + else if(CacheEn) begin + // Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value + if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = #1 NextLRU; + else CurrLRU = #1 LRUMemory[CacheSetTag]; + if(LRUWriteEn) LRUMemory[PAdr] = NextLRU; end end diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 07494c2a9..0059bb81d 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -49,7 +50,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, output logic CacheAccess, // Cache access // cache internals - input logic CacheHit, // Exactly 1 way hits + input logic Hit, // Exactly 1 way hits input logic LineDirty, // The selected line and way is dirty input logic HitLineDirty, // The cache hit way is dirty input logic FlushAdrFlag, // On last set of a cache flush @@ -62,7 +63,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, output logic ClearDirty, // Clear the dirty bit in the selected way and set output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback output logic LRUWriteEn, // Update the LRU state - output logic SelWay, // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway + output logic SelVictim, // Overides HitWay Tag matching. Selects selects the victim tag/data regardless of hit output logic FlushAdrCntEn, // Enable the counter for Flush Adr output logic FlushWayCntEn, // Enable the way counter during a flush output logic FlushCntRst, // Reset both flush counters @@ -78,12 +79,12 @@ module cachefsm import cvw::*; #(parameter cvw_t P, logic CMOZeroNoEviction; logic StallConditions; - typedef enum logic [3:0]{STATE_READY, // hit states + typedef enum logic [3:0]{STATE_ACCESS, // hit states // miss states STATE_FETCH, STATE_WRITEBACK, STATE_WRITE_LINE, - STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM + STATE_ADDRESS_SETUP, // required for back to back reads. structural hazard on writting SRAM // flush cache STATE_FLUSH, STATE_FLUSH_WRITEBACK @@ -91,61 +92,60 @@ module cachefsm import cvw::*; #(parameter cvw_t P, statetype CurrState, NextState; - assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss - assign AnyUpdateHit = (CacheRW[0]) & CacheHit; // exclusion-tag: icache storeAMO1 - assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); // exclusion-tag: icache AnyUpdateHit + assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~Hit & ~InvalidateCache; // exclusion-tag: cache AnyMiss + assign AnyUpdateHit = (CacheRW[0]) & Hit; // exclusion-tag: icache storeAMO1 + assign AnyHit = AnyUpdateHit | (CacheRW[1] & Hit); // exclusion-tag: icache AnyUpdateHit assign CMOZeroNoEviction = CMOpM[3] & ~LineDirty; // (hit or miss) with no writeback store zeros now - assign CMOWriteback = ((CMOpM[1] | CMOpM[2]) & CacheHit & HitLineDirty) | CMOpM[3] & LineDirty; + assign CMOWriteback = ((CMOpM[1] | CMOpM[2]) & Hit & HitLineDirty) | CMOpM[3] & LineDirty; assign FlushFlag = FlushAdrFlag & FlushWayFlag; // outputs for the performance counters. - assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) | (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW - assign CacheMiss = CacheAccess & ~CacheHit; + assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW + assign CacheMiss = CacheAccess & ~Hit; - // special case on reset. When the fsm first exists reset the + // special case on reset. When the fsm first exists reset twayhe // PCNextF will no longer be pointing to the correct address. // But PCF will be the reset vector. flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay)); always_ff @(posedge clk) - if (reset | FlushStage) CurrState <= #1 STATE_READY; + if (reset | FlushStage) CurrState <= #1 STATE_ACCESS; else CurrState <= #1 NextState; always_comb begin - NextState = STATE_READY; + NextState = STATE_ACCESS; case (CurrState) // exclusion-tag: icache state-case - STATE_READY: if(InvalidateCache) NextState = STATE_READY; // exclusion-tag: dcache InvalidateCheck - else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; + STATE_ACCESS: if(InvalidateCache) NextState = STATE_ACCESS; // exclusion-tag: dcache InvalidateCheck + else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; // exclusion-tag: icache FLUSHStatement else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement - else if(AnyMiss | CMOWriteback) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement - else NextState = STATE_READY; + else if((AnyMiss | CMOWriteback) & ~READ_ONLY_CACHE) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement + else NextState = STATE_ACCESS; STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; - else if(CacheBusAck) NextState = STATE_READY; else NextState = STATE_FETCH; - STATE_WRITE_LINE: NextState = STATE_READ_HOLD; - STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; - else NextState = STATE_READY; + STATE_WRITE_LINE: NextState = STATE_ADDRESS_SETUP; + STATE_ADDRESS_SETUP: if(Stall) NextState = STATE_ADDRESS_SETUP; + else NextState = STATE_ACCESS; // exclusion-tag-start: icache case STATE_WRITEBACK: if(CacheBusAck & ~(|CMOpM[3:1])) NextState = STATE_FETCH; - else if(CacheBusAck) NextState = STATE_READ_HOLD; // Read_hold lowers CacheStall + else if(CacheBusAck) NextState = STATE_ADDRESS_SETUP; // Read_hold lowers CacheStall else NextState = STATE_WRITEBACK; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; - else if (FlushFlag) NextState = STATE_READ_HOLD; + else if (FlushFlag) NextState = STATE_ADDRESS_SETUP; else NextState = STATE_FLUSH; STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; - else if(CacheBusAck) NextState = STATE_READ_HOLD; + else if(CacheBusAck) NextState = STATE_ADDRESS_SETUP; else NextState = STATE_FLUSH_WRITEBACK; // exclusion-tag-end: icache case - default: NextState = STATE_READY; + default: NextState = STATE_ACCESS; endcase end // com back to CPU - assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD)); - assign StallConditions = FlushCache | AnyMiss | CMOWriteback; - assign CacheStall = (CurrState == STATE_READY & StallConditions) | // exclusion-tag: icache StallStates + assign CacheCommitted = (CurrState != STATE_ACCESS) & ~(READ_ONLY_CACHE & (CurrState == STATE_ADDRESS_SETUP)); + assign StallConditions = FlushCache | AnyMiss | CMOWriteback; // exclusion-tag: icache FlushCache + assign CacheStall = (CurrState == STATE_ACCESS & StallConditions) | // exclusion-tag: icache StallStates (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. @@ -153,27 +153,26 @@ module cachefsm import cvw::*; #(parameter cvw_t P, (CurrState == STATE_FLUSH_WRITEBACK); // write enables internal to cache assign SetValid = CurrState == STATE_WRITE_LINE | - (CurrState == STATE_READY & CMOZeroNoEviction) | + (CurrState == STATE_ACCESS & CMOZeroNoEviction) | (CurrState == STATE_WRITEBACK & CacheBusAck & CMOpM[3]); - assign ClearValid = (CurrState == STATE_READY & CMOpM[0]) | + assign ClearValid = (CurrState == STATE_ACCESS & CMOpM[0]) | (CurrState == STATE_WRITEBACK & CMOpM[2] & CacheBusAck); - // coverage off -item e 1 -fecexprrow 8 - assign LRUWriteEn = (((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) | + assign LRUWriteEn = (((CurrState == STATE_ACCESS & (AnyHit | CMOZeroNoEviction)) | (CurrState == STATE_WRITE_LINE)) & ~FlushStage) | (CurrState == STATE_WRITEBACK & CMOpM[3] & CacheBusAck); // exclusion-tag-start: icache flushdirtycontrols - assign SetDirty = (CurrState == STATE_READY & (AnyUpdateHit | CMOZeroNoEviction)) | // exclusion-tag: icache SetDirty + assign SetDirty = (CurrState == STATE_ACCESS & (AnyUpdateHit | CMOZeroNoEviction)) | // exclusion-tag: icache SetDirty (CurrState == STATE_WRITE_LINE & (CacheRW[0])) | (CurrState == STATE_WRITEBACK & (CMOpM[3] & CacheBusAck)); assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. // Flush and eviction controls CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2]) & CacheBusAck; - assign SelWay = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOpM[1] | CMOpM[2])) | (CacheBusAck & CMOpM[3]))) | - (CurrState == STATE_READY & ((AnyMiss & LineDirty) | (CMOZeroNoEviction & ~CacheHit))) | + assign SelVictim = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOpM[1] | CMOpM[2])) | (CacheBusAck & CMOpM[3]))) | + (CurrState == STATE_ACCESS & ((AnyMiss & LineDirty) | (CMOZeroNoEviction & ~Hit))) | (CurrState == STATE_WRITE_LINE); assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2] | ~CacheBusAck)) | - (CurrState == STATE_READY & AnyMiss & LineDirty); + (CurrState == STATE_ACCESS & AnyMiss & LineDirty); // coverage off -item e 1 -fecexprrow 1 // (state is always FLUSH_WRITEBACK when FlushWayFlag & CacheBusAck) assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | @@ -184,31 +183,29 @@ module cachefsm import cvw::*; #(parameter cvw_t P, (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); // exclusion-tag-end: icache flushdirtycontrols // Bus interface controls - assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses + assign CacheBusRW[1] = (CurrState == STATE_ACCESS & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses (CurrState == STATE_FETCH & ~CacheBusAck) | (CurrState == STATE_WRITEBACK & CacheBusAck & ~(|CMOpM)); logic LoadMiss; - - //assign StoreMiss = (CacheRW[0]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss - assign LoadMiss = (CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss + assign LoadMiss = (CacheRW[1]) & ~Hit & ~InvalidateCache; // exclusion-tag: cache AnyMiss - assign CacheBusRW[0] = (CurrState == STATE_READY & LoadMiss & LineDirty) | // exclusion-tag: icache CacheBusW + assign CacheBusRW[0] = (CurrState == STATE_ACCESS & LoadMiss & LineDirty) | // exclusion-tag: icache CacheBusW (CurrState == STATE_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck) | (CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2]) & ~CacheBusAck); - assign SelAdrData = (CurrState == STATE_READY & (CacheRW[0] | AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed + assign SelAdrData = (CurrState == STATE_ACCESS & (CacheRW[0] | AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITE_LINE) | resetDelay; - assign SelAdrTag = (CurrState == STATE_READY & (AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed + assign SelAdrTag = (CurrState == STATE_ACCESS & (AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrTag // changes if store delay hazard removed (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | (CurrState == STATE_WRITE_LINE) | resetDelay; - assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD; - assign CacheEn = (~Stall | StallConditions) | (CurrState != STATE_READY) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn + assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_ADDRESS_SETUP; + assign CacheEn = (~Stall | StallConditions) | (CurrState != STATE_ACCESS) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn endmodule // cachefsm diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 3445067a0..e14a31c97 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -41,7 +42,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, input logic SetValid, // Set the valid bit in the selected way and set input logic ClearValid, // Clear the valid bit in the selected way and set input logic SetDirty, // Set the dirty bit in the selected way and set - input logic SelWay, // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway + input logic SelVictim, // Overides HitWay Tag matching. Selects selects the victim tag/data regardless of hit input logic ClearDirty, // Clear the dirty bit in the selected way and set input logic FlushCache, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr input logic VictimWay, // LRU selected this way as victim to evict @@ -52,7 +53,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid output logic HitWay, // This way hits output logic ValidWay, // This way is valid - output logic HitDirtyWay, // The hit way is dirty + output logic HitDirtyWay, // The hit way is dirty output logic DirtyWay , // The selected way is dirty output logic [TAGLEN-1:0] TagWay); // This way's tag if valid @@ -67,7 +68,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, logic [LINELEN-1:0] ReadDataLine; logic [TAGLEN-1:0] ReadTag; logic Dirty; - logic SelDirty; + logic SelecteDirty; logic SelectedWriteWordEn; logic [LINELEN/8-1:0] FinalByteMask; logic SetValidEN, ClearValidEN; @@ -76,36 +77,33 @@ module cacheway import cvw::*; #(parameter cvw_t P, logic SetDirtyWay; logic ClearDirtyWay; logic SelNonHit; - logic SelData; + logic SelectedWay; logic InvalidateCacheDelay; if (!READ_ONLY_CACHE) begin:flushlogic - logic FlushWayEn; - mux2 #(1) seltagmux(VictimWay, FlushWay, FlushCache, SelDirty); - + mux2 #(1) seltagmux(VictimWay, FlushWay, FlushCache, SelecteDirty); + mux3 #(1) selectedmux(HitWay, FlushWay, VictimWay, {SelVictim, FlushCache}, SelectedWay); // FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected. // coverage off -item e 1 -fecexprrow 3 // nonzero ways will never see FlushCache=0 while FlushWay=1 since FlushWay only advances on a subset of FlushCache assertion cases. - assign FlushWayEn = FlushWay & FlushCache; - assign SelNonHit = FlushWayEn | SelWay; end else begin:flushlogic // no flush operation for read-only caches. - assign SelDirty = VictimWay; - assign SelNonHit = SelWay; + assign SelecteDirty = VictimWay; + mux2 #(1) selectedwaymux(HitWay, SelecteDirty, SelVictim , SelectedWay); end - mux2 #(1) selectedwaymux(HitWay, SelDirty, SelNonHit , SelData); + ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux ///////////////////////////////////////////////////////////////////////////////////////////// - assign SetValidWay = SetValid & SelData; - assign ClearValidWay = ClearValid & SelData; - assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay - assign ClearDirtyWay = ClearDirty & SelData; + assign SetValidWay = SetValid & SelectedWay; + assign ClearValidWay = ClearValid & SelectedWay; // exclusion-tag: icache ClearValidWay + assign SetDirtyWay = SetDirty & SelectedWay; // exclusion-tag: icache SetDirtyWay + assign ClearDirtyWay = ClearDirty & SelectedWay; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN - assign ClearValidEN = ClearValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN + assign ClearValidEN = ClearValidWay & ~FlushStage; // exclusion-tag: cache ClearValidEN // If writing the whole line set all write enables to 1, else only set the correct word. assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR @@ -119,10 +117,10 @@ module cacheway import cvw::*; #(parameter cvw_t P, .din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); // AND portion of distributed tag multiplexer - assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux + assign TagWay = SelectedWay ? ReadTag : 0; // AND part of AOMux assign HitDirtyWay = Dirty & ValidWay; - assign DirtyWay = SelDirty & HitDirtyWay; - assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay; + assign DirtyWay = SelecteDirty & HitDirtyWay; // exclusion-tag: icache DirtyWay + assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay; // exclusion-tag: dcache HitWay flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay); @@ -151,19 +149,19 @@ module cacheway import cvw::*; #(parameter cvw_t P, end // AND portion of distributed read multiplexers - assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux. + assign ReadDataLineWay = SelectedWay ? ReadDataLine : 0; // AND part of AO mux. ///////////////////////////////////////////////////////////////////////////////////////////// // Valid Bits ///////////////////////////////////////////////////////////////////////////////////////////// always_ff @(posedge clk) begin // Valid bit array, - if (reset) ValidBits <= #1 '0; + if (reset) ValidBits <= #1 0; if(CacheEn) begin ValidWay <= #1 ValidBits[CacheSetTag]; - if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway + if(InvalidateCache) ValidBits <= #1 0; // exclusion-tag: dcache invalidateway else if (SetValidEN) ValidBits[CacheSetData] <= #1 SetValidWay; - else if (ClearValidEN) ValidBits[CacheSetData] <= #1 '0; + else if (ClearValidEN) ValidBits[CacheSetData] <= #1 0; // exclusion-tag: icache ClearValidBits end end @@ -178,7 +176,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, //if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; if(CacheEn) begin Dirty <= #1 DirtyBits[CacheSetTag]; - if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= #1 SetDirtyWay; + if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= #1 SetDirtyWay; // exclusion-tag: cache UpdateDirty end end end else assign Dirty = 1'b0; diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index db80cfc83..95920ec7e 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cvw.sv b/src/cvw.sv index a9ee9d093..75f83f68b 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -41,6 +41,8 @@ typedef struct packed { logic IEEE754; // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead) int MISA; // Machine Instruction Set Architecture int AHBW; // AHB bus width (usually = XLEN) + int RAM_LATENCY; // Latency to stress AHB + logic BURST_EN; // Support AHB Burst Mode // RISC-V Features logic ZICSR_SUPPORTED; @@ -160,6 +162,7 @@ typedef struct packed { int BPRED_SIZE; int BTB_SIZE; int RAS_SIZE; + logic INSTR_CLASS_PRED; // is class predictor enabled // FPU division architecture int RADIX; diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 5f2dff313..f033b40cc 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -27,10 +28,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ahbcacheinterface #( - parameter AHBW, - parameter LLEN, - parameter PA_BITS, +module ahbcacheinterface import cvw::*; #( + parameter cvw_t P, parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter AHBWLOGBWPL, // Log2 of ^ parameter LINELEN, // Number of bits in cacheline @@ -45,14 +44,14 @@ module ahbcacheinterface #( output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HBURST, // AHB burst length // bus interface buses - input logic [AHBW-1:0] HRDATA, // AHB read data - output logic [PA_BITS-1:0] HADDR, // AHB address - output logic [AHBW-1:0] HWDATA, // AHB write data - output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask + input logic [P.AHBW-1:0] HRDATA, // AHB read data + output logic [P.PA_BITS-1:0] HADDR, // AHB address + output logic [P.AHBW-1:0] HWDATA, // AHB write data + output logic [P.AHBW/8-1:0] HWSTRB, // AHB byte mask // cache interface - input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line - input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback + input logic [P.PA_BITS-1:0] CacheBusAdr, // Address of cache line + input logic [P.LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ input logic Cacheable, // Memory operation is cachable input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch @@ -62,8 +61,8 @@ module ahbcacheinterface #( output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface - input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation - input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store + input logic [P.PA_BITS-1:0] PAdr, // Physical address of uncached memory operation + input logic [P.LLEN-1:0] WriteDataM, // IEU write data for uncached store input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write input logic BusAtomic, // Uncache atomic memory operation input logic [2:0] Funct3, // Size of uncached memory operation @@ -77,12 +76,12 @@ module ahbcacheinterface #( localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index - logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation + logic [P.PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s - logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data - logic [PA_BITS-1:0] PAdrZero; + logic [P.AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [P.AHBW-1:0] PreHWDATA; // AHB Address phase write data + logic [P.PA_BITS-1:0] PAdrZero; genvar index; @@ -90,38 +89,38 @@ module ahbcacheinterface #( for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer logic [BEATSPERLINE-1:0] CaptureBeat; assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); - flopen #(AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), - .q(FetchBuffer[(index+1)*AHBW-1:index*AHBW])); + flopen #(P.AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), + .q(FetchBuffer[(index+1)*P.AHBW-1:index*P.AHBW])); end - assign PAdrZero = BusCMOZero ? {PAdr[PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; - mux2 #(PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); - assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR; + assign PAdrZero = BusCMOZero ? {PAdr[P.PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; + mux2 #(P.PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); + assign HADDR = ({{P.PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(P.AHBW/8)) + LocalHADDR; - mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); + mux2 #(3) sizemux(.d0(Funct3), .d1(P.AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. - logic [AHBW-1:0] CacheReadDataWordAHB; + logic [P.AHBW-1:0] CacheReadDataWordAHB; if(LLENPOVERAHBW > 1) begin - logic [AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; + logic [P.AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; genvar index; for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux - assign AHBWordSets[index] = CacheReadDataWordM[(index*AHBW)+AHBW-1: (index*AHBW)]; + assign AHBWordSets[index] = CacheReadDataWordM[(index*P.AHBW)+P.AHBW-1: (index*P.AHBW)]; end assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; - end else assign CacheReadDataWordAHB = CacheReadDataWordM[AHBW-1:0]; + end else assign CacheReadDataWordAHB = CacheReadDataWordM[P.AHBW-1:0]; - mux2 #(AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[AHBW-1:0]), + mux2 #(P.AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[P.AHBW-1:0]), .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); - flopen #(AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec + flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); + swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); - flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB); + flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB); - buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( + buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .BusCMOZero, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index df84175f0..2f4944303 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -61,8 +62,8 @@ module ahbinterface #( flop #(XLEN) wdreg(HCLK, WriteData, HWDATA); flop #(XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB); end else begin - assign HWDATA = '0; - assign HWSTRB = '0; + assign HWDATA = 0; + assign HWSTRB = 0; end busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 8d434c678..e1fded607 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -27,13 +28,12 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define BURST_EN 1 // Enables burst mode. Disable to show the lost performance. - // HCLK and clk must be the same clock! module buscachefsm #( parameter BeatCountThreshold, // Largest beat index parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE - parameter READ_ONLY_CACHE + parameter READ_ONLY_CACHE, // 1 for read-only instruction cache + parameter BURST_EN // burst mode supported )( input logic HCLK, input logic HRESETn, @@ -79,7 +79,7 @@ module buscachefsm #( logic CacheAccess; logic BusWrite; - assign BusWrite = CacheBusRW[0] | BusCMOZero; + assign BusWrite = (CacheBusRW[0] | BusCMOZero) & ~READ_ONLY_CACHE; always_ff @(posedge HCLK) if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; @@ -87,28 +87,28 @@ module buscachefsm #( always_comb begin case(CurrState) - ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; - else if (HREADY & BusWrite) NextState = CACHE_WRITEBACK; - else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; + ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; // exclusion-tag: buscachefsm HREADY0 + else if (HREADY & BusWrite & ~READ_ONLY_CACHE) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm HREADY1 + else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm HREADYread else NextState = ADR_PHASE; - DATA_PHASE: if(HREADY & BusAtomic) NextState = ATOMIC_READ_DATA_PHASE; - else if(HREADY & ~BusAtomic) NextState = MEM3; + DATA_PHASE: if(HREADY & BusAtomic & ~READ_ONLY_CACHE) NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm HREADY2 + else if(HREADY & ~BusAtomic) NextState = MEM3; // exclusion-tag: buscachefsm HREADY3 else NextState = DATA_PHASE; - ATOMIC_READ_DATA_PHASE: if(HREADY) NextState = ATOMIC_PHASE; - else NextState = ATOMIC_READ_DATA_PHASE; - ATOMIC_PHASE: if(HREADY) NextState = MEM3; - else NextState = ATOMIC_PHASE; + ATOMIC_READ_DATA_PHASE: if(HREADY) NextState = ATOMIC_PHASE; // exclusion-tag: buscachefsm AtomicReadData + else NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm AtomicElse + ATOMIC_PHASE: if(HREADY) NextState = MEM3; // exclusion-tag: buscachefsm AtomicPhase + else NextState = ATOMIC_PHASE; // exclusion-tag: buscachefsm AtomicWait MEM3: if(Stall) NextState = MEM3; else NextState = ADR_PHASE; - CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; - else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; + CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm FetchWriteback + else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm FetchWait else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; else NextState = CACHE_FETCH; - CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; - else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; - else if(HREADY & FinalBeatCount & BusCMOZero) NextState = MEM3; - else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; - else NextState = CACHE_WRITEBACK; + CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback + else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm HREADY4 + else if(HREADY & FinalBeatCount & BusCMOZero) NextState = MEM3; // exclusion-tag: buscachefsm HREADY5 + else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; // exclusion-tag: buscachefsm HREADY6 + else NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback2 default: NextState = ADR_PHASE; endcase end @@ -139,13 +139,13 @@ module buscachefsm #( // AHB bus interface assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) | - (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | + (CurrState == ATOMIC_READ_DATA_PHASE) | (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request - (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; + (CacheAccess & |BeatCount) ? (BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; - assign HWRITE = ((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | - (CurrState == CACHE_WRITEBACK & |BeatCount); - assign HBURST = `BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; + assign HWRITE = (((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | + (CurrState == CACHE_WRITEBACK & |BeatCount)) & ~READ_ONLY_CACHE; + assign HBURST = BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; always_comb begin case(BeatCountThreshold) diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 81d11715e..e49a6313a 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 60df9e44b..67e4795a6 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 4a1b00b57..356f955f3 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -31,31 +32,31 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ebu #(parameter XLEN, PA_BITS, AHBW)( +module ebu import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Signals from IFU input logic [1:0] IFUHTRANS, // IFU AHB transaction request input logic [2:0] IFUHSIZE, // IFU AHB transaction size input logic [2:0] IFUHBURST, // IFU AHB burst length - input logic [PA_BITS-1:0] IFUHADDR, // IFU AHB address + input logic [P.PA_BITS-1:0] IFUHADDR, // IFU AHB address output logic IFUHREADY, // AHB peripheral ready gated by possible non-grant // Signals from LSU input logic [1:0] LSUHTRANS, // LSU AHB transaction request input logic LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read input logic [2:0] LSUHSIZE, // LSU AHB size input logic [2:0] LSUHBURST, // LSU AHB burst length - input logic [PA_BITS-1:0] LSUHADDR, // LSU AHB address - input logic [XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN - input logic [XLEN/8-1:0] LSUHWSTRB, // AHB byte mask + input logic [P.PA_BITS-1:0] LSUHADDR, // LSU AHB address + input logic [P.XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN + input logic [P.XLEN/8-1:0] LSUHWSTRB, // AHB byte mask output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority // AHB-Lite external signals output logic HCLK, HRESETn, input logic HREADY, // AHB peripheral ready input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored. - output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration - output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration - output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration + output logic [P.PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration + output logic [P.AHBW-1:0] HWDATA, // AHB Write data after arbitration + output logic [P.XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration output logic HWRITE, // AHB transaction direction after arbitration output logic [2:0] HSIZE, // AHB transaction size after arbitration output logic [2:0] HBURST, // AHB burst length after arbitration @@ -71,13 +72,13 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( logic IFUDisable; logic IFUSelect; - logic [PA_BITS-1:0] IFUHADDROut; + logic [P.PA_BITS-1:0] IFUHADDROut; logic [1:0] IFUHTRANSOut; logic [2:0] IFUHBURSTOut; logic [2:0] IFUHSIZEOut; logic IFUHWRITEOut; - logic [PA_BITS-1:0] LSUHADDROut; + logic [P.PA_BITS-1:0] LSUHADDROut; logic [1:0] LSUHTRANSOut; logic [2:0] LSUHBURSTOut; logic [2:0] LSUHSIZEOut; @@ -96,25 +97,25 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( // input stages and muxing for IFU and LSU //////////////////////////////////////////////////////////////////////////////////////////////////// - controllerinput #(PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), + controllerinput #(P.PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), .Request(IFUReq), .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY)); // LSU always has priority so there should never be a need to save and restore the address phase inputs. - controllerinput #(PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), + controllerinput #(P.PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), .Request(LSUReq), .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY)); // output mux //*** switch to structural implementation - assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0; - assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: '0; - assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst. - assign HTRANS = LSUSelect ? LSUHTRANSOut : IFUSelect ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise - assign HWRITE = LSUSelect ? LSUHWRITEOut : IFUSelect ? 1'b0 : '0; + assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : 0; + assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: 0; + assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : 0; // If doing memory accesses, use LSUburst, else use Instruction burst. + assign HTRANS = LSUSelect ? LSUHTRANSOut : IFUSelect ? IFUHTRANSOut: 0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise + assign HWRITE = LSUSelect ? LSUHWRITEOut : 0; assign HPROT = 4'b0011; // not used; see Section 3.7 assign HMASTLOCK = 0; // no locking supported diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 302c4752f..55ba9a506 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv index bfc7a53dd..f35f71869 100644 --- a/src/fpu/fclassify.sv +++ b/src/fpu/fclassify.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index e330f1fda..0944090fc 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -67,12 +68,13 @@ module fcmp import cvw::*; #(parameter cvw_t P) ( // LT/LE - signaling - sets invalid if NaN input // EQ - quiet - sets invalid if signaling NaN input always_comb begin - case (OpCtrl[2:0]) + casez (OpCtrl[2:0]) 3'b110: CmpNV = EitherSNaN; //min 3'b101: CmpNV = EitherSNaN; //max 3'b010: CmpNV = EitherSNaN; //equal - 3'b001: CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq / flt perform CompareQuietLess / CompareSignalingLess differing on when to set invalid - 3'b011: CmpNV = Zfa ? EitherSNaN : EitherNaN; // fleq / fle differ on when to set invalid + 3'b0?1: if (P.ZFA_SUPPORTED) + CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq,fleq / flt,fle perform CompareQuietLess / CompareSignalingLess differing on when to set invalid + else CmpNV = EitherNaN; // flt, fle default: CmpNV = 1'bx; endcase end diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 6d5a91aa6..c61629c13 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -45,11 +46,11 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( // input mux selections output logic XEnD, YEnD, ZEnD, // enable inputs output logic XEnE, YEnE, ZEnE, // enable inputs - // opperation mux selections - output logic FCvtIntE, FCvtIntW, // convert to integer opperation + // operation mux selections + output logic FCvtIntE, FCvtIntW, // convert to integer operation output logic [2:0] FrmM, // FP rounding mode output logic [P.FMTBITS-1:0] FmtE, FmtM, // FP format - output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component + output logic [2:0] OpCtrlE, OpCtrlM, // Select which operation to do in each component output logic FpLoadStoreM, // FP load or store instruction output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage @@ -71,7 +72,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( logic FRegWriteD; // FP register write enable logic FDivStartD; // start division/sqrt logic FWriteIntD; // integer register write enable - logic [2:0] OpCtrlD; // Select which opperation to do in each component + logic [2:0] OpCtrlD; // Select which operation to do in each component logic [1:0] PostProcSelD; // select result in the post processing unit logic [1:0] FResSelD; // Select one of the results that finish in the memory stage logic [2:0] FrmD, FrmE; // FP rounding mode @@ -79,16 +80,15 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( logic [1:0] Fmt, Fmt2; // format - before possible reduction logic SupportedFmt; // is the format supported logic SupportedFmt2; // is the source format supported for fp -> fp - logic FCvtIntD, FCvtIntM; // convert to integer opperation + logic FCvtIntD, FCvtIntM; // convert to integer operation logic ZfaD; // Zfa variants of instructions // FPU Instruction Decoder assign Fmt = Funct7D[1:0]; assign Fmt2 = Rs2D[1:0]; // source format for fcvt fp->fp - assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & P.D_SUPPORTED) | - (Fmt == 2'b10 & P.ZFH_SUPPORTED & {OpD[6:4], OpD[1:0]} != 5'b10011) | // fma not supported for Zfh - (Fmt == 2'b11 & P.Q_SUPPORTED)); + assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & P.D_SUPPORTED) | + (Fmt == 2'b10 & P.ZFH_SUPPORTED) | (Fmt == 2'b11 & P.Q_SUPPORTED)); assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) | (Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED)); @@ -237,11 +237,10 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.q q->l 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.q q->lu endcase - // coverage on + // coverage off + // Not covered in testing because rv64gc is not RV64Q or RV32D 7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000) ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.d.x (Zfa) *** untested, controls could be wrong - // Not covered in testing because rv64gc does not support quad precision - // coverage off 7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000) ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.q.x (Zfa) // coverage on diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index ad767d2ef..ad3a2f602 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -31,7 +31,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( input logic [P.NE-1:0] Xe, // input's exponent input logic [P.NF:0] Xm, // input's fraction input logic [P.XLEN-1:0] Int, // integer input - from IEU - input logic [2:0] OpCtrl, // choose which opperation (look below for values) + input logic [2:0] OpCtrl, // choose which operation (look below for values) input logic ToInt, // is fp->int (since it's writting to the integer register) input logic XZero, // is the input zero input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) @@ -58,9 +58,9 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] TrimInt; // integer trimmed to the correct size logic [P.NE-2:0] NewBias; // the bias of the final result logic [P.NE-1:0] OldExp; // the old exponent - logic Signed; // is the opperation with a signed integer? + logic Signed; // is the operation with a signed integer? logic Int64; // is the integer 64 bits? - logic IntToFp; // is the opperation an int->fp conversion? + logic IntToFp; // is the operation an int->fp conversion? logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder) logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC @@ -69,7 +69,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( assign Int64 = OpCtrl[1]; assign IntToFp = OpCtrl[2]; - // choose the output format depending on the opperation + // choose the output format depending on the operation // - fp -> fp: OpCtrl contains the precision of the output // - int -> fp: Fmt contains the precision of the output if (P.FPSIZES == 2) diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index a4e20f229..85a1a5494 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index 1e6eda56c..72fe04249 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -70,8 +71,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) ( // The datapath produces rk bits per cycle, so Cycles = ceil (ResultBitsE / rk) always_comb begin - if (SqrtE) FPResultBitsE = Nf + 2 + 0; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1 - else FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits + FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1 if (P.IDIV_ON_FPU) ResultBitsE = IntDivE ? IntResultBitsE : FPResultBitsE; else ResultBitsE = FPResultBitsE; diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index bbb2d9360..d24b490ab 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index cf398f570..732bd6f51 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -36,7 +37,7 @@ module fdivsqrtfgen2 import cvw::*; #(parameter cvw_t P) ( // Generate for both positive and negative quotient digits assign FP = ~(U << 1) & C; assign FN = (UM << 1) | (C & ~(C << 2)); - assign FZ = '0; + assign FZ = 0; always_comb // Choose which adder input will be used if (up) F = FP; diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index e2cec1ab4..f1c2e3281 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -36,7 +37,7 @@ module fdivsqrtfgen4 import cvw::*; #(parameter cvw_t P) ( // Generate for both positive and negative digits assign F2 = (~U << 2) & (C << 2); // assign F1 = ~(U << 1) & C; - assign F0 = '0; + assign F0 = 0; assign FN1 = (UM << 1) | (C & ~(C << 3)); assign FN2 = (UM << 2) | ((C << 2) & ~(C << 4)); diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 862d53b25..f7d21e5d8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -70,8 +71,8 @@ module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) ( end else if (state == BUSY) begin if (step == 1 | WZeroE) state <= #1 DONE; // finished steps or terminate early on zero residual step <= step - 1; - end else if (state == DONE) begin - if (StallM) state <= #1 DONE; + end else if (state == DONE) begin // Can't still be stalled in configs tested, but keep this check for paranoia + if (StallM) state <= #1 DONE; // exclusion-tag: fdivsqrtfsm stallm else state <= #1 IDLE; end end diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 863d94837..c942db450 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -43,7 +44,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( logic [P.DIVb+3:0] WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb logic [P.DIVb+3:0] WS[P.DIVCOPIES:0]; // Q4.DIVb logic [P.DIVb+3:0] WC[P.DIVCOPIES:0]; // Q4.DIVb - logic [P.DIVb:0] U[P.DIVCOPIES:0]; // U1.DIVb + logic [P.DIVb:0] U[P.DIVCOPIES:0]; // U1.DIVb // *** probably Q not U. See Table 16.26 notes logic [P.DIVb:0] UM[P.DIVCOPIES:0]; // U1.DIVb logic [P.DIVb:0] UNext[P.DIVCOPIES-1:0]; // U1.DIVb logic [P.DIVb:0] UMNext[P.DIVCOPIES-1:0]; // U1.DIVb @@ -70,24 +71,18 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( flopen #(P.DIVb+4) wcreg(clk, FDivBusyE, WCN, WC[0]); // UOTFC Result U and UM registers/initialization mux - // Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 otherwise - assign initU = {SqrtE, {(P.DIVb){1'b0}}}; - assign initUM = {~SqrtE, {(P.DIVb){1'b0}}}; + // Initialize U to 0 = 0.0000... and UM to -1 = 1.00000... (in Q1.Divb) + assign initU ={(P.DIVb+1){1'b0}}; + assign initUM = {{1'b1}, {(P.DIVb){1'b0}}}; mux2 #(P.DIVb+1) Umux(UNext[P.DIVCOPIES-1], initU, IFDivStartE, UMux); mux2 #(P.DIVb+1) UMmux(UMNext[P.DIVCOPIES-1], initUM, IFDivStartE, UMMux); flopen #(P.DIVb+1) UReg(clk, FDivBusyE, UMux, U[0]); flopen #(P.DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]); - // C register/initialization mux - // Initialize C to -1 for sqrt and -R for division - logic [1:0] initCUpper; - if(P.RADIX == 4) begin - mux2 #(2) cuppermux4(2'b00, 2'b11, SqrtE, initCUpper); - end else begin - mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, initCUpper); - end - - assign initC = {initCUpper, {P.DIVb{1'b0}}}; + // C register/initialization mux: C = -R: + // C = -4 = 00.000000... (in Q2.DIVb) for radix 4, C = -2 = 10.000000... for radix2 + if(P.RADIX == 4) assign initC = 0; + else assign initC = {2'b10, {{P.DIVb{1'b0}}}}; mux2 #(P.DIVb+2) cmux(C[P.DIVCOPIES], initC, IFDivStartE, NextC); flopen #(P.DIVb+2) creg(clk, FDivBusyE, NextC, C[0]); @@ -107,9 +102,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]), .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i])); end else begin: stage - logic j1; - assign j1 = (i == 0 & ~C[0][P.DIVb-1]); - fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1, + fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]), .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i])); end diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 5a40a3bdc..78a50d0c3 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -120,7 +121,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( else IntDivResultM = {(P.XLEN){1'b1}}; end else if (ALTBM) begin // Numerator is small if (RemOpM) IntDivResultM = AM; - else IntDivResultM = '0; + else IntDivResultM = 0; end else IntDivResultM = PreIntResultM[P.XLEN-1:0]; // sign extend result for W64 diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 939b9c133..0f0273c25 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -173,9 +174,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( logic [P.DIVb:0] PreSqrtX; assign EvenExp = Xe[0] ^ ell[0]; // effective unbiased exponent after normalization is even - mux2 #(P.DIVb+1) sqrtxmux(Xnorm, {1'b0, Xnorm[P.DIVb:1]}, EvenExp, PreSqrtX); // X if exponent odd, X/2 if exponent even - if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX}; // PreSqrtX - 2 = 2(PreSqrtX/2 - 1) - else assign SqrtX = {2'b11, PreSqrtX, 1'b0}; // 2PreSqrtX - 4 = 4(PreSqrtX/2 - 1) + mux2 #(P.DIVb+4) sqrtxmux({4'b0,Xnorm[P.DIVb:1]}, {5'b00, Xnorm[P.DIVb:2]}, EvenExp, SqrtX); // X/2 if exponent odd, X/4 if exponent even /* // Attempt to optimize radix 4 to use a left shift by 1 or zero initially, followed by no more left shift diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 40a2a5a01..a0a552ac8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -57,7 +58,7 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) ( // Divisor multiple always_comb if (up) Dsel = DBar; - else if (uz) Dsel = '0; + else if (uz) Dsel = 0; else Dsel = D; // un // Residual Update diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index a24c1155f..d879e0f90 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -31,7 +32,7 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) ( input logic [P.DIVb:0] U,UM, // U1.DIVb input logic [P.DIVb+3:0] WS, WC, // Q4.DIVb input logic [P.DIVb+1:0] C, // Q2.DIVb - input logic SqrtE, j1, + input logic SqrtE, output logic [P.DIVb+1:0] CNext, // Q2.DIVb output logic un, output logic [P.DIVb:0] UNext, UMNext, // U1.DIVb @@ -47,13 +48,16 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) ( logic [7:0] WCmsbs, WSmsbs; // U4.4 logic CarryIn; logic [P.DIVb+3:0] WSA, WCA; // Q4.DIVb + logic j0, j1; // step j = 0 or step j = 1 // Digit Selection logic + assign j0 = ~C[P.DIVb+1]; // first step of R digit selection: C = 00...0 + assign j1 = C[P.DIVb] & ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; *** could simplify to ~C[P.DIVb-1] because j=0 case takes priority assign Smsbs = U[P.DIVb:P.DIVb-4]; // U1.4 most significant bits of square root assign Dmsbs = D[P.DIVb-1:P.DIVb-3]; // U0.3 most significant fractional bits of divisor after leading 1 assign WCmsbs = WC[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual assign WSmsbs = WS[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual - fdivsqrtuslc4cmp uslc4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit); + fdivsqrtuslc4cmp uslc4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j0, .j1, .udigit); assign un = 1'b0; // unused for radix 4 // F generation logic @@ -64,7 +68,7 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) ( case (udigit) 4'b1000: Dsel = DBar2; 4'b0100: Dsel = DBar; - 4'b0000: Dsel = '0; + 4'b0000: Dsel = 0; 4'b0010: Dsel = D; 4'b0001: Dsel = D2; default: Dsel = 'x; diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index c895fa2ce..032bb700e 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index b12b9174b..19e322013 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv index e4fcfeadf..2d4cd5e48 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv index b44b34a35..610b79395 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -30,7 +31,7 @@ module fdivsqrtuslc4 ( input logic [2:0] Dmsbs, // U0.3 fractional bits after implicit leading 1 input logic [4:0] Smsbs, // U1.4 leading bits of square root approximation input logic [7:0] WSmsbs, WCmsbs, // Q4.4 redundant residual most significant bits - input logic Sqrt, j1, + input logic Sqrt, j0, j1, output logic [3:0] udigit // {2, 1, -1, -2} digit is 0 if none are hot ); logic [7:0] PreWmsbs; // Q4.4 nonredundant residual msbs @@ -101,11 +102,12 @@ module fdivsqrtuslc4 ( // Select A always_comb if (Sqrt) begin - if (j1) A = 3'b101; // on first sqrt iteration A = .101 - else if (Smsbs == 5'b10000) A = 3'b111; // if S = 1.0, use A = .111 - else A = Smsbs[2:0]; // otherwise use A = 2S (in U0.3 format) - end else A = Dmsbs; // division Unless A = D (IN U0.3 format, dropping leading 1) + if (j1) A = 3'b101; // on first sqrt iteration A = .101 + else if (Smsbs[4] == 1) A = 3'b111; // if S = 1.0000, use A = .111 + else A = Smsbs[2:0]; // otherwise use A = 2S (in U0.3 format) + end else A = Dmsbs; // division A = D (IN U0.3 format, dropping leading 1) // Select quotient digit from lookup table based on A and W - assign udigit = USel4[{A,Wmsbs}]; + // On step j = 0 for square root, always select u_0 = 1 + assign udigit = (Sqrt & j0) ? 4'b0100 : USel4[{A,Wmsbs}]; endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv index ccb5e618a..fef26668c 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -30,7 +31,8 @@ module fdivsqrtuslc4cmp ( input logic [2:0] Dmsbs, // U0.3 fractional bits after implicit leading 1 input logic [4:0] Smsbs, // U1.4 leading bits of square root approximation input logic [7:0] WSmsbs, WCmsbs, // Q4.4 residual most significant bits - input logic SqrtE, j1, + input logic SqrtE, + input logic j0, j1, // are we on first (j0) or second step (j1) of digit selection output logic [3:0] udigit // {2, 1, -1, -2} digit is 0 if none are hot ); logic [6:0] Wmsbs; @@ -45,7 +47,9 @@ module fdivsqrtuslc4cmp ( // Wmsbs = | | logic [6:0] mk2, mk1, mk0, mkm1; + logic [6:0] mkj2, mkj1, mkj0, mkjm1; logic [6:0] mks2[7:0], mks1[7:0]; + logic sqrtspecial; // Prepopulate table of mks0 assign mks2[0] = 12; @@ -64,20 +68,25 @@ module fdivsqrtuslc4cmp ( assign mks1[5] = 8; // is the logic any cheaper if this is a 6? assign mks1[6] = 8; assign mks1[7] = 8; + + // handles special case when j = 0 or j = 1 for sqrt + assign mkj2 = 20; // when j = 1 use mk2[101] when j = 0 use anything bigger than 7. + assign mkj1 = j0 ? 0 : 8; // when j = 1 use mk1[101] = 8 and when j = 0 use 0 so we choose u_0 = 1 + assign sqrtspecial = SqrtE & (j1 | j0); - // Choose A for current operation + // Choose A for current operation always_comb if (SqrtE) begin - if (j1) A = 3'b101; - else if (Smsbs == 5'b10000) A = 3'b111; + if (Smsbs[4]) A = 3'b111; // for S = 1.0000 *** can we optimize away this case? else A = Smsbs[2:0]; end else A = Dmsbs; - + // Choose selection constants based on a - assign mk2 = mks2[A]; - assign mk1 = mks1[A]; - assign mk0 = -mks1[A]; - assign mkm1 = (A == 3'b000) ? -13 : -mks2[A]; // asymmetry in table + + assign mk2 = sqrtspecial ? mkj2 : mks2[A]; + assign mk1 = sqrtspecial ? mkj1 : mks1[A]; + assign mk0 = -mk1; + assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide from critical path // Compare residual W to selection constants to choose digit always_comb diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv index 14f8c945f..e68934294 100644 --- a/src/fpu/fhazard.sv +++ b/src/fpu/fhazard.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv index e61415388..c352d7a5c 100644 --- a/src/fpu/fli.sv +++ b/src/fpu/fli.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 16 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -79,7 +80,7 @@ module fli import cvw::*; #(parameter cvw_t P) ( endcase end assign HImmBox = {{(P.FLEN-16){1'b1}}, HImm}; // NaN-box HImm - end else assign HImmBox = '0; + end else assign HImmBox = 0; //////////////////////////// // single @@ -167,14 +168,14 @@ module fli import cvw::*; #(parameter cvw_t P) ( endcase end assign DImmBox = {{(P.FLEN-64){1'b1}}, DImm}; // NaN-box DImm - end else assign DImmBox = '0; + end else assign DImmBox = 0; //////////////////////////// // double //////////////////////////// if (P.Q_SUPPORTED) begin - logic [63:0] QImm; + logic [127:0] QImm; always_comb begin case(Rs1) 0: QImm = 128'hBFFF0000000000000000000000000000; @@ -212,7 +213,7 @@ module fli import cvw::*; #(parameter cvw_t P) ( endcase end assign QImmBox = QImm; // NaN-box QImm trivial because Q is longest format - end else assign QImmBox = '0; + end else assign QImmBox = 0; mux4 #(P.FLEN) flimux(SImmBox, DImmBox, HImmBox, QImmBox, Fmt, Imm); // select immediate based on format diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv index a6e87a240..bdf2898f7 100644 --- a/src/fpu/fma/fma.sv +++ b/src/fpu/fma/fma.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -35,7 +36,7 @@ module fma import cvw::*; #(parameter cvw_t P) ( output logic ASticky, // sticky bit that is calculated during alignment output logic [3*P.NF+3:0] Sm, // the positive sum's significand output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A) - output logic As, // the aligned addend's sign (modified Z sign for other opperations) + output logic As, // the aligned addend's sign (modified Z sign for other operations) output logic Ps, // the product's sign output logic Ss, // the sum's sign output logic [P.NE+1:0] Se, // the sum's exponent @@ -73,7 +74,7 @@ module fma import cvw::*; #(parameter cvw_t P) ( // multiplication of the mantissa's fmamult #(P) mult(.Xm, .Ym, .Pm); - // calculate the signs and take the opperation into account + // calculate the signs and take the operation into account fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As, .InvA); /////////////////////////////////////////////////////////////////////////////// diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 98ff21491..00951ee10 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -29,7 +30,7 @@ module fmaadd import cvw::*; #(parameter cvw_t P) ( input logic [3*P.NF+3:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1) input logic [P.NE-1:0] Ze, // exponent of Z - input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations) + input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other operations) input logic [P.NE+1:0] Pe, // product's exponet input logic [2*P.NF+1:0] Pm, // the product's mantissa input logic InvA, // invert the aligned addend @@ -50,9 +51,9 @@ module fmaadd import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////////////////////////////////////////// // Choose an inverted or non-inverted addend. Put carry into adder/LZA for addition - assign AmInv = {3*P.NF+4{InvA}}^Am; + assign AmInv = InvA ? ~Am : Am; // Kill the product if the product is too small to effect the addition (determined in fma1.sv) - assign PmKilled = {2*P.NF+2{~KillProd}}&Pm; + assign PmKilled = KillProd ? 0 : Pm; // Do the addition // - calculate a positive and negative sum in parallel // if there was a small negative number killed in the alignment stage one needs to be subtracted from the sum diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index efc4a4c5f..9001742e4 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv index bb7bf2437..50b85ded0 100644 --- a/src/fpu/fma/fmaexpadd.sv +++ b/src/fpu/fma/fmaexpadd.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -36,6 +37,6 @@ module fmaexpadd import cvw::*; #(parameter cvw_t P) ( // kill the exponent if the product is zero - either X or Y is 0 assign PZero = XZero | YZero; - assign Pe = PZero ? '0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)}); + assign Pe = PZero ? 0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)}); endmodule diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv index 66659665a..822f857c2 100644 --- a/src/fpu/fma/fmalza.sv +++ b/src/fpu/fma/fmalza.sv @@ -10,6 +10,7 @@ // See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv index 91f255b87..8ce492f03 100644 --- a/src/fpu/fma/fmamult.sv +++ b/src/fpu/fma/fmamult.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv index aca6c8f8c..891c28746 100644 --- a/src/fpu/fma/fmasign.sv +++ b/src/fpu/fma/fmasign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -27,10 +28,10 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fmasign( - input logic [2:0] OpCtrl, // opperation contol + input logic [2:0] OpCtrl, // operation contol input logic Xs, Ys, Zs, // sign of the inputs - output logic Ps, // the product's sign - takes opperation into account - output logic As, // aligned addend sign used in fma - takes opperation into account + output logic Ps, // the product's sign - takes operation into account + output logic As, // aligned addend sign used in fma - takes operation into account output logic InvA // Effective subtraction: invert addend ); diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index c304219aa..c97a12d32 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -74,7 +75,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( logic FDivStartE, IDivStartE; // Start division or squareroot logic FWriteIntM; // Write to integer register logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals - logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component + logic [2:0] OpCtrlE, OpCtrlM; // Select which operation to do in each component logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input @@ -211,7 +212,8 @@ module fpu import cvw::*; #(parameter cvw_t P) ( {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)}, {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}, {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes - assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10); + assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(PostProcSelE==2'b10); + // ***simplified from appearently redundant assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10); mux2 #(P.FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z @@ -268,15 +270,22 @@ module fpu import cvw::*; #(parameter cvw_t P) ( // floating-point load immediate: fli if (P.ZFA_SUPPORTED) begin logic [4:0] Rs1E; + logic [1:0] Fmt2E; // Two-bit format field from instruction flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E); - fli #(P) fli(.Rs1(Rs1E), .Fmt(FmtE), .Imm(FliResE)); - end else assign FliResE = '0; + flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E); + fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE)); + end else assign FliResE = 0; // fmv.*.x: NaN Box SrcA to extend integer to requested FP size - if(P.FPSIZES == 1) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}; + if(P.FPSIZES == 1) + if (P.FLEN >= P.XLEN) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}; + else assign PreIntSrcE = ForwardedSrcAE[P.FLEN-1:0]; else if(P.FPSIZES == 2) - mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE); + if (P.FLEN >= P.XLEN) + mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE); + else + mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, ForwardedSrcAE[P.FLEN-1:0], FmtE, PreIntSrcE); else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN mux3 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]}, @@ -285,7 +294,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( FmtE, PreIntSrcE); // NaN boxing zeroes end // fmvp.*.x: Select pair of registers - if (P.ZFA_SUPPORTED & (P.XLEN==32 & P.D_SUPPORTED) | (P.XLEN==64 & P.Q_SUPPORTED)) + if (P.ZFA_SUPPORTED & (P.FLEN == 2*P.XLEN)) assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x else assign IntSrcE = PreIntSrcE; @@ -309,11 +318,11 @@ module fpu import cvw::*; #(parameter cvw_t P) ( end // sign extend to XLEN if necessary - if (P.FLEN>P.XLEN) - if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.* - else assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; + if (P.FLEN >= 2*P.XLEN) + if (P.ZFA_SUPPORTED & P.FLEN == 2*P.XLEN) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.* + else assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; else - assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE}; + assign IntSrcXE = {{(P.XLEN-P.FLEN){mvsgn}}, SgnExtXE}; mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE); // E/M pipe registers @@ -352,7 +361,8 @@ module fpu import cvw::*; #(parameter cvw_t P) ( .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM)); // FPU flag selection - to privileged - mux2 #(5) FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM); + //mux2 #(5) FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM); + mux2 #(5) FPUFlgMux({PreNVM, 4'b0}, PostProcFlgM, (FResSelM == 2'b01), SetFflagsM); mux2 #(P.FLEN) FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM); // M/W pipe registers diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index 6ab14df20..2de41088b 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index cee13f4f9..4fe03522b 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index ff3d29b90..8b7587e49 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -98,6 +99,6 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) ( // determine if the result underflows ??? -> fp // - if the first 1 is shifted out of the result then the result underflows // - can't underflow an integer to fp conversions - assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp; + assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp; endmodule diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index 9e5de7173..b0335c780 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -64,7 +65,7 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) ( // if the shift amount is negative then don't shift (keep sticky bit) // need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES) - assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0; + assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : 0; assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift; // pre-shift the divider result for normalization diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv index 50d9bf229..cb16cc2a1 100644 --- a/src/fpu/postproc/flags.sv +++ b/src/fpu/postproc/flags.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -41,7 +42,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( input logic Round, Guard, Sticky, // bits used to determine rounding input logic UfPlus1, // do you add one for rounding for the unbounded exponent result // convert - input logic CvtOp, // conversion opperation? + input logic CvtOp, // conversion operation? input logic ToInt, // convert to integer input logic IntToFp, // convert integer to floating point input logic Int64, // convert to 64 bit integer @@ -49,10 +50,10 @@ module flags import cvw::*; #(parameter cvw_t P) ( input logic [P.NE:0] CvtCe, // the calculated expoent - Cvt input logic [1:0] CvtNegResMsbs, // the negative integer result's most significant bits // divsqrt - input logic DivOp, // conversion opperation? + input logic DivOp, // conversion operation? input logic Sqrt, // Sqrt? // fma - input logic FmaOp, // Fma opperation? + input logic FmaOp, // Fma operation? input logic FmaAs, FmaPs, // the product and modified Z signs // flags output logic DivByZero, // divide by zero flag @@ -148,8 +149,7 @@ module flags import cvw::*; #(parameter cvw_t P) ( // Set Inexact flag if the result is diffrent from what would be outputed given infinite precision // - Don't set the underflow flag if an underflowed res isn't outputed assign FpInexact = (Sticky|Guard|Overflow|Round)&~(InfIn|NaNIn|DivByZero|Invalid); - //assign FpInexact = (Sticky|Guard|Overflow|Round)&~(InfIn|NaNIn|DivByZero|Invalid|XZero); - + // if the res is too small to be represented and not 0 // | and if the res is not invalid (outside the integer bounds) // | | diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index 0a8ac3035..81e7fb6d9 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -59,7 +60,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( end else if (P.FPSIZES == 3) begin always_comb begin case (Fmt) - P.FMT: BiasCorr = '0; + P.FMT: BiasCorr = 0; P.FMT1: BiasCorr = (P.NE+2)'(P.BIAS1-P.BIAS); P.FMT2: BiasCorr = (P.NE+2)'(P.BIAS2-P.BIAS); default: BiasCorr = 'x; @@ -69,7 +70,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( end else if (P.FPSIZES == 4) begin always_comb begin case (Fmt) - 2'h3: BiasCorr = '0; + 2'h3: BiasCorr = 0; 2'h1: BiasCorr = (P.NE+2)'(P.D_BIAS-P.Q_BIAS); 2'h0: BiasCorr = (P.NE+2)'(P.S_BIAS-P.Q_BIAS); 2'h2: BiasCorr = (P.NE+2)'(P.H_BIAS-P.Q_BIAS); @@ -101,9 +102,9 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) ( assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-2+P.BIAS-P.BIAS2)) | ~|PreNormSumExp; always_comb begin case (Fmt) - P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; - P.FMT1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL & ~FmaSZero; - P.FMT2: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL & ~FmaSZero; + P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL; // & ~FmaSZero; // checking sum is not zero is harmless but turns out to be unnecessary + P.FMT1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL; // & ~FmaSZero; + P.FMT2: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL; // & ~FmaSZero; default: FmaPreResultSubnorm = 1'bx; endcase end diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv index d0aaf760b..5ca848b0b 100644 --- a/src/fpu/postproc/negateintres.sv +++ b/src/fpu/postproc/negateintres.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv index f24a75fe1..f235d4d5b 100644 --- a/src/fpu/postproc/normshift.sv +++ b/src/fpu/postproc/normshift.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 1d51fdf85..17dda38a0 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -32,7 +33,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( input logic [P.NF:0] Xm, Ym, Zm, // input mantissas input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude input logic [P.FMTBITS-1:0] Fmt, // precision 1 = double 0 = single - input logic [2:0] OpCtrl, // choose which opperation (look below for values) + input logic [2:0] OpCtrl, // choose which operation (look below for values) input logic XZero, YZero, // inputs are zero input logic XInf, YInf, ZInf, // inputs are infinity input logic XNaN, YNaN, ZNaN, // inputs are NaN @@ -103,14 +104,14 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( logic CvtResUf; // did the convert result underflow logic IntInvalid; // invalid integer flag // readability signals - logic Mult; // multiply opperation - logic Sqrt; // is the divsqrt opperation sqrt + logic Mult; // multiply operation + logic Sqrt; // is the divsqrt operation sqrt logic Int64; // is the integer 64 bits? - logic Signed; // is the opperation with a signed integer? - logic IntToFp; // is the opperation an int->fp conversion? - logic CvtOp; // convertion opperation - logic FmaOp; // fma opperation - logic DivOp; // divider opperation + logic Signed; // is the operation with a signed integer? + logic IntToFp; // is the operation an int->fp conversion? + logic CvtOp; // convertion operation + logic FmaOp; // fma operation + logic DivOp; // divider operation logic InfIn; // are any of the inputs infinity logic NaNIn; // are any of the inputs NaN @@ -128,7 +129,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( assign InfIn = XInf|YInf|ZInf; assign NaNIn = XNaN|YNaN|ZNaN; - // choose the output format depending on the opperation + // choose the output format depending on the operation // - fp -> fp: OpCtrl contains the precision of the output // - otherwise: Fmt contains the precision of the output if (P.FPSIZES == 2) diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv index 0dd22c1f4..69f25a2b0 100644 --- a/src/fpu/postproc/resultsign.sv +++ b/src/fpu/postproc/resultsign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -29,7 +30,7 @@ module resultsign( input logic [2:0] Frm, // rounding mode input logic FmaOp, // is the operation an Fma - input logic Mult, // is the fma opperation multipy + input logic Mult, // is the fma operation multipy input logic ZInf, // is Z infinity input logic InfIn, // are any of the inputs infinity input logic FmaSZero, // is the fma sum zero @@ -48,7 +49,7 @@ module resultsign( // determine the sign for a result of 0 // The IEEE754-2019 standard specifies: // - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negative infinity - // - when the exact result of an FMA opperation is non-zero, but is zero due to rounding, use the sign of the exact result + // - when the exact result of an FMA operation is non-zero, but is zero due to rounding, use the sign of the exact result // - if x = +0 or -0 then x+x=x and x-(-x)=x // - the sign of a product is the exclisive or or the opperand's signs // Zero sign will only be selected if: @@ -57,7 +58,7 @@ module resultsign( // - P is killed and Z is zero - Psgn // - Z is killed and P is zero - impossible // Zero sign calculation: - // - if a multiply opperation is done, then use the products sign(Ps) + // - if a multiply operation is done, then use the products sign(Ps) // - if the zero sum is not exactly zero i.e. Round|Sticky use the sign of the exact result (which is the product's sign) // - if an effective addition occurs (P+A or -P+-A or P--A) then use the product's sign assign Zeros = (FmaPs^FmaAs)&~(Round|Guard|Sticky)&~Mult ? Frm[1:0] == 2'b10 : FmaPs; diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index 460786135..9e2de2320 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -33,15 +34,15 @@ module round import cvw::*; #(parameter cvw_t P) ( input logic Ms, // normalized sign input logic [P.CORRSHIFTSZ-1:0] Mf, // normalized fraction // fma - input logic FmaOp, // is an fma opperation being done? + input logic FmaOp, // is an fma operation being done? input logic [P.NE+1:0] FmaMe, // exponent of the normalized sum for fma input logic FmaASticky, // addend's sticky bit // divsqrt - input logic DivOp, // is a division opperation being done + input logic DivOp, // is a division operation being done input logic DivSticky, // divsqrt sticky bit input logic [P.NE+1:0] Ue, // the divsqrt calculated expoent // cvt - input logic CvtOp, // is a convert opperation being done + input logic CvtOp, // is a convert operation being done input logic ToInt, // is the cvt op a cvt to integer input logic CvtResSubnormUf, // is the cvt result subnormal or underflow input logic CvtResUf, // does the cvt result underflow @@ -68,6 +69,7 @@ module round import cvw::*; #(parameter cvw_t P) ( logic CalcPlus1; // calculated plus1 logic FpPlus1; // do you add one to the fp result logic [P.FLEN:0] RoundAdd; // how much to add to the result + logic CvtToInt; // Convert to integer operation // what position is XLEN in? // options: @@ -111,6 +113,7 @@ module round import cvw::*; #(parameter cvw_t P) ( // determine what format the final result is in: int or fp assign IntRes = ToInt; assign FpRes = ~IntRes; + assign CvtToInt = ToInt; // under current encodings, CvtOp always is 1 when ToInt is selected, so leave it out // sticky bit calculation if (P.FPSIZES == 1) begin @@ -178,7 +181,7 @@ module round import cvw::*; #(parameter cvw_t P) ( end - // only add the Addend sticky if doing an FMA opperation + // only add the Addend sticky if doing an FMA operation // - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits) assign Sticky = FmaASticky&FmaOp | NormSticky | CvtResUf&CvtOp | FmaMe[P.NE+1]&FmaOp | DivSticky&DivOp; @@ -244,9 +247,9 @@ module round import cvw::*; #(parameter cvw_t P) ( endcase end - assign Guard = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN-1] : FpGuard; - assign LsbRes = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN] : FpLsbRes; - assign Round = ToInt&CvtOp ? Mf[P.CORRSHIFTSZ-P.XLEN-2] : FpRound; + assign Guard = CvtToInt ? Mf[P.CORRSHIFTSZ-P.XLEN-1] : FpGuard; + assign LsbRes = CvtToInt ? Mf[P.CORRSHIFTSZ-P.XLEN] : FpLsbRes; + assign Round = CvtToInt ? Mf[P.CORRSHIFTSZ-P.XLEN-2] : FpRound; always_comb begin // Determine if you add 1 @@ -272,7 +275,7 @@ module round import cvw::*; #(parameter cvw_t P) ( // If an answer is exact don't round assign Plus1 = CalcPlus1 & (Sticky|Round|Guard); - assign FpPlus1 = Plus1&~(ToInt&CvtOp); + assign FpPlus1 = Plus1&~(CvtToInt); assign UfPlus1 = UfCalcPlus1 & (Sticky|Round); // place Plus1 into the proper position for the format @@ -300,9 +303,9 @@ module round import cvw::*; #(parameter cvw_t P) ( case(PostProcSel) 2'b10: Me = FmaMe; // fma 2'b00: Me = {CvtCe[P.NE], CvtCe}&{P.NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt - // 2'b01: Me = DivDone ? Ue : '0; // divide + // 2'b01: Me = DivDone ? Ue : 0; // divide 2'b01: Me = Ue; // divide - default: Me = '0; + default: Me = 0; endcase diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv index 6c1135602..7eedc5eba 100644 --- a/src/fpu/postproc/roundsign.sv +++ b/src/fpu/postproc/roundsign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -32,9 +33,9 @@ module roundsign( input logic CvtCs, // convert result sign input logic FmaSs, // fma sum sign input logic Sqrt, // sqrt oppertion? (when using divsqrt unit) - input logic FmaOp, // is fma opperation - input logic DivOp, // is divsqrt opperation - input logic CvtOp, // is cvt opperation + input logic FmaOp, // is fma operation + input logic DivOp, // is divsqrt operation + input logic CvtOp, // is cvt operation output logic Ms // normalized result sign ); diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index 1da3556d8..b06d8db0d 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -29,12 +30,12 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( input logic [P.NORMSHIFTSZ-1:0] Shifted, // the shifted sum before LZA correction // divsqrt - input logic DivOp, // is it a divsqrt opperation + input logic DivOp, // is it a divsqrt operation input logic DivResSubnorm, // is the divsqrt result subnormal input logic [P.NE+1:0] DivUe, // the divsqrt result's exponent input logic DivSubnormShiftPos, // is the subnorm divider shift amount positive (ie not underflowed) //fma - input logic FmaOp, // is it an fma opperation + input logic FmaOp, // is it an fma operation input logic [P.NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account Subnormal or zero results input logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection input logic FmaSZero, @@ -87,5 +88,5 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( // the quotent is in the range [.5,2) if there is no early termination // if the quotent < 1 and not Subnormal then subtract 1 to account for the normalization shift - assign Ue = (DivResSubnorm & DivSubnormShiftPos) ? '0 : DivUe - {(P.NE+1)'(0), ~LZAPlus1}; + assign Ue = (DivResSubnorm & DivSubnormShiftPos) ? 0 : DivUe - {(P.NE+1)'(0), ~LZAPlus1}; endmodule diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index 76784e4a1..e3a1466fe 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -43,14 +44,14 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( input logic [P.NE+1:0] FullRe, // Result full exponent input logic [P.NF-1:0] Rf, // Result fraction // fma - input logic FmaOp, // is it a fma opperation + input logic FmaOp, // is it a fma operation // divsqrt - input logic DivOp, // is it a divsqrt opperation + input logic DivOp, // is it a divsqrt operation input logic DivByZero, // divide by zero flag // cvt - input logic CvtOp, // is it a conversion opperation + input logic CvtOp, // is it a conversion operation input logic IntZero, // is the integer input zero - input logic IntToFp, // is cvt int -> fp opperation + input logic IntToFp, // is cvt int -> fp operation input logic Int64, // is the integer 64 bits input logic Signed, // is the integer signed input logic Zfa, // Zfa conversion operation: fcvtmod.w.d @@ -338,11 +339,11 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( if (P.ZFA_SUPPORTED & P.D_SUPPORTED) // fcvtmod.w.d support always_comb begin - if (Zfa) OfIntRes2 = '0; + if (Zfa) OfIntRes2 = 0; // fcvtmod.w.d produces 0 on overflow else OfIntRes2 = OfIntRes; if (Zfa) Int64Res = {{(P.XLEN-32){CvtNegRes[P.XLEN-1]}}, CvtNegRes[31:0]}; else Int64Res = CvtNegRes[P.XLEN-1:0]; - if (Zfa) SelCvtOfRes = InfIn | NaNIn; // fcvtmod.w.d only overflows to 0 on NaN or Infinity + if (Zfa) SelCvtOfRes = InfIn | NaNIn | (CvtCe > 32 + 52); // fcvtmod.w.d only overflows to 0 on NaN or Infinity, or if the shift is so large that only zeros are left else SelCvtOfRes = IntInvalid; // regular fcvt gives an overflow if out of range end else @@ -355,7 +356,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( // select the integer output // - if the input is invalid (out of bounds NaN or Inf) then output overflow res // - if the input underflows - // - if rounding and signed opperation and negative input, output -1 + // - if rounding and signed operation and negative input, output -1 // - otherwise output a rounded 0 // - otherwise output the normal res (trmined and sign extended if nessisary) always_comb diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 145d6a701..eab224dd9 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index b3d7f901e..e5c5f3deb 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -139,15 +140,12 @@ module unpackinput import cvw::*; #(parameter cvw_t P) ( endcase always_comb - if (BadNaNBox) begin - case (Fmt) - P.FMT: PostBox = In; - P.FMT1: PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}}; - P.FMT2: PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}}; - default: PostBox = 'x; - endcase - end else - PostBox = In; + if (BadNaNBox & Fmt == P.FMT1) + PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}}; + else if (BadNaNBox) // Fmt == P.FMT2 + PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}}; + else + PostBox = In; // extract the sign bit always_comb diff --git a/src/generic/adder.sv b/src/generic/adder.sv index 4d341d6c1..f499eca88 100644 --- a/src/generic/adder.sv +++ b/src/generic/adder.sv @@ -7,6 +7,7 @@ // Purpose: Adder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv index f8d675b33..dc5f6450c 100644 --- a/src/generic/aplusbeq0.sv +++ b/src/generic/aplusbeq0.sv @@ -7,6 +7,7 @@ // Purpose: Determine if A+B = 0. Used in FP divider. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index dd473b307..cbff0e82b 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -10,6 +10,7 @@ // rising edge, but then syncs the falling edge to the posedge clk. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/binencoder.sv b/src/generic/binencoder.sv index 89093ea5b..a9349879a 100644 --- a/src/generic/binencoder.sv +++ b/src/generic/binencoder.sv @@ -6,6 +6,7 @@ // Purpose: one-hot to binary encoding. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv index c0150133c..48282ccfa 100644 --- a/src/generic/clockgater.sv +++ b/src/generic/clockgater.sv @@ -7,6 +7,7 @@ // Purpose: Clock gater model. Must use standard cell for synthesis. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/counter.sv b/src/generic/counter.sv index faba2e5e5..cc20ae71e 100644 --- a/src/generic/counter.sv +++ b/src/generic/counter.sv @@ -7,6 +7,7 @@ // Purpose: Counter with reset and enable // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/csa.sv b/src/generic/csa.sv index 91aef44dd..ac9dfe098 100644 --- a/src/generic/csa.sv +++ b/src/generic/csa.sv @@ -7,6 +7,7 @@ // Purpose: 3:2 carry-save adder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv index 6284a454c..78b816c3c 100644 --- a/src/generic/decoder.sv +++ b/src/generic/decoder.sv @@ -7,6 +7,7 @@ // Purpose: Binary encoding to one-hot decoder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flop.sv b/src/generic/flop/flop.sv index 97e0ac7e4..b7e7a82ee 100644 --- a/src/generic/flop/flop.sv +++ b/src/generic/flop/flop.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv index 2e6432519..f1db84776 100644 --- a/src/generic/flop/flopen.sv +++ b/src/generic/flop/flopen.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv index 562c4565a..08b6590a8 100644 --- a/src/generic/flop/flopenl.sv +++ b/src/generic/flop/flopenl.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable and synchronous load // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv index 2c2144ab8..565fbfa7a 100644 --- a/src/generic/flop/flopenr.sv +++ b/src/generic/flop/flopenr.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous reset // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv index 94b2b3cb0..983fae5f2 100644 --- a/src/generic/flop/flopenrc.sv +++ b/src/generic/flop/flopenrc.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous reset, enabled clear // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv index c4fc5d01b..11c128393 100644 --- a/src/generic/flop/flopens.sv +++ b/src/generic/flop/flopens.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous set // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv index 2e39ee8d6..b3edcbdf9 100644 --- a/src/generic/flop/flopr.sv +++ b/src/generic/flop/flopr.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with synchronous reset // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv deleted file mode 100644 index b35e9ccce..000000000 --- a/src/generic/flop/floprc.sv +++ /dev/null @@ -1,37 +0,0 @@ -/////////////////////////////////////////// -// floprc.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: D flip-flop with synchronous reset and clear -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module floprc #(parameter WIDTH = 8) ( - input logic clk, - input logic reset, - input logic clear, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk) - if (reset | clear ) q <= #1 0; - else q <= #1 d; -endmodule diff --git a/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv index f99088af4..d4a63cd53 100644 --- a/src/generic/flop/synchronizer.sv +++ b/src/generic/flop/synchronizer.sv @@ -7,6 +7,7 @@ // Purpose: Two-stage flip-flop synchronizer // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index aa5381a22..855b64d88 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -6,6 +6,7 @@ // Purpose: Leading Zero Counter // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 4af3c255c..186fb9c5a 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -13,6 +13,7 @@ // Documentation: // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -42,7 +43,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE output logic [WIDTH-1:0] dout ); - logic [WIDTH-1:0] RAM[DEPTH-1:0]; + bit [WIDTH-1:0] RAM[DEPTH-1:0]; // *************************************************************************** // TRUE SRAM macro diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index 55b1d75b0..64ddec259 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 5e7a4c5cf..1b5e1bdb7 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index a2c2c81fa..1744ba59f 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index e3746c181..dd1d884f5 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -11,6 +11,7 @@ // Documentation: // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -39,7 +40,7 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( output logic [WIDTH-1:0] dout ); - logic [WIDTH-1:0] RAM[DEPTH-1:0]; + bit [WIDTH-1:0] RAM[DEPTH-1:0]; // *************************************************************************** // TRUE SRAM macro @@ -48,19 +49,19 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( // 64 x 128-bit SRAM ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), - .BWEB('0), .Q(dout)); + .BWEB(0), .Q(dout)); end else if ((USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag // 64 x 44-bit SRAM ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), - .BWEB('0), .Q(dout)); + .BWEB(0), .Q(dout)); end else if ((USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag // 64 x 22-bit SRAM ram1p1rwbe_64x22 sram1 (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), - .BWEB('0), .Q(dout)); + .BWEB(0), .Q(dout)); // *************************************************************************** // READ first SRAM model diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 42435c607..83334ea76 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -12,6 +12,7 @@ // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -42,7 +43,7 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) output logic [WIDTH-1:0] rd1 ); - logic [WIDTH-1:0] mem[DEPTH-1:0]; + bit [WIDTH-1:0] mem[DEPTH-1:0]; localparam SRAMWIDTH = 32; localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; @@ -54,11 +55,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), - .WEBA('0), .WEBB(~we2), + .WEBA(0), .WEBB(~we2), .AA(ra1), .AB(wa2), - .DA('0), + .DA(0), .DB(wd2), - .BWEBA('0), .BWEBB('1), + .BWEBA(0), .BWEBB('1), .QA(rd1), .QB()); @@ -66,11 +67,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), - .WEBA('0), .WEBB(~we2), + .WEBA(0), .WEBB(~we2), .AA(ra1), .AB(wa2), - .DA('0), + .DA(0), .DB(wd2), - .BWEBA('0), .BWEBB('1), + .BWEBA(0), .BWEBB('1), .QA(rd1), .QB()); @@ -94,12 +95,12 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), - .WEBA('0), .WEBB(~we2), + .WEBA(0), .WEBB(~we2), .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), - .DA('0), + .DA(0), .DB(SRAMWriteData), - .BWEBA('0), .BWEBB(SRAMBitMask), + .BWEBA(0), .BWEBB(SRAMBitMask), .QA(SRAMReadData), .QB()); @@ -109,13 +110,14 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) // READ first SRAM model // *************************************************************************** integer i; - +/* initial begin // initialize memory for simulation only; not needed because done in the testbench now integer j; for (j=0; j < DEPTH; j++) - mem[j] = '0; + mem[j] = 0; end - +*/ + // Read logic [$clog2(DEPTH)-1:0] ra1d; flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d); diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index 302277ed0..d499442b4 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index 6da7e06d6..a1633f8e9 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_128x64.sv b/src/generic/mem/ram2p1r1wbe_128x64.sv index e181fdd07..54d0ee8dc 100644 --- a/src/generic/mem/ram2p1r1wbe_128x64.sv +++ b/src/generic/mem/ram2p1r1wbe_128x64.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_512x64.sv index 442eff90d..95185346a 100644 --- a/src/generic/mem/ram2p1r1wbe_512x64.sv +++ b/src/generic/mem/ram2p1r1wbe_512x64.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index 4236bb3f6..db3cbc846 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index c298dba63..7350eac9c 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -6,6 +6,7 @@ // Purpose: Single-ported ROM // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -33,7 +34,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) ); // Core Memory - logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; + bit [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; // dh 10/30/23 ROM macros are presently commented out // because they don't point to a generated ROM @@ -51,7 +52,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) end end - always @ (posedge clk) begin + always_ff @ (posedge clk) begin if(ce) dout <= ROM[addr]; end diff --git a/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv index ea5b92054..0854f1557 100755 --- a/src/generic/mem/rom1p1r_128x32.sv +++ b/src/generic/mem/rom1p1r_128x32.sv @@ -7,6 +7,7 @@ // Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv index 6712d10fa..7a86bc50e 100755 --- a/src/generic/mem/rom1p1r_128x64.sv +++ b/src/generic/mem/rom1p1r_128x64.sv @@ -7,6 +7,7 @@ // Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mux.sv b/src/generic/mux.sv index 9c1dfe335..5a4767c87 100644 --- a/src/generic/mux.sv +++ b/src/generic/mux.sv @@ -7,6 +7,7 @@ // Purpose: Various flavors of multiplexers // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/neg.sv b/src/generic/neg.sv index e971fc232..8621e510e 100644 --- a/src/generic/neg.sv +++ b/src/generic/neg.sv @@ -7,6 +7,7 @@ // Purpose: 2's complement negator // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index b672a08e5..433e12d37 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -7,6 +7,7 @@ // Purpose: Bin to one hot decoder. Power of 2 only. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -30,7 +31,7 @@ module onehotdecoder #(parameter WIDTH = 2) ( ); always_comb begin - decoded = '0; + decoded = 0; decoded[bin] = 1'b1; end diff --git a/src/generic/or_rows.sv b/src/generic/or_rows.sv index 476b62586..56e693abb 100644 --- a/src/generic/or_rows.sv +++ b/src/generic/or_rows.sv @@ -7,6 +7,7 @@ // Purpose: Perform OR across a 2-dimensional array of inputs to produce a 1-D array of outputs // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv index 1cddb2bfc..65882dd75 100644 --- a/src/generic/priorityonehot.sv +++ b/src/generic/priorityonehot.sv @@ -17,6 +17,7 @@ // out 00000000000100000 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv index f779d4748..23acfcfb3 100644 --- a/src/generic/prioritythermometer.sv +++ b/src/generic/prioritythermometer.sv @@ -13,6 +13,7 @@ // out 00000000000011111 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 3728ceb17..f7bc2a486 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -81,7 +82,7 @@ module hazard import cvw::*; #(parameter cvw_t P) ( // The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation. // The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions // A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation - assign StallFCause = '0; + assign StallFCause = 0; assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause; assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; assign StallMCause = WFIStallM & ~FlushMCause; diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 4c296fda2..51cf00b97 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 4a5b4bfab..3f7d0ae7a 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index fc2530aab..3876c31e4 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 59a8e4a16..5b758f123 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index 2879ba042..191919ecc 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 675387577..f32fcece9 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index d015c1195..85861b19f 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -56,8 +57,8 @@ module cnt #(parameter WIDTH = 32) ( lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult[$clog2(WIDTH):0])); popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult[$clog2(WIDTH):0])); // zero extend these results to fit into width - assign czResult[WIDTH-1:$clog2(WIDTH)+1] = '0; - assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = '0; + assign czResult[WIDTH-1:$clog2(WIDTH)+1] = 0; + assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = 0; mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult); endmodule diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 1feca6e1e..5ce1139fb 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 7701c0d65..903b67eeb 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 9ae3df42d..52ed8ef34 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 4dc3ad1bd..6e1948c33 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv index 0803d8b2f..466167fb3 100644 --- a/src/ieu/comparator.sv +++ b/src/ieu/comparator.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 35da15efe..d9c076dbd 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index c2bcaf8c3..eb6fd1d81 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index 4f7ee387f..b090c3f5e 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index ddd6fe089..438ca7534 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index 2b76bca17..bf6990ea9 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index bb0160c71..af44b6136 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index bc245d984..9f5dd2a43 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 64297c44a..568eeecb5 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -9,6 +9,7 @@ // Prediction made during the fetch stage and corrected in the execution stage. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -87,15 +88,17 @@ module bpred import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] BPBTAD; - logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; - logic BPBranchF, BPJumpF, BPReturnF, BPCallF; - logic BPBranchD, BPJumpD, BPReturnD, BPCallD; - logic ReturnD, CallD; - logic ReturnE, CallE; - logic BranchM, JumpM, ReturnM, CallM; - logic BranchW, JumpW, ReturnW, CallW; - logic BPReturnWrongD; + logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; + logic BPBranchF, BPJumpF, BPReturnF, BPCallF; + logic BPBranchD, BPJumpD, BPReturnD, BPCallD; + logic ReturnD, CallD; + logic ReturnE, CallE; + logic BranchM, JumpM, ReturnM, CallM; + logic BranchW, JumpW, ReturnW, CallW; + logic BPReturnWrongD; logic [P.XLEN-1:0] BPBTAE; + logic BPBTAWrongM; + logic PCSrcM; // Part 1 branch direction prediction if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor @@ -143,6 +146,8 @@ module bpred import cvw::*; #(parameter cvw_t P) ( .BranchD, .BranchE, .BranchM, .PCSrcE); end + flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); + // Part 2 Branch target address prediction // BTB contains target address for all CFI @@ -151,6 +156,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPBTAF, .BPBTAD, .BPBTAE, .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}), + .BPBTAWrongM, .IClassWrongM, .IClassWrongE, .IEUAdrE, .IEUAdrM, .InstrClassD({CallD, ReturnD, JumpD, BranchD}), @@ -195,7 +201,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( if(P.ZIHPM_SUPPORTED) begin logic [P.XLEN-1:0] RASPCD, RASPCE; - logic BTAWrongE, RASPredPCWrongE; + logic RASPredPCWrongE; // performance counters // 1. class (class wrong / minstret) (IClassWrongM / csr) // Correct now // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) @@ -207,17 +213,18 @@ module bpred import cvw::*; #(parameter cvw_t P) ( // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. // **** use BPBTAWrongM from BTB. - assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE; flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); - flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {BPDirPredWrongE, BTAWrongE, RASPredPCWrongE}, - {BPDirPredWrongM, BTAWrongM, RASPredPCWrongM}); + flopenrc #(2) BPPredWrongRegM(clk, reset, FlushM, ~StallM, + {BPDirPredWrongE, RASPredPCWrongE}, + {BPDirPredWrongM, RASPredPCWrongM}); + + assign BTAWrongM = BPBTAWrongM & PCSrcM; end else begin - assign {BTAWrongM, RASPredPCWrongM} = '0; + assign {BTAWrongM, RASPredPCWrongM} = 0; end // **** Fix me diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 567e4d3cd..448be38d0 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -38,6 +39,7 @@ module btb import cvw::*; #(parameter cvw_t P, output logic [P.XLEN-1:0] BPBTAD, output logic [P.XLEN-1:0] BPBTAE, output logic [3:0] BTBIClassF, // BTB's guess at instruction class + output logic BPBTAWrongM, // update input logic IClassWrongM, // BTB's instruction class guess was wrong input logic IClassWrongE, @@ -56,7 +58,7 @@ module btb import cvw::*; #(parameter cvw_t P, logic [P.XLEN-1:0] IEUAdrW; logic [P.XLEN-1:0] PCW; logic BTBWrongE, BPBTAWrongE; - logic BTBWrongM, BPBTAWrongM; + logic BTBWrongM; // hashing function for indexing the PC diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index fcdf46655..7f5906084 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -10,6 +10,7 @@ // Purpose: gshare and Global History Branch predictors // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 7ae9f0282..1fa6f21f6 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -10,6 +10,7 @@ // Purpose: Global History Branch predictor with parameterized global history register // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index e4895d4b7..8d0ecc890 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -9,6 +9,7 @@ // Call, Return, Jump, and Branch // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -64,7 +65,7 @@ module icpred import cvw::*; #(parameter cvw_t P, assign CJumpF = cjal | cj | cjr | cjalr; assign CBranchF = CompressedOpcF[4:1] == 4'h7; end else begin - assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = '0; + assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = 0; end assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F; diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index 4d6d536a7..fd8acbc82 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -8,6 +8,7 @@ // Purpose: local history branch predictor with ahead pipelining and SRAM memories. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index d3a694c33..5c4485f3f 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -9,6 +9,7 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 95399e65a..6920f4ae1 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -8,6 +8,7 @@ // Purpose: Local history branch predictor with speculation and repair using CBH. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -115,7 +116,7 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, SpeculativeFlushedF <= #1 FlushedBits[IndexLHRNextF]; if (reset | FlushD) FlushedBits <= #1 '1; if(BranchD & ~StallE & ~FlushE) begin - FlushedBits[IndexLHRD] <= #1 '0; + FlushedBits[IndexLHRD] <= #1 0; end end diff --git a/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv index 470375adc..7dd33ffb3 100644 --- a/src/ifu/bpred/satCounter2.sv +++ b/src/ifu/bpred/satCounter2.sv @@ -9,6 +9,7 @@ // Purpose: 2 bit starting counter // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 5b2fcb9b8..583b8d805 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -9,6 +9,7 @@ // Purpose: 2 bit saturating counter predictor with parameterized table depth. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 50617d3c5..e6c4fcd9a 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -12,6 +12,7 @@ // *** probably need more documentation in this file since the book is very light on decompression. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 0bd899306..f12e02ec9 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -8,6 +8,7 @@ // PC, branch prediction, instruction cache // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -193,10 +194,10 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin - assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateDAF} = '0; + assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateDAF} = 0; assign PCPF = PCFExt[P.PA_BITS-1:0]; - assign CacheableF = '1; - assign SelIROM = '0; + assign CacheableF = 1; + assign SelIROM = 0; end //////////////////////////////////////////////////////////////////////////////////////////////// @@ -233,8 +234,8 @@ module ifu import cvw::*; #(parameter cvw_t P) ( logic ICacheBusAck; logic [1:0] CacheBusRW, BusRW, CacheRWF; - assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; - assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; + assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : 0; + assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : 0; // *** RT: PAdr and NextSet are replaced with mux between PCPF/IEUAdrM and PCSpillNextF/IEUAdrE. cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), @@ -254,7 +255,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0)); - ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) + ahbcacheinterface #(P, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), @@ -270,7 +271,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( end else begin : passthrough assign IFUHADDR = PCPF; logic [1:0] BusRW; - assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0; + assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : 0; assign IFUHSIZE = 3'b010; ahbinterface #(P.XLEN, 1'b0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), @@ -278,15 +279,15 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .HWSTRB(), .BusRW, .BusAtomic('0), .ByteMask(), .WriteData('0), .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); - assign CacheCommittedF = '0; + assign CacheCommittedF = 0; if(P.IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(ShiftUncachedInstr, IROMInstrF, SelIROM, InstrRawF); else assign InstrRawF = ShiftUncachedInstr; assign IFUHBURST = 3'b0; - assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0; + assign {ICacheMiss, ICacheAccess, ICacheStallF} = 0; end end else begin : nobus // block: bus - assign {BusStall, CacheCommittedF} = '0; - assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; + assign {BusStall, CacheCommittedF} = 0; + assign {ICacheStallF, ICacheMiss, ICacheAccess} = 0; assign InstrRawF = IROMInstrF; end @@ -354,7 +355,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .BTBBranchF(1'b0), .BPCallF(), .BPReturnF(), .BPJumpF(), .BPBranchF(), .IClassWrongM, .IClassWrongE(), .BPReturnWrongD()); flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, BPWrongM); - assign RASPredPCWrongM = '0; + assign RASPredPCWrongM = 0; assign BPDirPredWrongM = BPWrongM; assign BTAWrongM = BPWrongM; assign InstrClassM = {CallM, ReturnM, JumpM, BranchM}; diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index 0b29c72cf..e5e7a7f96 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -7,6 +7,7 @@ // // Purpose: simple instruction ROM // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 39b30abd1..ea045c43f 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 8710b1d6a..d4603941b 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -36,6 +37,7 @@ module align import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM input logic [2:0] Funct3M, // Size of memory operation + input logic FpLoadStoreM, // Floating point Load or Store input logic [1:0] MemRWM, input logic [P.LLEN*2-1:0] DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed input logic CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched @@ -51,7 +53,6 @@ module align import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill output logic SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline - output logic SelStoreDelay, //*** this is bad. really don't like moving this outside output logic [P.LLEN-1:0] DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction output logic SpillStallM); @@ -71,6 +72,7 @@ module align import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] IEUAdrIncrementM; + localparam OFFSET_LEN = $clog2(LLENINBYTES); logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM; logic [$clog2(LLENINBYTES)+2:0] ShiftAmount; logic PotentialSpillM; @@ -92,22 +94,25 @@ module align import cvw::*; #(parameter cvw_t P) ( // compute misalignement always_comb begin - case (Funct3M[1:0]) - 2'b00: AccessByteOffsetM = '0; // byte access - 2'b01: AccessByteOffsetM = {2'b00, IEUAdrM[0]}; // half access - 2'b10: AccessByteOffsetM = {1'b0, IEUAdrM[1:0]}; // word access - 2'b11: AccessByteOffsetM = IEUAdrM[2:0]; // double access - default: AccessByteOffsetM = IEUAdrM[2:0]; + case (Funct3M & {FpLoadStoreM, 2'b11}) + 3'b000: AccessByteOffsetM = 0; // byte access + 3'b001: AccessByteOffsetM = {{OFFSET_LEN-1{1'b0}}, IEUAdrM[0]}; // half access + 3'b010: AccessByteOffsetM = {{OFFSET_LEN-2{1'b0}}, IEUAdrM[1:0]}; // word access + 3'b011: if(P.LLEN >= 64) AccessByteOffsetM = {{OFFSET_LEN-3{1'b0}}, IEUAdrM[2:0]}; // double access + else AccessByteOffsetM = 0; // shouldn't happen + 3'b100: if(P.LLEN == 128) AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0]; // quad access + else AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0]; + default: AccessByteOffsetM = 0; // shouldn't happen endcase case (Funct3M[1:0]) - 2'b00: PotentialSpillM = '0; // byte access + 2'b00: PotentialSpillM = 0; // byte access 2'b01: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:1] == '1; // half access 2'b10: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:2] == '1; // word access 2'b11: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:3] == '1; // double access - default: PotentialSpillM = '0; + default: PotentialSpillM = 0; endcase end - assign MisalignedM = (|MemRWM) & (AccessByteOffsetM != '0); + assign MisalignedM = (|MemRWM) & (AccessByteOffsetM != 0); assign ValidSpillM = MisalignedM & PotentialSpillM & ~CacheBusHPWTStall; // Don't take the spill if there is a stall @@ -117,20 +122,17 @@ module align import cvw::*; #(parameter cvw_t P) ( always_comb begin case (CurrState) - STATE_READY: if (ValidSpillM & ~MemRWM[0]) NextState = STATE_SPILL; // load spill - else if(ValidSpillM) NextState = STATE_STORE_DELAY; // store spill + STATE_READY: if (ValidSpillM) NextState = STATE_SPILL; // load spill else NextState = STATE_READY; // no spill STATE_SPILL: if(StallM) NextState = STATE_SPILL; else NextState = STATE_READY; - STATE_STORE_DELAY: NextState = STATE_SPILL; default: NextState = STATE_READY; endcase end - assign SelSpillM = (CurrState == STATE_SPILL | CurrState == STATE_STORE_DELAY); - assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall) | (CurrState == STATE_STORE_DELAY); + assign SelSpillM = CurrState == STATE_SPILL; + assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall); assign SpillSaveM = (CurrState == STATE_READY) & ValidSpillM & ~FlushM; - assign SelStoreDelay = (CurrState == STATE_STORE_DELAY); // *** Can this be merged into the PreLSURWM logic? assign SpillStallM = SelSpillE; //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -146,7 +148,7 @@ module align import cvw::*; #(parameter cvw_t P) ( // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit) // 8 * is for shifting by bytes not bits - assign ShiftAmount = SelHPTW ? '0 : {AccessByteOffsetM, 3'b0}; // AND gate + assign ShiftAmount = SelHPTW ? 0 : {AccessByteOffsetM, 3'b0}; // AND gate assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount; assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0]; diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index c8b7ccee3..4d6330215 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 117a42c2b..7dbd0c8a2 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index a44086a15..1386db96f 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv index 551f08de4..7c042886a 100644 --- a/src/lsu/endianswap.sv +++ b/src/lsu/endianswap.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index 66a9956dc..f7d1d4799 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index a63468d61..9618e2cae 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -142,7 +143,6 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic [(P.LLEN-1)/8:0] ByteMaskExtendedM; // Selects which bytes within a word to write logic [1:0] MemRWSpillM; logic SpillStallM; - logic SelStoreDelay; logic DTLBMissM; // DTLB miss causes HPTW walk logic DTLBWriteM; // Writes PTE and PageType to DTLB @@ -163,28 +163,27 @@ module lsu import cvw::*; #(parameter cvw_t P) ( flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); if(MISALIGN_SUPPORT) begin : ziccslm_align logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM; - align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, + align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, .MemRWM, .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW, .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM, - .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM, - .SelStoreDelay); + .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM); assign IEUAdrExtM = {2'b00, IEUAdrSpillM}; assign IEUAdrExtE = {2'b00, IEUAdrSpillE}; end else begin : no_ziccslm_align assign IEUAdrExtM = {2'b00, IEUAdrM}; assign IEUAdrExtE = {2'b00, IEUAdrE}; - assign SelSpillE = '0; + assign SelSpillE = 0; assign DCacheReadDataWordSpillM = DCacheReadDataWordM; assign ByteMaskSpillM = ByteMaskM; assign LSUWriteDataSpillM = LSUWriteDataM; assign MemRWSpillM = MemRWM; - assign {SpillStallM, SelStoreDelay} = '0; + assign {SpillStallM} = 0; end if(P.ZICBOZ_SUPPORTED) begin : cboz - mux2 #(P.XLEN) writedatacbozmux(WriteDataM, '0, CMOpM[3], WriteDataZM); - end else begin : cboz + assign WriteDataZM = CMOpM[3] ? 0 : WriteDataM; + end else begin : cboz assign WriteDataZM = WriteDataM; end @@ -217,8 +216,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM; assign LoadPageFaultM = LSULoadPageFaultM; assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM; - assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; - assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0; + assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = 0; + assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = 0; end // CommittedM indicates the cache, bus, or HPTW are busy with a multiple cycle operation. @@ -254,8 +253,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin // No MMU, so no PMA/page faults and no address translation - assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0; - assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = '0; + assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = 0; + assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = 0; assign PAdrM = IHAdrM[P.PA_BITS-1:0]; assign CacheableM = 1'b1; assign SelDTIM = P.DTIM_SUPPORTED & ~P.BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM. If there is @@ -280,7 +279,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // The DTIM uses untranslated addresses, so it is not compatible with virtual memory. mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr); - assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0; + assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : 0; // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length. // **** create config to support DTIM with floating point. // Add support for cboz @@ -317,22 +316,22 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(P.ZICBOZ_SUPPORTED) begin assign BusCMOZero = CMOpM[3] & ~CacheableM; - assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : '0; + assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : 0; assign BusAtomic = AtomicM[1] & ~CacheableM; end else begin - assign BusCMOZero = '0; - assign CacheCMOpM = '0; - assign BusAtomic = '0; + assign BusCMOZero = 0; + assign CacheCMOpM = 0; + assign BusAtomic = 0; end - assign BusRW = ~CacheableM & ~SelDTIM ? LSURWM : '0; + assign BusRW = (~CacheableM & ~SelDTIM )? LSURWM : 0; assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM; - assign CacheRWM = CacheableM & ~SelDTIM ? LSURWM : '0; + assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : 0; assign FlushDCache = FlushDCacheM & ~(SelHPTW); cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), - .CacheRW(SelStoreDelay ? 2'b00 : CacheRWM), + .CacheRW(CacheRWM), .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .CacheWriteData(LSUWriteDataSpillM), .SelHPTW, @@ -345,7 +344,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign DCacheStallM = CacheStall & ~IgnoreRequestTLB; assign CacheBusRW = CacheBusRWTemp; - ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( + ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), @@ -366,7 +365,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( end else begin : passthrough // No Cache, use simple ahbinterface instad of ahbcacheinterface logic [1:0] BusRW; // Non-DTIM memory access, ignore cacheableM logic [P.XLEN-1:0] FetchBuffer; - assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; + assign BusRW = (~IgnoreRequestTLB & ~SelDTIM) ? LSURWM : 0; assign LSUHADDR = PAdrM; assign LSUHSIZE = LSUFunct3M; @@ -380,14 +379,14 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]); else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats. assign LSUHBURST = 3'b0; - assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; + assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = 0; end end else begin: nobus // block: bus, only DTIM - assign LSUHWDATA = '0; + assign LSUHWDATA = 0; assign ReadDataWordMuxM = DTIMReadDataWordM; - assign {BusStall, BusCommittedM} = '0; - assign {DCacheMiss, DCacheAccess} = '0; - assign {DCacheStallM, DCacheCommittedM} = '0; + assign {BusStall, BusCommittedM} = 0; + assign {DCacheMiss, DCacheAccess} = 0; + assign {DCacheStallM, DCacheCommittedM} = 0; end assign LSUBusStallM = BusStall & ~IgnoreRequestTLB; @@ -405,14 +404,18 @@ module lsu import cvw::*; #(parameter cvw_t P) ( end if (P.F_SUPPORTED) - mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM); + if (P.FLEN >= P.XLEN) + mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM); + else + mux2 #(P.LLEN) datamux(IMAWriteDataM, {{{P.XLEN-P.FLEN}{1'b0}}, FWriteDataM}, FpLoadStoreM, IMAFWriteDataM); + else assign IMAFWriteDataM = IMAWriteDataM; ///////////////////////////////////////////////////////////////////////////////////////////// // Subword Accesses ///////////////////////////////////////////////////////////////////////////////////////////// - subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, + subwordread #(P) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[3:0]), .BigEndianM, .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM); diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv index e5666eb84..a5ccd12bf 100644 --- a/src/lsu/subwordread.sv +++ b/src/lsu/subwordread.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -27,98 +28,47 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module subwordread #(parameter LLEN) - ( - input logic [LLEN-1:0] ReadDataWordMuxM, - input logic [2:0] PAdrM, - input logic [2:0] Funct3M, - input logic FpLoadStoreM, - input logic BigEndianM, - output logic [LLEN-1:0] ReadDataM +module subwordread import cvw::*; #(parameter cvw_t P) ( + input logic [P.LLEN-1:0] ReadDataWordMuxM, + input logic [3:0] PAdrM, + input logic [2:0] Funct3M, + input logic FpLoadStoreM, + input logic BigEndianM, + output logic [P.LLEN-1:0] ReadDataM ); + localparam ADRBITS = $clog2(P.LLEN)-3; + + logic [ADRBITS-1:0] PAdrSwapM; logic [7:0] ByteM; logic [15:0] HalfwordM; - logic [2:0] PAdrSwap; - // Funct3M[2] is the unsigned bit. mask upper bits. - // Funct3M[1:0] is the size of the memory access. - assign PAdrSwap = PAdrM ^ {3{BigEndianM}}; + logic [31:0] WordM; + logic [63:0] DblWordM; - if (LLEN == 64) begin:swrmux - // ByteMe mux - always_comb - case(PAdrSwap[2:0]) - 3'b000: ByteM = ReadDataWordMuxM[7:0]; - 3'b001: ByteM = ReadDataWordMuxM[15:8]; - 3'b010: ByteM = ReadDataWordMuxM[23:16]; - 3'b011: ByteM = ReadDataWordMuxM[31:24]; - 3'b100: ByteM = ReadDataWordMuxM[39:32]; - 3'b101: ByteM = ReadDataWordMuxM[47:40]; - 3'b110: ByteM = ReadDataWordMuxM[55:48]; - 3'b111: ByteM = ReadDataWordMuxM[63:56]; - endcase - - // halfword mux - always_comb - case(PAdrSwap[2:1]) - 2'b00: HalfwordM = ReadDataWordMuxM[15:0]; - 2'b01: HalfwordM = ReadDataWordMuxM[31:16]; - 2'b10: HalfwordM = ReadDataWordMuxM[47:32]; - 2'b11: HalfwordM = ReadDataWordMuxM[63:48]; - endcase - - logic [31:0] WordM; - - always_comb - case(PAdrSwap[2]) - 1'b0: WordM = ReadDataWordMuxM[31:0]; - 1'b1: WordM = ReadDataWordMuxM[63:32]; - endcase + // invert lsbs of address to select appropriate subword for big endian + if (P.BIGENDIAN_SUPPORTED) assign PAdrSwapM = PAdrM[ADRBITS-1:0] ^ {ADRBITS{BigEndianM}}; + else assign PAdrSwapM = PAdrM[ADRBITS-1:0]; - logic [63:0] DblWordM; - assign DblWordM = ReadDataWordMuxM[63:0]; + // Use indexed part select to imply muxes to select each size of subword + if (P.LLEN == 128) mux2 #(64) dblmux(ReadDataWordMuxM[63:0], ReadDataWordMuxM[127:64], PAdrSwapM[3], DblWordM); + else if (P.LLEN == 64) assign DblWordM = ReadDataWordMuxM; + if (P.LLEN >= 64) mux2 #(32) wordmux(DblWordM[31:0], DblWordM[63:32], PAdrSwapM[2], WordM); + else assign WordM = ReadDataWordMuxM; + mux2 #(16) halfwordmux(WordM[15:0], WordM[31:16], PAdrSwapM[1], HalfwordM); + mux2 #(8) bytemux(HalfwordM[7:0], HalfwordM[15:8], PAdrSwapM[0], ByteM); - // sign extension/ NaN boxing - always_comb + // sign extension/ NaN boxing + always_comb case(Funct3M) - 3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb - 3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh - 3'b010: ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw - 3'b011: ReadDataM = {{LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld - 3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu - //3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128 - 3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu - 3'b110: ReadDataM = {{LLEN-32{1'b0}}, WordM[31:0]}; // lwu - default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen + 3'b000: ReadDataM = {{(P.LLEN-8){ByteM[7]}}, ByteM}; // lb + 3'b001: ReadDataM = {{P.LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh + 3'b010: ReadDataM = {{P.LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw + 3'b011: if (P.LLEN >= 64) ReadDataM = {{P.LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld + else ReadDataM = ReadDataWordMuxM; // shouldn't happen + 3'b100: if (P.LLEN == 128) ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{P.LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq + else ReadDataM = {{P.LLEN-8{1'b0}}, ByteM[7:0]}; // lbu + 3'b101: ReadDataM = {{P.LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu + 3'b110: ReadDataM = {{P.LLEN-32{1'b0}}, WordM[31:0]}; // lwu + default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen endcase - - end else begin:swrmux // 32-bit - // byte mux - always_comb - case(PAdrSwap[1:0]) - 2'b00: ByteM = ReadDataWordMuxM[7:0]; - 2'b01: ByteM = ReadDataWordMuxM[15:8]; - 2'b10: ByteM = ReadDataWordMuxM[23:16]; - 2'b11: ByteM = ReadDataWordMuxM[31:24]; - endcase - - // halfword mux - always_comb - case(PAdrSwap[1]) - 1'b0: HalfwordM = ReadDataWordMuxM[15:0]; - 1'b1: HalfwordM = ReadDataWordMuxM[31:16]; - endcase - - // sign extension - always_comb - case(Funct3M) - 3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb - 3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh - 3'b010: ReadDataM = {{LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw - 3'b011: ReadDataM = ReadDataWordMuxM; // fld - 3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu - 3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu - default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen - endcase - end endmodule diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv index ad21b3c25..659d6d9c7 100644 --- a/src/lsu/subwordwrite.sv +++ b/src/lsu/subwordwrite.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -54,9 +55,9 @@ module subwordwrite #(parameter LLEN) ( end else begin:sww // 32-bit always_comb case(LSUFunct3M[1:0]) - 2'b00: LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}}; // sb - 2'b01: LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}}; // sh - 2'b10: LittleEndianWriteDataM = IMAFWriteDataM; // sw + 2'b00: LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}}; // sb + 2'b01: LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}}; // sh + 2'b10: LittleEndianWriteDataM = IMAFWriteDataM; // sw default: LittleEndianWriteDataM = IMAFWriteDataM; // shouldn't happen endcase end diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index 5737bdc9b..d8db91cbc 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -41,7 +42,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)( assign ByteMaskExtended = ExtendedByteMask[WORDLEN*2/8-1:WORDLEN/8]; end else begin assign ByteMask = (('d2**('d2**Size))-'d1) << Adr; - assign ByteMaskExtended = '0; + assign ByteMaskExtended = 0; end /* Equivalent to the following diff --git a/src/mdu/div.sv b/src/mdu/div.sv index c550c06fc..2ae35d8f4 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv index 712e98866..f478ad86f 100644 --- a/src/mdu/divstep.sv +++ b/src/mdu/divstep.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index e152fc6de..886eaf2b3 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/mul.sv b/src/mdu/mul.sv index a5946b95c..65eaefd82 100644 --- a/src/mdu/mul.sv +++ b/src/mdu/mul.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv index 492d55372..bf092dbc6 100644 --- a/src/mmu/adrdec.sv +++ b/src/mmu/adrdec.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -48,5 +49,5 @@ module adrdec #(parameter PA_BITS) ( assign SizeValid = SizeMask[Size]; // Select this peripheral if the address matches, the peripheral is supported, and the type and size of access is ok - assign Sel = Match & Supported & AccessValid & SizeValid; + assign Sel = Match & Supported & AccessValid & SizeValid; // exclusion-tag: adrdecSel endmodule diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index 282918484..d71fef82a 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 82eeaef87..77e73e696 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -13,6 +13,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // @@ -93,7 +94,6 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic [P.PA_BITS-1:0] HPTWReadAdr; logic SelHPTWAdr; logic [P.XLEN+1:0] HPTWAdrExt; - logic ITLBMissOrUpdateDAF; logic DTLBMissOrUpdateDAM; logic LSUAccessFaultM; logic [P.PA_BITS-1:0] HPTWAdr; @@ -113,12 +113,12 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // map hptw access faults onto either the original LSU load/store fault or instruction access fault assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; assign HPTWFaultM = LSUAccessFaultM | PBMTFaultM; - assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; + assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; assign HPTWStoreAmoAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[0]; assign HPTWInstrAccessFault = LSUAccessFaultM & ~DTLBWalk; - assign HPTWLoadPageFault = PBMTFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; - assign HPTWStoreAmoPageFault = PBMTFaultM & DTLBWalk & MemRWM[0]; - assign HPTWInstrPageFault = PBMTFaultM & ~DTLBWalk; + assign HPTWLoadPageFault = PBMTFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; + assign HPTWStoreAmoPageFault = PBMTFaultM & DTLBWalk & MemRWM[0]; + assign HPTWInstrPageFault = PBMTFaultM & ~DTLBWalk; flopr #(7) HPTWAccesFaultReg(clk, reset, {TakeHPTWFault, HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault, HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault}, @@ -127,17 +127,18 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign TakeHPTWFault = WalkerState != IDLE; - assign LoadAccessFaultM = TakeHPTWFault ? HPTWLoadAccessFaultDelay : LSULoadAccessFaultM; + // Improve timing by taking HPTW faults off critical path because these are multicycle operations anyway + assign LoadAccessFaultM = TakeHPTWFault ? HPTWLoadAccessFaultDelay : LSULoadAccessFaultM; assign StoreAmoAccessFaultM = TakeHPTWFault ? HPTWStoreAmoAccessFaultDelay : LSUStoreAmoAccessFaultM; assign HPTWInstrAccessFaultF = TakeHPTWFault ? HPTWInstrAccessFaultDelay : 1'b0; - assign LoadPageFaultM = TakeHPTWFault ? HPTWLoadPageFaultDelay : LSULoadPageFaultM; - assign StoreAmoPageFaultM = TakeHPTWFault ? HPTWStoreAmoPageFaultDelay : LSUStoreAmoPageFaultM; - assign HPTWInstrPageFaultF = TakeHPTWFault ? HPTWInstrPageFaultDelay : 1'b0; + assign LoadPageFaultM = TakeHPTWFault ? HPTWLoadPageFaultDelay : LSULoadPageFaultM; + assign StoreAmoPageFaultM = TakeHPTWFault ? HPTWStoreAmoPageFaultDelay : LSUStoreAmoPageFaultM; + assign HPTWInstrPageFaultF = TakeHPTWFault ? HPTWInstrPageFaultDelay : 1'b0; // Extract bits from CSRs and inputs assign SvMode = SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]; assign BasePageTablePPN = SATP_REGW[P.PPN_BITS-1:0]; - assign TLBMiss = (DTLBMissOrUpdateDAM | ITLBMissOrUpdateDAF); + assign TLBMiss = (DTLBMissOrUpdateDAM | ITLBMissF); // Determine which address to translate mux2 #(P.XLEN) vadrmux(PCSpillF, IEUAdrExtM[P.XLEN-1:0], DTLBWalk, TranslationVAdr); @@ -172,7 +173,8 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] AccessedPTE; assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit - assign ReadDataNoXM = (ReadDataM[0] === 'x) ? '0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation. + //assign ReadDataNoXM = (ReadDataM[0] === 'x) ? 0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation. + assign ReadDataNoXM = ReadDataM; // *** temporary fix for synthesis; === and x in line above are not synthesizable. mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0 flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); @@ -203,7 +205,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // memory access. If there is the PTE needs to be updated seting Access // and possibly also Dirty. Dirty is set if the operation is a store/amo. // However any other fault should not cause the update, and updates are in software when ENVCFG_ADUE = 0 - assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_ADUE & ~OtherPageFault; + assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_ADUE & ~OtherPageFault; assign HPTWRW[0] = (WalkerState == UPDATE_PTE); // HPTWRW[0] will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0 so WalkerState never is UPDATE_PTE assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0 @@ -211,9 +213,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( end else begin // block: hptwwrites assign NextPTE = ReadDataNoXM; assign HPTWAdr = HPTWReadAdr; - assign HPTWUpdateDA = '0; - assign UpdatePTE = '0; - assign HPTWRW[0] = '0; + assign HPTWUpdateDA = 0; + assign UpdatePTE = 0; + assign HPTWRW[0] = 0; end // Enable and select signals based on states @@ -283,7 +285,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) - IDLE: if (TLBMiss & ~DCacheBusStallM) NextWalkerState = InitialWalkerState; + IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; L3_ADR: NextWalkerState = L3_RD; // first access in SV48 L3_RD: if (DCacheBusStallM) NextWalkerState = L3_RD; @@ -294,7 +296,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( L2_RD: if (DCacheBusStallM) NextWalkerState = L2_RD; else if(HPTWFaultM) NextWalkerState = FAULT; else NextWalkerState = L1_ADR; - L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32 + L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32 else NextWalkerState = LEAF; L1_RD: if (DCacheBusStallM) NextWalkerState = L1_RD; else if(HPTWFaultM) NextWalkerState = FAULT; @@ -320,9 +322,8 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // The FSM directly transistions to IDLE to ready for the next operation when the delayed version will not be high. assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay; - assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss); + assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss); - assign ITLBMissOrUpdateDAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF); assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM); // HTPW address/data/control muxing diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index dffa7be76..e842016a2 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -74,6 +75,8 @@ module mmu import cvw::*; #(parameter cvw_t P, logic TLBPageFault; // Page fault from TLB logic ReadNoAmoAccessM; // Read that is not part of atomic operation causes Load faults. Otherwise StoreAmo faults logic [1:0] PBMemoryType; // PBMT field of PTE during TLB hit, or 00 otherwise + logic AmoMisalignedCausesAccessFaultM; // Misaligned AMO is not handled by hardware even with ZICCLSM, so it throws an access fault instead of misaligned with ZICCLSM + logic AmoAccessM; // AMO access detected when ReadAccessM and WriteAccessM are simultaneously asserted // only instantiate TLB if Virtual Memory is supported if (P.VIRTMEM_SUPPORTED) begin:tlb @@ -123,24 +126,30 @@ module mmu import cvw::*; #(parameter cvw_t P, assign PMPLoadAccessFaultM = 0; end - assign ReadNoAmoAccessM = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault - - // Access faults - // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. - assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~TLBMiss; - assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~TLBMiss; - assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~TLBMiss; + assign ReadNoAmoAccessM = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault + assign AmoAccessM = ReadAccessM & WriteAccessM; // Misaligned faults - always_comb // exclusion-tag: immu-wordaccess + always_comb // exclusion-tag: immu-wordaccess case(Size[1:0]) 2'b00: DataMisalignedM = 0; // lb, sb, lbu 2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu 2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu 2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd endcase + // When ZiCCLSM_SUPPORTED, misalgined cachable loads and stores are handled in hardware so they do not throw a misaligned fault assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable); - assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & (~(P.ZICCLSM_SUPPORTED & Cacheable) | ReadAccessM); // Misaligned AMO faults even if ZICCLSM supported + assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable); // Store and AMO both assert WriteAccess + + // Access faults + // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. + assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~TLBMiss; + assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~TLBMiss; + // a misaligned AMO causes an access fault rather than a misaligned fault if a misaligned load/store is handled in hardware + // this is subtle - see privileged spec 3.6.3.3 + // AMO is detected as ReadAccess & WriteAccess + assign AmoMisalignedCausesAccessFaultM = DataMisalignedM & AmoAccessM & (P.ZICCLSM_SUPPORTED & Cacheable); + assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM | AmoMisalignedCausesAccessFaultM) & ~TLBMiss; // Specify which type of page fault is occurring assign InstrPageFaultF = TLBPageFault & ExecuteAccessF; diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 896274554..84e41ba65 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 9f283772d..7226237f6 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -13,6 +13,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index ef8c42aac..30a525744 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -70,13 +71,13 @@ module pmpchecker import cvw::*; #(parameter cvw_t P) ( priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); // *** switch to this logic when PMP is initialized for non-machine mode + assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); - assign PMPCBOMAccessFault = EnforcePMP & (|CMOpM[2:0]) & ~|((R|W) & FirstMatch) ; - assign PMPCBOZAccessFault = EnforcePMP & CMOpM[3] & ~|(W & FirstMatch) ; - assign PMPCMOAccessFault = PMPCBOZAccessFault | PMPCBOMAccessFault; + assign PMPCBOMAccessFault = EnforcePMP & (|CMOpM[2:0]) & ~|((R|W) & FirstMatch) ; // exclusion-tag: immu-pmpcbom + assign PMPCBOZAccessFault = EnforcePMP & CMOpM[3] & ~|(W & FirstMatch) ; // exclusion-tag: immu-pmpcboz + assign PMPCMOAccessFault = PMPCBOZAccessFault | PMPCBOMAccessFault; // exclusion-tag: immu-pmpcboaccess assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; - assign PMPStoreAmoAccessFaultM = (EnforcePMP & WriteAccessM & ~|(W & FirstMatch)) | PMPCMOAccessFault; + assign PMPStoreAmoAccessFaultM = (EnforcePMP & WriteAccessM & ~|(W & FirstMatch)) | PMPCMOAccessFault; // exclusion-tag: immu-pmpstoreamoaccessfault assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ; endmodule diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index a417bb530..5fbd10caf 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv index e591498c4..aa569f2dd 100644 --- a/src/mmu/tlb/tlbcam.sv +++ b/src/mmu/tlb/tlbcam.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index 9471fb3d9..f5856ef56 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index aa9ec348a..83074deb3 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 18014155a..4776b5afb 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv index 9652e21ef..d615d1370 100644 --- a/src/mmu/tlb/tlbmixer.sv +++ b/src/mmu/tlb/tlbmixer.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -97,6 +98,6 @@ module tlbmixer import cvw::*; #(parameter cvw_t P) ( // Output the hit physical address if translation is currently on. // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal - mux2 #(P.PA_BITS) hitmux('0, {PPNMixed2, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system + assign TLBPAdr = TLBHit ? {PPNMixed2, Offset} : 0; endmodule diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 1a667d847..620f338a1 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv index 5e17e86eb..910db3aec 100644 --- a/src/mmu/tlb/tlbramline.sv +++ b/src/mmu/tlb/tlbramline.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv index a089031c2..4a4e96387 100644 --- a/src/mmu/tlb/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 9405cfdb9..4be12e383 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index bc8768f47..722449284 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -11,6 +11,7 @@ // MHPMEVENT is not supported // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index ea7bf7afb..fafc5c845 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -73,11 +74,11 @@ module csri import cvw::*; #(parameter cvw_t P) ( assign SIP_WRITE_MASK = 12'h000; assign MIE_WRITE_MASK = 12'h888; end - always @(posedge clk) + always_ff @(posedge clk) if (reset) MIP_REGW_writeable <= 12'b0; else if (WriteMIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK); else if (WriteSIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK) | (MIP_REGW_writeable & ~SIP_WRITE_MASK); - always @(posedge clk) + always_ff @(posedge clk) if (reset) MIE_REGW <= 12'b0; else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222 & MIDELEG_REGW) | (MIE_REGW & 12'h888); // only S fields diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 056e8f2f9..35c27736c 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -162,7 +163,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); if (P.U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); - end else assign MCOUNTEREN_REGW = '0; + end else assign MCOUNTEREN_REGW = 0; // MENVCFG register if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control @@ -198,7 +199,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( // verilator lint_off WIDTH logic [5:0] entry; always_comb begin - entry = '0; + entry = 0; CSRMReadValM = 0; IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index e107fc0f7..2357fc131 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 9935da179..733b2f0c6 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -65,7 +66,7 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE, /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0}; - assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. + assign MSTATUSH_REGW = 0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. end else begin: csrsr32 // RV32 assign MSTATUS_REGW = {STATUS_SD, 8'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index 3a0f8c909..37891d009 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index a5bfde1cf..cf32c1f28 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -79,8 +80,8 @@ module privdec import cvw::*; #(parameter cvw_t P) ( if (P.U_SUPPORTED) begin:wfi logic [P.WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; - assign WFICountPlus1 = WFICount + 1; - floprc #(P.WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI + assign WFICountPlus1 = wfiM ? WFICount + 1 : '0; // restart counting on WFI + flopr #(P.WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, WFICountPlus1, WFICount); // count while in WFI // coverage off -item e 1 -fecexprrow 1 // WFI Timout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout. assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != P.M_MODE) | (P.S_SUPPORTED & PrivilegeModeW == P.U_MODE)) & WFICount[P.WFI_TIMEOUT_BIT]; diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 063504730..09a56259f 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privmode.sv b/src/privileged/privmode.sv index 5ac4cae78..f1c5bfd76 100644 --- a/src/privileged/privmode.sv +++ b/src/privileged/privmode.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv index 5dea45972..ed43571bd 100644 --- a/src/privileged/privpiperegs.sv +++ b/src/privileged/privpiperegs.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index 43ff8eadc..db31afa69 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -64,8 +65,8 @@ module trap import cvw::*; #(parameter cvw_t P) ( assign PendingIntsM = MIP_REGW & MIE_REGW; assign IntPendingM = |PendingIntsM; assign Committed = CommittedM | CommittedF; - assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); - assign ValidIntsM = {12{~Committed}} & EnabledIntsM; + assign EnabledIntsM = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : 0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : 0); + assign ValidIntsM = Committed ? 0 : EnabledIntsM; assign InterruptM = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage. // wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage. assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index 454f4d5df..dc7ceeab3 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -8,6 +8,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 6e35ffdaf..961a50824 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -62,7 +63,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( // register access if (P.XLEN==64) begin:clint // 64-bit - always @(posedge PCLK) begin + always_ff @(posedge PCLK) begin case(entry) 16'h0000: PRDATA <= {63'b0, MSIP}; 16'h4000: PRDATA <= MTIMECMP; @@ -96,7 +97,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( MTIME[j*8 +: 8] <= PWDATA[j*8 +: 8]; end else MTIME <= MTIME + 1; end else begin:clint // 32-bit - always @(posedge PCLK) begin + always_ff @(posedge PCLK) begin case(entry) 16'h0000: PRDATA <= {31'b0, MSIP}; 16'h4000: PRDATA <= MTIMECMP[31:0]; diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv index 4ba3e1ccf..3b4ae1cb0 100644 --- a/src/uncore/gpio_apb.sv +++ b/src/uncore/gpio_apb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 8ced27319..7858b2e35 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -90,7 +91,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( assign memread = ~PWRITE & PSEL; // read at start of access phase. PENABLE hasn't set up before this assign PREADY = 1'b1; // PLIC never takes >1 cycle to respond assign entry = {PADDR[23:2],2'b0}; - assign One[P.PLIC_NUM_SRC-1:1] = '0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment. + assign One[P.PLIC_NUM_SRC-1:1] = 0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment. // account for subword read/write circuitry // -- Note PLIC registers are 32 bits no matter what; access them with LW SW. @@ -103,13 +104,13 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // ================== localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 31; - always @(posedge PCLK) begin + always_ff @(posedge PCLK) begin // resetting if (~PRESETn) begin - intPriority <= #1 '0; - intEn <= #1 '0; - intThreshold <= #1 '0; - intInProgress <= #1 '0; + intPriority <= #1 0; + intEn <= #1 0; + intThreshold <= #1 0; + intInProgress <= #1 0; // writing end else begin if (memwrite) diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 896c2a4cb..98bdfcb09 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -26,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define RAM_LATENCY 0 - module ram_ahb import cvw::*; #(parameter cvw_t P, parameter BASE=0, RANGE = 65535, PRELOAD = 0) ( input logic HCLK, HRESETn, @@ -75,7 +74,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); // use this to add arbitrary latency to ram. Helps test AHB controller correctness - if(`RAM_LATENCY > 0) begin + if(P.RAM_LATENCY > 0) begin logic [7:0] NextCycle, Cycle; logic CntEn, CntRst; logic CycleFlag; @@ -100,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, endcase end - assign CycleFlag = Cycle == `RAM_LATENCY; + assign CycleFlag = Cycle == P.RAM_LATENCY[7:0]; assign CntEn = NextState == DELAY; assign DelayReady = NextState == DELAY; assign CntRst = NextState == READY; diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv index d94cd6e07..9576f33d7 100644 --- a/src/uncore/rom_ahb.sv +++ b/src/uncore/rom_ahb.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index ad1e0f259..555a7682c 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -16,6 +16,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -519,7 +520,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( intrpending = 0; end end - always @(posedge PCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin + always_ff @(posedge PCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin // Side effect of reading LSR is lowering overrun, parity, framing, break intr's assign setSquashRXerrIP = ~MEMRb & (A==3'b101); diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv index 6fab04189..eeecb7ea5 100644 --- a/src/uncore/uart_apb.sv +++ b/src/uncore/uart_apb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 1675d5a38..22e0a35fc 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 9f84cc7bf..440307806 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design (Figure 4.1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -252,7 +253,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .LSUStallM); if(P.BUS_SUPPORTED) begin : ebu - ebu #(P.XLEN, P.PA_BITS, P.AHBW) ebu(// IFU connections + ebu #(P) ebu(// IFU connections .clk, .reset, // IFU interface .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE, diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index ab0071fff..d82a5c0d4 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design (Figure 6.20) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/studies/comparator.sv b/studies/comparator.sv index a5dbb6cb6..01d38181b 100644 --- a/studies/comparator.sv +++ b/studies/comparator.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/synthDC/Makefile b/synthDC/Makefile index 7968a7b52..03c3c6612 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -51,7 +51,8 @@ configs: $(CONFIG) $(CONFIG): @echo $(CONFIG) cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR) - cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR) +# cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR) + cp -r $(OLDCONFIGDIR)/deriv/$(CONFIG)/* $(CONFIGDIR) # adjust DTIM and IROM to reasonable values depending on config ifneq ($(filter $(CONFIG), $(DIRS32)),) @@ -61,8 +62,8 @@ else ifneq ($(filter $(CONFIG), $(DIRS64)),) sed -i "s/DTIM_RANGE.*/DTIM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh sed -i "s/IROM_RANGE.*/IROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh else - $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) - @echo "Config not in list, RAM_RANGE will be unmodified" + $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) + @echo "Config not in list, RAM_RANGE will be unmodified" endif # if USESRAM = 1, set that in the config file, otherwise reduce sizes diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl index 5f595dad8..fa630a3e7 100755 --- a/synthDC/extractArea.pl +++ b/synthDC/extractArea.pl @@ -10,6 +10,7 @@ ## Purpose: Pull area statistics from run directory ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 1b2402bee..c08b1d767 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -136,7 +136,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r"); // read line by line to count lines - if (ProgramAddrMapFP != '0) begin + if (ProgramAddrMapFP != 0) begin while (! $feof(ProgramAddrMapFP)) begin status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine); ProgramAddrMapMemory[ProgramAddrMapLineCount] = ProgramAddrMapLine; @@ -154,7 +154,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( ProgramLabelMapLineCount = 0; ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r"); - if (ProgramLabelMapFP != '0) begin + if (ProgramLabelMapFP != 0) begin while (! $feof(ProgramLabelMapFP)) begin status = $fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine); ProgramLabelMapMemory[ProgramLabelMapLineCount] = ProgramLabelMapLine; @@ -174,7 +174,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( logic OrReducedAdr, AnyUnknown; assign OrReducedAdr = |ProgramAddrIndex; assign AnyUnknown = (OrReducedAdr === 1'bx) ? 1'b1 : 1'b0; - initial ProgramAddrIndex = '0; + initial ProgramAddrIndex = 0; always @(*) FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex]; diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index dcbe7e32a..b439b3d75 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -21,53 +21,51 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); initial begin - assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); - assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); - assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); - assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); - assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); - assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); - assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); - assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); - assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); - assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); - assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); + assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); + assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "Virtual memory requires S mode support"); + assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); + assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)"); + assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)"); + assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)"); + assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB/DTIM bus width is XLEN"); + assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported"); + assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size"); + assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size"); + assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "DTLB_ENTRIES must be a power of 2"); assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF"); - assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); + assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $fatal(1, "PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); + assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $fatal(1, "S and U modes not supported if ZICSR not supported"); assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); - assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); - assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); - assert (P.DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally."); - assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); - assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); - assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); - assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED"); - assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); - assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOM requires DCACHE_SUPPORTED"); - assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOZ requires DCACHE_SUPPORTED"); - assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP requires DCACHE_SUPPORTED"); - assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVPBMT requires VIRTMEM_SUPPORTED and RV64"); - assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVNAPOT requires VIRTMEM_SUPPORTED and RV64"); - assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $error("ZCB requires M and ZBB (and also ZBA for RV64)"); - assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $error("C and ZCA/ZCD/ZCF cannot simultaneously be supported"); - assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $error("ZCF or ZCD requires ZCA"); - assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $error("ZCF requires F"); - assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $error("ZCD requires D"); + assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $fatal(1, "Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); + assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs dcache"); + assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs icache"); + assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED."); + assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16"); + assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); + assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally."); + assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED"); + assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED"); + assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $fatal(1, "At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); + assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $fatal(1, "ZICNTR_SUPPORTED requires ZICSR_SUPPORTED"); + assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); + assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED"); + assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED"); + assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64"); + assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64"); + assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $fatal(1, "ZCB requires M and ZBB (and also ZBA for RV64)"); + assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $fatal(1, "C and ZCA/ZCD/ZCF cannot simultaneously be supported"); + assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA"); + assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F"); + assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D"); end endmodule diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 746fde068..554ebc5d7 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -63,7 +63,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic CSRWriteM, CSRWriteW; logic [11:0] CSRAdrM, CSRAdrW; logic wfiM; - logic InterruptM; + logic InterruptM, InterruptW; assign clk = testbench.dut.clk; // assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet @@ -231,7 +231,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end genvar index; - assign rf[0] = '0; + assign rf[0] = 0; for(index = 1; index < NUMREGS; index += 1) assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index]; @@ -239,7 +239,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3; always_comb begin - rf_wb <= '0; + rf_wb <= 0; if(rf_we3) rf_wb[rf_a3] <= 1'b1; end @@ -251,7 +251,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4; always_comb begin - frf_wb <= '0; + frf_wb <= 0; if(frf_we4) frf_wb[frf_a4] <= 1'b1; end @@ -266,6 +266,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW); flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW); flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW); + flopenrc #(1) InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW); flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW); // **** remove? are these used? @@ -287,9 +288,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order assign rvvi.insn[0][0] = InstrRawW; assign rvvi.pc_rdata[0][0] = PCW; - assign rvvi.trap[0][0] = 0; + assign rvvi.trap[0][0] = TrapW; assign rvvi.halt[0][0] = HaltW; - assign rvvi.intr[0][0] = 0; + assign rvvi.intr[0][0] = InterruptW; assign rvvi.mode[0][0] = PrivilegeModeW; assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 : PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL; @@ -492,7 +493,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end // *** implementation only cancel? so sc does not clear? - assign rvvi.lrsc_cancel[0][0] = '0; + assign rvvi.lrsc_cancel[0][0] = 0; integer index2; diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv index 1e2b760ca..296900b20 100644 --- a/testbench/common/watchdog.sv +++ b/testbench/common/watchdog.sv @@ -40,7 +40,7 @@ module watchdog #(parameter XLEN, WatchDogTimerThreshold) always_ff @(posedge clk) begin OldPCW <= PCW; if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1; - else WatchDogTimerCount = '0; + else WatchDogTimerCount = 0; end always_comb begin diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index b19542d62..5eab7c7ec 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -35,6 +35,8 @@ module testbenchfp; `include "parameter-defs.vh" + parameter MAXVECTORS = 8388610; + // FIXME: needs cleaning of unused variables (jes) string Tests[]; // list of tests to be run logic [2:0] OpCtrl[]; // list of op controls @@ -49,7 +51,7 @@ module testbenchfp; logic [31:0] errors=0; // how many errors logic [31:0] VectorNum=0; // index for test vector logic [31:0] FrmNum=0; // index for rounding mode - logic [P.FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors + logic [P.FLEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors logic [1:0] FmtVal; // value of the current Fmt logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal @@ -83,7 +85,7 @@ module testbenchfp; logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by logic [P.DIVb:0] Quot; logic CvtResSubnormUfE; - logic DivStart; + logic DivStart=0; logic FDivBusyE; logic OldFDivBusyE; logic reset = 1'b0; @@ -120,7 +122,11 @@ module testbenchfp; logic ResMatch; // Check if result match logic FlagMatch; // Check if IEEE flags match logic CheckNow; // Final check - logic FMAop; // Is this a FMA operation? + logic FMAop; // Is this a FMA operation? + + // FSM for testing each item per clock + typedef enum logic [2:0] {S0, Start, S2, Done} statetype; + statetype state, nextstate; /////////////////////////////////////////////////////////////////////////////////////////////// @@ -676,7 +682,7 @@ module testbenchfp; .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, .Xs, .Ys, .Zs, .Unit(UnitVal), .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal), - .Xm, .Ym, .Zm, .DivStart, + .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, .XSubnorm, .ZSubnorm, @@ -748,16 +754,6 @@ module testbenchfp; clk = 1; #5; clk = 0; #5; end - // Provide reset for divsqrt to reset state to IDLE - // Previous version did not initiate a divide due to missing state - // information. This starts the FSM by putting the fdivsqrt into - // the IDLE state. - initial - begin - #0 reset = 1'b1; - #25 reset = 1'b0; - end - /////////////////////////////////////////////////////////////////////////////////////////////// // ||||| ||| |||||||||| ||||| ||| @@ -835,45 +831,64 @@ module testbenchfp; `CMPUNIT: ResFlg = CmpFlg; `CVTINTUNIT: ResFlg = Flg; `CVTFPUNIT: ResFlg = Flg; - endcase - end + endcase + // Use four state test sequence to handle div properly. + // Four states should allow other operations to finish + // properly and within time. + case (state) + S0: begin + DivStart = 1'b0; + nextstate = Start; + end + Start: begin + if (UnitVal == `DIVUNIT) + DivStart = 1'b1; + else + DivStart = 1'b0; + nextstate = S2; + end + S2: begin + DivStart = 1'b0; + if ((FDivBusyE|~DivDone)&(UnitVal == `DIVUNIT)) + nextstate = S2; + else + nextstate = Done; + end + Done: begin + DivStart = 1'b0; + nextstate = S0; + end + endcase // case (state) + + end + + // Provide reset for divsqrt to reset state + initial + begin + #0 reset = 1'b1; + #25 reset = 1'b0; + end + + // Left-over from before - will remove soon always @(posedge clk) OldFDivBusyE = FDivDoneE; - // For FP division this adds extra clock cycles to make sure the - // computation completes. + // state machine to handle timing for testing due + // various cycle counts for different fp/int operations + // Adds vector at start of clock always @(posedge clk) begin - // Add extra clock cycles in beginning for fdivsqrt to adequate reset state - if (~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin - // This allows specific number of clocks to allow each vector - // to complete for division or square root. It is an - // arbitrary value and can be changed, if needed. - case (FmtVal) - // QP - 2'b11: begin - repeat (20) - @(posedge clk); - end - // HP - 2'b10: begin - repeat (14) - @(posedge clk); - end - // DP - 2'b01: begin - repeat (18) - @(posedge clk); - end - // SP - 2'b00: begin - repeat (16) - @(posedge clk); - end - endcase // case (FmtVal) - if (reset != 1'b1) - VectorNum += 1; // increment the vector - end + + // state machine element for testing + if (reset) + state <= S0; + else + state <= nextstate; + + // Increment the vector when Done with each test + if (state == Done) + VectorNum += 1; // increment the vector + end // check results on falling edge of clk @@ -904,7 +919,7 @@ module testbenchfp; (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) | (ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]}))); endcase - else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format + else if (UnitVal === `CVTFPUNIT) // if converting from FP to FP OpCtrl contains the final FP format case (OpCtrlVal[1:0]) 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | @@ -941,35 +956,28 @@ module testbenchfp; /////////////////////////////////////////////////////////////////////////////////////////////// // check if result is correct - // wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); assign FMAop = (OpCtrlVal == `FMAUNIT); assign DivDone = OldFDivBusyE & ~FDivBusyE; - - // Maybe change OpCtrl but for now just look at TEST for fma test - assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); - if (~(ResMatch & FlagMatch) & CheckNow) begin + assign CheckNow = ((DivDone | ~divsqrtop) | + (TEST == "add" | TEST == "fma" | TEST == "sub") | + ((TEST == "all") & (DivDone | ~divsqrtop))); + + if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin errors += 1; $display("\nError in %s", Tests[TestNum]); $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; - end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & - ~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons - errors += 1; - $display("\nError in %s", Tests[TestNum]); - $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); - $stop; end if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof // increment the test TestNum += 1; // clear the vectors - for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}}; + for(int i=0; i> 32; - rvviRefMemoryWrite(0, index+0, x32[0], 4); - rvviRefMemoryWrite(0, index+4, x32[1], 4); - //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); - end - $fclose(memFile); - - $display("RVVI Loading ram.bin"); - memFile = $fopen({testvectorDir,"ram.bin"}, "rb"); - index = 'h80000000 - 8; - while(!$feof(memFile)) begin - index+=8; - readResult = $fread(x64, memFile); - if (x64 == 0) continue; - x32[0] = x64 & 'hffffffff; - x32[1] = x64 >> 32; - rvviRefMemoryWrite(0, index+0, x32[0], 4); - rvviRefMemoryWrite(0, index+4, x32[1], 4); - //$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); - end - $fclose(memFile); - - $display("RVVI Loading Complete"); - - void'(rvviRefPcSet(0, 'h1000)); // set BOOTROM address - end - end - - always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1])); - always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5])); - - final begin - void'(rvviRefShutdown()); - end - - `endif - - - // Wally - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); - - // W-stage hardware not needed by Wally itself - parameter nop = 'h13; - logic [P.XLEN-1:0] PCW; - logic [31:0] InstrW; - logic InstrValidW; - logic [P.XLEN-1:0] IEUAdrW, WriteDataW; - logic TrapW; - `define FLUSHW dut.core.FlushW - `define STALLW dut.core.StallW - flopenrc #(P.XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW); - flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : InstrM, InstrW); - flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW); - flopenrc #(P.XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); - flopenrc #(P.XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); - flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW); - - - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////// INITIALIZATION //////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // ========== CHECKPOINTING ========== - `define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ - initial begin \ - #1; \ - if (CHECKPOINT!=0) $readmemh({checkpointDir,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \ - end - - `define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - initial begin \ - if (CHECKPOINT!=0) begin \ - force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ - while (reset!==1) #1; \ - while (reset!==0) #1; \ - #1; \ - release `SIGNAL; \ - end \ - end - - `define INIT_CHECKPOINT_PACKED_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - for (i=ARRAY_MIN; i= 2)) fault = 1; \ - end - - `define checkCSR(CSR) \ - begin \ - if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ - $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ - if(`DEBUG_TRACE >= 3) fault = 1; \ - end \ - end - - // =========== CORE =========== - assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM; - always @(negedge clk) begin - `SCAN_NEW_INSTR_FROM_TRACE(E) - `SCAN_NEW_INSTR_FROM_TRACE(M) - end - - // step 1: register expected state into the write back stage. - always @(posedge clk) begin - if (reset) begin - ExpectedPCW <= '0; - ExpectedInstrW <= '0; - textW <= ""; - RegWriteW <= ""; - ExpectedRegAdrW <= '0; - ExpectedRegValueW <= '0; - ExpectedIEUAdrW <= '0; - MemOpW <= ""; - ExpectedMemWriteDataW <= '0; - ExpectedMemReadDataW <= '0; - NumCSRW <= '0; - end else if(~dut.core.StallW) begin - if(dut.core.FlushW) begin - ExpectedPCW <= '0; - ExpectedInstrW <= '0; - textW <= ""; - RegWriteW <= ""; - ExpectedRegAdrW <= '0; - ExpectedRegValueW <= '0; - ExpectedIEUAdrW <= '0; - MemOpW <= ""; - ExpectedMemWriteDataW <= '0; - ExpectedMemReadDataW <= '0; - NumCSRW <= '0; - end else if (dut.core.ieu.c.InstrValidM) begin - ExpectedPCW <= ExpectedPCM; - ExpectedInstrW <= ExpectedInstrM; - textW <= textM; - RegWriteW <= RegWriteM; - ExpectedRegAdrW <= ExpectedRegAdrM; - ExpectedRegValueW <= ExpectedRegValueM; - ExpectedIEUAdrW <= ExpectedIEUAdrM; - MemOpW <= MemOpM; - ExpectedMemWriteDataW <= ExpectedMemWriteDataM; - ExpectedMemReadDataW <= ExpectedMemReadDataM; - NumCSRW <= NumCSRM; - for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin - ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex]; - ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex]; - end - end - #1; - // override on special conditions - if(~dut.core.StallW) begin - if(textW.substr(0,5) == "rdtime") begin - //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); - if(!NO_SPOOFING) - release dut.uncore.uncore.clint.clint.MTIME; - end - //if (ExpectedIEUAdrM == 'h10000005) begin - //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount); - //release dut.core.ieu.dp.ReadDataM; - //end - end - end - end - - // step2: make all checks in the write back stage. - assign checkInstrW = InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. - always @(negedge clk) begin - #1; // small delay allows interrupt spoofing to happen first - // always check PC, instruction bits - if (checkInstrW) begin - InstrCountW += 1; - // print progress message - if (AttemptedInstructionCount % 'd100000 == 0) $display("Reached %d instructions", AttemptedInstructionCount); - // turn on waves - if (AttemptedInstructionCount == INSTR_WAVEON) $stop; - // end sim - if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end - fault = 0; - if (`DEBUG_TRACE >= 1) begin - `checkEQ("PCW",PCW,ExpectedPCW) - //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of - // compressed to uncompressed conversion - `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW) - #2; // delay 2 ns. - if(`DEBUG_TRACE >= 5) begin - $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); - $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); - end - if (RegWriteW == "GPR") begin - `checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW) - $sformat(name,"RF[%02d]",ExpectedRegAdrW); - `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW) - end - if (MemOpW.substr(0,2) == "Mem") begin - if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); - `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) - if(MemOpW == "MemR" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); - `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) - end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); - `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) - end - end - // check csr - for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin - case(ExpectedCSRArrayW[NumCSRPostWIndex]) - "mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW) - "mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW) - "sstatus": `checkCSR(`CSR_BASE.csrs.csrs.SSTATUS_REGW) - "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) - "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) - "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) - "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) - "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) - "mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW) - "menvcfg": `checkCSR(`CSR_BASE.csrm.MENVCFG_REGW) - "sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW) - "scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW) - "stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW) - "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) - // "senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW) // *** fix me - "mip": begin - `checkCSR(`CSR_BASE.csrm.MIP_REGW) - if(!NO_SPOOFING) begin - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0) - force `MEIP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0) - force `SEIP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & ((1<<11) | (1<<09))) == 0) - force `UART_IP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<07) == 0) - force `MTIP = 0; - end - end - endcase - end - if (fault == 1) begin - errorCount +=1; - $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); - $stop; $stop; - end - end // if (`DEBUG_TRACE >= 1) - end // if (checkInstrW) - end // always @ (negedge clk) - - - // New IP spoofing - logic globalIntsBecomeEnabled; - assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); - logic checkInterruptM; - assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM; - - always @(negedge clk) begin - if(checkInterruptM) begin - if((interruptInstrCount+1) == AttemptedInstructionCount) begin - if(!NO_SPOOFING) begin - case (interruptCauseVal) - 11: begin - force `MEIP = 1; - force `UART_IP = 1; - end - 09: begin - force `SEIP = 1; - force `UART_IP = 1; - end - 07: force `MTIP = 1; - default: $display("Unsupported interrupt in interrupts.txt. cause = %0d",interruptCauseVal); - endcase - $display("Forcing interrupt."); - end - `SCAN_NEW_INTERRUPT - if (globalIntsBecomeEnabled) begin - $display("Enabled global interrupts"); - // The idea here is if a CSR instruction causes an interrupt by - // enabling interrupts, that CSR instruction will commit. - end else begin - // Other instructions, however, will get interrupted and not - // commit, so we don't want our W-stage checker to look for them - // and get confused when it doesn't find them. - garbageInt = $fgets(garbageString,traceFileE); - garbageInt = $fgets(garbageString,traceFileM); - AttemptedInstructionCount += 1; - end - end - end - end - - - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - //////////////////////////////// Extra Features /////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Function Tracking - FunctionName #(P) FunctionName(.reset(reset), - .clk(clk), - .ProgramAddrMapFile(ProgramAddrMapFile), - .ProgramLabelMapFile(ProgramLabelMapFile)); - - // Instr Opcode Tracking - // For waveview convenience - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.InstrRawF[31:0], - dut.core.ifu.InstrD, dut.core.ifu.InstrE, - InstrM, InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - - // ------------------ - // Address Translator - // ------------------ - /** - * Walk the page table stored in ram according to sv39 logic and translate a - * virtual address to a physical address. - * - * See section 4.3.2 of the RISC-V Privileged specification for a full - * explanation of the below algorithm. - */ - logic SvMode, PTE_R, PTE_X; - logic [P.XLEN-1:0] SATP, PTE; - logic [55:0] BaseAdr, PAdr; - logic [8:0] VPN [2:0]; - logic [11:0] Offset; - function logic [P.XLEN-1:0] adrTranslator( - input logic [P.XLEN-1:0] adrIn); - begin - int i; - // Grab the SATP register from privileged unit - SATP = dut.core.priv.priv.csr.SATP_REGW; - // Split the virtual address into page number segments and offset - VPN[2] = adrIn[38:30]; - VPN[1] = adrIn[29:21]; - VPN[0] = adrIn[20:12]; - Offset = adrIn[11:0]; - // We do not support sv48; only sv39 - SvMode = SATP[63]; - // Only perform translation if translation is on and the processor is not - // in machine mode - if (SvMode & (dut.core.priv.priv.PrivilegeModeW != P.M_MODE)) begin - BaseAdr = SATP[43:0] << 12; - for (i = 2; i >= 0; i--) begin - PAdr = BaseAdr + (VPN[i] << 3); - // ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift - // by 3 (the PTE size) to get the requested 64-bit PTE. - PTE = dut.uncore.uncore.ram.ram.memory.RAM[PAdr >> 3]; - PTE_R = PTE[1]; - PTE_X = PTE[3]; - if (PTE_R | PTE_X) begin - // Leaf page found - break; - end else begin - // Go to next level of table - BaseAdr = PTE[53:10] << 12; - end - end - // Determine which parts of the PTE page number to use based on the - // level of the page table we reached. - if (i == 2) begin - // Gigapage - assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset}; - end else if (i == 1) begin - // Megapage - assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset}; - end else begin - // Kilopage - assign adrTranslator = {8'b0, PTE[53:10], Offset}; - end - end else begin - // Direct translation if address translation is not on - assign adrTranslator = adrIn; - end - end - endfunction -endmodule diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv deleted file mode 100644 index 011c4d148..000000000 --- a/testbench/testbench-linux.sv +++ /dev/null @@ -1,870 +0,0 @@ -/////////////////////////////////////////// -// testbench-linux.sv -// -// Written: nboorstin@g.hmc.edu 2021 -// Modified: -// -// Purpose: Testbench for Buildroot Linux -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "config.vh" -import cvw::*; - -`define DEBUG_TRACE 0 -// Debug Levels -// 0: don't check against QEMU -// 1: print disagreements with QEMU, but only halt on PCW disagreements -// 2: halt on any disagreement with QEMU except CSRs -// 3: halt on all disagreements with QEMU -// 4: print memory accesses whenever they happen -// 5: print everything - -module testbench; - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////////// CONFIG //////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Recommend setting all of these in 'do' script using -G option - parameter INSTR_LIMIT = 0; // # of instructions at which to stop - parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim - parameter CHECKPOINT = 0; - parameter RISCV_DIR = "/opt/riscv"; - parameter NO_SPOOFING = 0; - - -`include "parameter-defs.vh" - - - //////////////////////////////////////////////////////////////////////////////////// - //////////////////////// SIGNAL / VAR / MACRO DECLARATIONS ///////////////////////// - //////////////////////////////////////////////////////////////////////////////////// - // ========== Testbench Core ========== - integer warningCount = 0; - integer errorCount = 0; - integer fault; - string ProgramAddrMapFile, ProgramLabelMapFile; - // ========== Initialization ========== - string testvectorDir; - string linuxImageDir; - integer memFile; - integer readResult; - // ========== Checkpointing ========== - string checkpointDir; - logic [1:0] initPriv; - // ========== Trace parsing & checking ========== - integer garbageInt; - string garbageString; - `define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \ - integer traceFile``STAGE; \ - integer matchCount``STAGE; \ - string line``STAGE; \ - string token``STAGE; \ - string ExpectedTokens``STAGE [31:0]; \ - integer index``STAGE; \ - integer StartIndex``STAGE, EndIndex``STAGE; \ - integer TokenIndex``STAGE; \ - integer MarkerIndex``STAGE; \ - integer NumCSR``STAGE; \ - logic [P.XLEN-1:0] ExpectedPC``STAGE; \ - logic [31:0] ExpectedInstr``STAGE; \ - string text``STAGE; \ - string MemOp``STAGE; \ - string RegWrite``STAGE; \ - integer ExpectedRegAdr``STAGE; \ - logic [P.XLEN-1:0] ExpectedRegValue``STAGE; \ - logic [P.XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ - string ExpectedCSRArray``STAGE[10:0]; \ - logic [P.XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? - `DECLARE_TRACE_SCANNER_SIGNALS(E) - `DECLARE_TRACE_SCANNER_SIGNALS(M) - // M-stage expected values - logic checkInstrM; - integer MIPexpected, SIPexpected; - string name; - logic [P.AHBW-1:0] readDataExpected; - // W-stage expected values - logic checkInstrW; - logic [P.XLEN-1:0] ExpectedPCW; - logic [31:0] ExpectedInstrW; - string textW; - string RegWriteW; - integer ExpectedRegAdrW; - logic [P.XLEN-1:0] ExpectedRegValueW; - string MemOpW; - logic [P.XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW; - integer NumCSRW; - string ExpectedCSRArrayW[10:0]; - logic [P.XLEN-1:0] ExpectedCSRArrayValueW[10:0]; - logic [P.XLEN-1:0] ExpectedIntType; - integer NumCSRWIndex; - integer NumCSRPostWIndex; - logic [P.XLEN-1:0] InstrCountW; - // ========== Interrupt parsing & spoofing ========== - string interrupt; - string interruptLine; - integer interruptFile; - integer interruptInstrCount; - integer interruptHartVal; - integer interruptAsyncVal; - longint interruptCauseVal; - longint interruptEpcVal; - longint interruptTVal; - string interruptDesc; - integer NextMIPexpected, NextSIPexpected; - integer NextMepcExpected; - logic [P.XLEN-1:0] AttemptedInstructionCount; - // ========== Misc Aliases ========== - `define RF dut.core.ieu.dp.regf.rf - `define PC dut.core.ifu.pcreg.q - `define PRIV_BASE dut.core.priv.priv - `define PRIV `PRIV_BASE.privmode.privmode.privmodereg.q - `define CSR_BASE `PRIV_BASE.csr - `define MEIP `PRIV_BASE.MExtInt - `define SEIP `PRIV_BASE.SExtInt - `define MTIP `PRIV_BASE.MTimerInt - `define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW - `define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q - `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q - `define MIE `CSR_BASE.csri.MIE_REGW - `define MIP `CSR_BASE.csri.MIP_REGW_writeable - `define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q - `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q - `define MEPC `CSR_BASE.csrm.MEPCreg.q - `define SEPC `CSR_BASE.csrs.csrs.SEPCreg.q - `define MCOUNTEREN `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q - `define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q - `define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q - `define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q - `define MTVEC `CSR_BASE.csrm.MTVECreg.q - `define STVEC `CSR_BASE.csrs.csrs.STVECreg.q - `define SATP `CSR_BASE.csrs.csrs.genblk2.SATPreg.q - `define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2] - `define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW - `define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW - `define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT - `define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT - `define STATUS_TVM `CSR_BASE.csrsr.STATUS_TVM_INT - `define STATUS_MXR `CSR_BASE.csrsr.STATUS_MXR_INT - `define STATUS_SUM `CSR_BASE.csrsr.STATUS_SUM_INT - `define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT - `define STATUS_FS `CSR_BASE.csrsr.STATUS_FS_INT - `define STATUS_MPP `CSR_BASE.csrsr.STATUS_MPP - `define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP - `define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE - `define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE - `define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE - `define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE - `define UART dut.uncore.uncore.uart.uart.u - `define UART_IER `UART.IER - `define UART_LCR `UART.LCR - `define UART_MCR `UART.MCR - `define UART_SCR `UART.SCR - `define UART_IP `UART.INTR - `define PLIC dut.uncore.uncore.plic.plic - `define PLIC_INT_PRIORITY `PLIC.intPriority - `define PLIC_INT_ENABLE `PLIC.intEn - `define PLIC_THRESHOLD `PLIC.intThreshold - `define PCM dut.core.ifu.PCM - // ========== COMMON MACROS ========== - // Needed for initialization and core - `define SCAN_NEW_INTERRUPT \ - begin \ - $fgets(interruptLine, interruptFile); \ - //$display("Time %t, interruptLine %x", $time, interruptLine); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%d", interruptInstrCount); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%d", interruptHartVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%d", interruptAsyncVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%x", interruptCauseVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%x", interruptEpcVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%x", interruptTVal); \ - $fgets(interruptLine, interruptFile); \ - $sscanf(interruptLine, "%s", interruptDesc); \ - end - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////// Cache Issue /////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - - // Duplicate copy of pipeline registers that are optimized out of some configurations - logic [31:0] NextInstrE, InstrM; - mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE); - flopenr #(32) InstrMReg(dut.core.clk, dut.core.reset, ~dut.core.ifu.StallM, NextInstrE, InstrM); - - logic probe; - if (NO_SPOOFING) - assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c - & InstrM != 32'h14021273 - & testbench.dut.core.InstrValidM; - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - ////////////////////////////////// HARDWARE /////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Clock and Reset - logic clk, reset_ext; - logic reset; - initial begin reset_ext <= 1; # 22; reset_ext <= 0; end - always begin clk <= 1; # 5; clk <= 0; # 5; end - // Wally Interface - logic [P.AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; - logic HCLK, HRESETn; - logic HREADY; - logic HSELEXT; - logic HSELEXTSDC; - logic [P.PA_BITS-1:0] HADDR; - logic [P.AHBW-1:0] HWDATA; - logic [P.XLEN/8-1:0] HWSTRB; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic [31:0] GPIOIN; - logic [31:0] GPIOOUT, GPIOEN; - logic UARTSin, UARTSout; - logic SPIIn, SPIOut; - logic [3:0] SPICS; - - // FPGA-specific Stuff - logic SDCIntr; - - // Hardwire UART, GPIO pins - assign GPIOIN = 0; - assign UARTSin = 1; - assign SDCIntr = 0; - - // Wally - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn); - - // W-stage hardware not needed by Wally itself - parameter nop = 'h13; - logic [P.XLEN-1:0] PCW; - logic [31:0] InstrW; - logic InstrValidW; - logic [P.XLEN-1:0] IEUAdrW, WriteDataW; - logic TrapW; - `define FLUSHW dut.core.FlushW - `define STALLW dut.core.StallW - flopenrc #(P.XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW); - flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : InstrM, InstrW); - flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW); - flopenrc #(P.XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); - flopenrc #(P.XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); - flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW); - - - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - /////////////////////////////// INITIALIZATION //////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // ========== CHECKPOINTING ========== - `define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ - initial begin \ - #1; \ - if (CHECKPOINT!=0) $readmemh({checkpointDir,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \ - end - - `define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - initial begin \ - if (CHECKPOINT!=0) begin \ - force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ - while (reset!==1) #1; \ - while (reset!==0) #1; \ - #1; \ - release `SIGNAL; \ - end \ - end - - `define INIT_CHECKPOINT_PACKED_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ - for (i=ARRAY_MIN; i= 2)) fault = 1; \ - end - - `define checkCSR(CSR) \ - begin \ - if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ - $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ - if(`DEBUG_TRACE >= 3) fault = 1; \ - end \ - end - - // =========== CORE =========== - assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM; - always @(negedge clk) begin - `SCAN_NEW_INSTR_FROM_TRACE(E) - `SCAN_NEW_INSTR_FROM_TRACE(M) - end - - // step 1: register expected state into the write back stage. - always @(posedge clk) begin - if (reset) begin - ExpectedPCW <= '0; - ExpectedInstrW <= '0; - textW <= ""; - RegWriteW <= ""; - ExpectedRegAdrW <= '0; - ExpectedRegValueW <= '0; - ExpectedIEUAdrW <= '0; - MemOpW <= ""; - ExpectedMemWriteDataW <= '0; - ExpectedMemReadDataW <= '0; - NumCSRW <= '0; - end else if(~dut.core.StallW) begin - if(dut.core.FlushW) begin - ExpectedPCW <= '0; - ExpectedInstrW <= '0; - textW <= ""; - RegWriteW <= ""; - ExpectedRegAdrW <= '0; - ExpectedRegValueW <= '0; - ExpectedIEUAdrW <= '0; - MemOpW <= ""; - ExpectedMemWriteDataW <= '0; - ExpectedMemReadDataW <= '0; - NumCSRW <= '0; - end else if (dut.core.ieu.c.InstrValidM) begin - ExpectedPCW <= ExpectedPCM; - ExpectedInstrW <= ExpectedInstrM; - textW <= textM; - RegWriteW <= RegWriteM; - ExpectedRegAdrW <= ExpectedRegAdrM; - ExpectedRegValueW <= ExpectedRegValueM; - ExpectedIEUAdrW <= ExpectedIEUAdrM; - MemOpW <= MemOpM; - ExpectedMemWriteDataW <= ExpectedMemWriteDataM; - ExpectedMemReadDataW <= ExpectedMemReadDataM; - NumCSRW <= NumCSRM; - for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin - ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex]; - ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex]; - end - end - #1; - // override on special conditions - if(~dut.core.StallW) begin - if(textW.substr(0,5) == "rdtime") begin - //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); - if(!NO_SPOOFING) - release dut.uncore.uncore.clint.clint.MTIME; - end - //if (ExpectedIEUAdrM == 'h10000005) begin - //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount); - //release dut.core.ieu.dp.ReadDataM; - //end - end - end - end - - // step2: make all checks in the write back stage. - assign checkInstrW = InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction. - always @(negedge clk) begin - #1; // small delay allows interrupt spoofing to happen first - // always check PC, instruction bits - if (checkInstrW) begin - InstrCountW += 1; - // print progress message - if (AttemptedInstructionCount % 'd100000 == 0) $display("Reached %d instructions", AttemptedInstructionCount); - // turn on waves - if (AttemptedInstructionCount == INSTR_WAVEON) $stop; - // end sim - if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end - fault = 0; - if (`DEBUG_TRACE >= 1) begin - `checkEQ("PCW",PCW,ExpectedPCW) - //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of - // compressed to uncompressed conversion - `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW) - #2; // delay 2 ns. - if(`DEBUG_TRACE >= 5) begin - $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); - $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); - end - if (RegWriteW == "GPR") begin - `checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW) - $sformat(name,"RF[%02d]",ExpectedRegAdrW); - `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW) - end - if (MemOpW.substr(0,2) == "Mem") begin - if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); - `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) - if(MemOpW == "MemR" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); - `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) - end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); - `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) - end - end - // check csr - for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin - case(ExpectedCSRArrayW[NumCSRPostWIndex]) - "mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW) - "mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW) - "sstatus": `checkCSR(`CSR_BASE.csrs.csrs.SSTATUS_REGW) - "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) - "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) - "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) - "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) - "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) - "mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW) - "sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW) - "scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW) - "stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW) - "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) - "mip": begin - `checkCSR(`CSR_BASE.csrm.MIP_REGW) - if(!NO_SPOOFING) begin - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0) - force `MEIP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0) - force `SEIP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & ((1<<11) | (1<<09))) == 0) - force `UART_IP = 0; - if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<07) == 0) - force `MTIP = 0; - end - end - endcase - end - if (fault == 1) begin - errorCount +=1; - $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); - $stop; $stop; - end - end // if (`DEBUG_TRACE >= 1) - end // if (checkInstrW) - end // always @ (negedge clk) - - - // New IP spoofing - logic globalIntsBecomeEnabled; - assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); - logic checkInterruptM; - assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM; - - always @(negedge clk) begin - if(checkInterruptM) begin - if((interruptInstrCount+1) == AttemptedInstructionCount) begin - if(!NO_SPOOFING) begin - case (interruptCauseVal) - 11: begin - force `MEIP = 1; - force `UART_IP = 1; - end - 09: begin - force `SEIP = 1; - force `UART_IP = 1; - end - 07: force `MTIP = 1; - default: $display("Unsupported interrupt in interrupts.txt. cause = %0d",interruptCauseVal); - endcase - $display("Forcing interrupt."); - end - `SCAN_NEW_INTERRUPT - if (globalIntsBecomeEnabled) begin - $display("Enabled global interrupts"); - // The idea here is if a CSR instruction causes an interrupt by - // enabling interrupts, that CSR instruction will commit. - end else begin - // Other instructions, however, will get interrupted and not - // commit, so we don't want our W-stage checker to look for them - // and get confused when it doesn't find them. - garbageInt = $fgets(garbageString,traceFileE); - garbageInt = $fgets(garbageString,traceFileM); - AttemptedInstructionCount += 1; - end - end - end - end - - - - - - - - - - - /////////////////////////////////////////////////////////////////////////////// - //////////////////////////////// Extra Features /////////////////////////////// - /////////////////////////////////////////////////////////////////////////////// - // Function Tracking - FunctionName #(P) FunctionName(.reset(reset), - .clk(clk), - .ProgramAddrMapFile(ProgramAddrMapFile), - .ProgramLabelMapFile(ProgramLabelMapFile)); - - // Instr Opcode Tracking - // For waveview convenience - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.InstrRawF[31:0], - dut.core.ifu.InstrD, dut.core.ifu.InstrE, - InstrM, InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - - // ------------------ - // Address Translator - // ------------------ - /** - * Walk the page table stored in ram according to sv39 logic and translate a - * virtual address to a physical address. - * - * See section 4.3.2 of the RISC-V Privileged specification for a full - * explanation of the below algorithm. - */ - logic SvMode, PTE_R, PTE_X; - logic [P.XLEN-1:0] SATP, PTE; - logic [55:0] BaseAdr, PAdr; - logic [8:0] VPN [2:0]; - logic [11:0] Offset; - function logic [P.XLEN-1:0] adrTranslator( - input logic [P.XLEN-1:0] adrIn); - begin - int i; - // Grab the SATP register from privileged unit - SATP = dut.core.priv.priv.csr.SATP_REGW; - // Split the virtual address into page number segments and offset - VPN[2] = adrIn[38:30]; - VPN[1] = adrIn[29:21]; - VPN[0] = adrIn[20:12]; - Offset = adrIn[11:0]; - // We do not support sv48; only sv39 - SvMode = SATP[63]; - // Only perform translation if translation is on and the processor is not - // in machine mode - if (SvMode & (dut.core.priv.priv.PrivilegeModeW != P.M_MODE)) begin - BaseAdr = SATP[43:0] << 12; - for (i = 2; i >= 0; i--) begin - PAdr = BaseAdr + (VPN[i] << 3); - // ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift - // by 3 (the PTE size) to get the requested 64-bit PTE. - PTE = dut.uncore.uncore.ram.ram.memory.RAM[PAdr >> 3]; - PTE_R = PTE[1]; - PTE_X = PTE[3]; - if (PTE_R | PTE_X) begin - // Leaf page found - break; - end else begin - // Go to next level of table - BaseAdr = PTE[53:10] << 12; - end - end - // Determine which parts of the PTE page number to use based on the - // level of the page table we reached. - if (i == 2) begin - // Gigapage - assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset}; - end else if (i == 1) begin - // Megapage - assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset}; - end else begin - // Kilopage - assign adrTranslator = {8'b0, PTE[53:10], Offset}; - end - end else begin - // Direct translation if address translation is not on - assign adrTranslator = adrIn; - end - end - endfunction -endmodule diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv index 44afbcd3b..85b39e766 100644 --- a/testbench/testbench-xcelium.sv +++ b/testbench/testbench-xcelium.sv @@ -335,7 +335,7 @@ module testbench; if (P.UNCORE_RAM_SUPPORTED) begin `ifdef TB_UNCORE_RAM_SUPPORTED for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0; `endif end if(reset) begin // branch predictor must always be reset @@ -411,7 +411,7 @@ module testbench; .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin assign HREADYEXT = 1; - assign {HRESPEXT, HRDATAEXT} = '0; + assign {HRESPEXT, HRDATAEXT} = 0; end if(P.FPGA) begin : sdcard @@ -424,8 +424,8 @@ module testbench; assign SDCCmdIn = SDCCmd; assign SDCDatIn = SDCDat; end else begin - assign SDCCmd = '0; - assign SDCDat = '0; + assign SDCCmd = 0; + assign SDCDat = 0; end wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b20c6a993..1a72d4f0f 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -29,6 +29,10 @@ `include "tests.vh" `include "BranchPredictorType.vh" +`ifdef USE_IMPERAS_DV + `include "idv/idv.svh" +`endif + import cvw::*; module testbench; @@ -40,7 +44,15 @@ module testbench; parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; - + parameter RISCV_DIR = "/opt/riscv"; + parameter INSTR_LIMIT = 0; + + `ifdef USE_IMPERAS_DV + import idvPkg::*; + import rvviApiPkg::*; + import idvApiPkg::*; + `endif + `include "parameter-defs.vh" logic clk; @@ -104,12 +116,15 @@ module testbench; "arch64d": if (P.D_SUPPORTED) tests = arch64d; "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; "arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma; + "arch64f_divsqrt": if (P.F_SUPPORTED) tests = arch64f_divsqrt; + "arch64d_divsqrt": if (P.D_SUPPORTED) tests = arch64d_divsqrt; "arch64zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei; "arch64zicond": if (P.ZICOND_SUPPORTED) tests = arch64zicond; "imperas64i": tests = imperas64i; "imperas64f": if (P.F_SUPPORTED) tests = imperas64f; "imperas64d": if (P.D_SUPPORTED) tests = imperas64d; "imperas64m": if (P.M_SUPPORTED) tests = imperas64m; + "wally64q": if (P.Q_SUPPORTED) tests = wally64q; "wally64a": if (P.A_SUPPORTED) tests = wally64a; "imperas64c": if (P.C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; @@ -119,7 +134,7 @@ module testbench; "wally64periph": tests = wally64periph; "coremark": tests = coremark; "fpga": tests = fpga; - "ahb" : tests = ahb; + "ahb64" : tests = ahb64; "coverage64gc" : tests = coverage64gc; "arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba; "arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb; @@ -128,8 +143,11 @@ module testbench; "arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz; "arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb; "arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh; + "arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma; + "arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; "arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad; + "buildroot": tests = buildroot; endcase end else begin // RV32 case (TEST) @@ -145,6 +163,8 @@ module testbench; "arch32d": if (P.D_SUPPORTED) tests = arch32d; "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; "arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma; + "arch32f_divsqrt": if (P.F_SUPPORTED) tests = arch32f_divsqrt; + "arch32d_divsqrt": if (P.D_SUPPORTED) tests = arch32d_divsqrt; "arch32zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei; "arch32zicond": if (P.ZICOND_SUPPORTED) tests = arch32zicond; "imperas32i": tests = imperas32i; @@ -156,6 +176,7 @@ module testbench; "wally32i": tests = wally32i; "wally32priv": tests = wally32priv; "wally32periph": tests = wally32periph; + "ahb32" : tests = ahb32; "embench": tests = embench; "coremark": tests = coremark; "arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba; @@ -165,13 +186,15 @@ module testbench; "arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz; "arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb; "arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh; + "arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma; + "arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; "arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad; endcase end if (tests.size() == 0) begin $display("TEST %s not supported in this configuration", TEST); - $stop; + $finish; end end // initial begin @@ -201,7 +224,7 @@ module testbench; logic ResetCntRst; logic CopyRAM; - string signame, memfilename, pathname; + string signame, memfilename, bootmemfilename, pathname; integer begin_signature_addr, end_signature_addr, signature_size; assign ResetThreshold = 3'd5; @@ -270,10 +293,17 @@ module testbench; always @(posedge clk) begin if(SelectTest) begin if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; + else if(TEST == "buildroot") begin + memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; + bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; + end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; + end else if (TEST == "buildroot") begin + ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"}; + ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"}; end else begin ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; @@ -317,19 +347,18 @@ module testbench; end else begin // for tests with no self checking mechanism, read .signature.output file and compare to check for errors // clear signature to prevent contamination from previous tests + if (!begin_signature_addr) + $display("begin_signature addr not found in %s", ProgramLabelMapFile); + else if (TEST != "embench") begin // *** quick hack for embench. need a better long term solution + CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); + if(errors > 0) totalerrors = totalerrors + 1; + end end - - if (!begin_signature_addr) - $display("begin_signature addr not found in %s", ProgramLabelMapFile); - else if (TEST != "embench") begin // *** quick hack for embench. need a better long term solution - CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); - end - if(errors > 0) totalerrors = totalerrors + 1; test = test + 1; // *** this probably needs to be moved. if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); else $display("FAIL: %d test programs had errors", totalerrors); - $stop; + $stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage end end end @@ -344,6 +373,8 @@ module testbench; integer StartIndex; integer EndIndex; integer BaseIndex; + integer memFile; + integer readResult; if (P.SDC_SUPPORTED) begin always @(posedge clk) begin if (LoadMem) begin @@ -365,7 +396,16 @@ module testbench; end else if (P.BUS_SUPPORTED) begin : bus_supported always @(posedge clk) begin if (LoadMem) begin - $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (TEST == "buildroot") begin + memFile = $fopen(bootmemfilename, "rb"); + readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile); + $fclose(memFile); + memFile = $fopen(memfilename, "rb"); + readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile); + $fclose(memFile); + end else + $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (TEST == "embench") $display("Read memfile %s", memfilename); end if (CopyRAM) begin LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64 @@ -401,7 +441,7 @@ module testbench; always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0; //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -418,7 +458,7 @@ module testbench; .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin assign HREADYEXT = 1; - assign {HRESPEXT, HRDATAEXT} = '0; + assign {HRESPEXT, HRDATAEXT} = 0; end if(P.SDC_SUPPORTED) begin : sdcard @@ -434,9 +474,9 @@ module testbench; assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i; assign SDCDatIn = SDCDat; -----/\----- EXCLUDED -----/\----- */ - assign SDCIntr = '0; + assign SDCIntr = 0; end else begin - assign SDCIntr = '0; + assign SDCIntr = 0; end wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, @@ -511,6 +551,175 @@ module testbench; DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); + if(P.ZICSR_SUPPORTED & INSTR_LIMIT != 0) begin + logic [P.XLEN-1:0] Minstret; + assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; + always @(negedge clk) begin + if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); + if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end + end +end + + //////////////////////////////////////////////////////////////////////////////// + // ImperasDV Co-simulator hooks + //////////////////////////////////////////////////////////////////////////////// +`ifdef USE_IMPERAS_DV + + rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi(); + wallyTracer #(P) wallyTracer(rvvi); + + trace2log idv_trace2log(rvvi); + // trace2cov idv_trace2cov(rvvi); + + // enabling of comparison types + trace2api #(.CMP_PC (1), + .CMP_INS (1), + .CMP_GPR (1), + .CMP_FPR (1), + .CMP_VR (0), + .CMP_CSR (1) + ) idv_trace2api(rvvi); + + initial begin + int iter; + #1; + IDV_MAX_ERRORS = 3; + + // Initialize REF (do this before initializing the DUT) + if (!rvviVersionCheck(RVVI_API_VERSION)) begin + $display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); + $fatal; + end + + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); + void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); + void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56)); + void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6)); + + if (!rvviRefInit("")) begin + $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); + $fatal; + end + + // Volatile CSRs + void'(rvviRefCsrSetVolatile(0, 32'hC00)); // CYCLE + void'(rvviRefCsrSetVolatile(0, 32'hB00)); // MCYCLE + void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET + void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET + void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME + + // User HPMCOUNTER3 - HPMCOUNTER31 + for (iter='hC03; iter<='hC1F; iter++) begin + void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx + end + + // Machine MHPMCOUNTER3 - MHPMCOUNTER31 + for (iter='hB03; iter<='hB1F; iter++) begin + void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx + end + + // cannot predict this register due to latency between + // pending and taken + void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP + void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP + + // Privileges for PMA are set in the imperas.ic + // volatile (IO) regions are defined here + // only real ROM/RAM areas are BOOTROM and UNCORE_RAM + if (P.CLINT_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE))); + end + if (P.GPIO_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE))); + end + if (P.UART_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE))); + end + if (P.PLIC_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE))); + end + if (P.SDC_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE))); + end + if (P.SPI_SUPPORTED) begin + void'(rvviRefMemorySetVolatile(P.SPI_BASE, (P.SPI_BASE + P.SPI_RANGE))); + end + + if(P.XLEN==32) begin + void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH + void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH + end + + void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!! + + // Load memory + // *** RT: This section can probably be moved into the same chunk of code which + // loads the memories. However I'm not sure that ImperasDV supports reloading + // the memories without relaunching the simulator. + begin + longint x64; + int x32[2]; + longint index; + string memfilenameImperasDV, bootmemfilenameImperasDV; + + memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"}; + bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; + + $display("RVVI Loading bootmem.bin"); + memFile = $fopen(bootmemfilenameImperasDV, "rb"); + index = 'h1000 - 8; + while(!$feof(memFile)) begin + index+=8; + readResult = $fread(x64, memFile); + if (x64 == 0) continue; + x32[0] = x64 & 'hffffffff; + x32[1] = x64 >> 32; + rvviRefMemoryWrite(0, index+0, x32[0], 4); + rvviRefMemoryWrite(0, index+4, x32[1], 4); + //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); + end + $fclose(memFile); + + $display("RVVI Loading ram.bin"); + memFile = $fopen(memfilenameImperasDV, "rb"); + index = 'h80000000 - 8; + while(!$feof(memFile)) begin + index+=8; + readResult = $fread(x64, memFile); + if (x64 == 0) continue; + x32[0] = x64 & 'hffffffff; + x32[1] = x64 >> 32; + rvviRefMemoryWrite(0, index+0, x32[0], 4); + rvviRefMemoryWrite(0, index+4, x32[1], 4); + //$display("ram %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]); + end + $fclose(memFile); + + $display("RVVI Loading Complete"); + + void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address + end + end + + always @(dut.core.priv.priv.csr.csri.MIP_REGW[7]) void'(rvvi.net_push("MTimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[7])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[11]) void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[9]) void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[3]) void'(rvvi.net_push("MSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[3])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[1]) void'(rvvi.net_push("SSWInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[1])); + always @(dut.core.priv.priv.csr.csri.MIP_REGW[5]) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[5])); + + final begin + void'(rvviRefShutdown()); + end + +`endif + //////////////////////////////////////////////////////////////////////////////// + // END of ImperasDV Co-simulator hooks + //////////////////////////////////////////////////////////////////////////////// + task automatic CheckSignature; // This task must be declared inside this module as it needs access to parameter P. There is // no way to pass P to the task unless we convert it to a module. @@ -593,7 +802,7 @@ module testbench; errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); - $stop; + $stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage end end if (errors) $display("%s failed with %d errors. :(", TestName, errors); diff --git a/testbench/tests.vh b/testbench/tests.vh index fecf4ebc9..afde1f2e6 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -31,6 +31,7 @@ `define EMBENCH "4" `define CUSTOM "5" `define COVERAGE "6" +`define BUILDROOT "7" string tvpaths[] = '{ "$RISCV/imperas-riscv-tests/work/", @@ -44,8 +45,6 @@ string tvpaths[] = '{ string coverage64gc[] = '{ `COVERAGE, - "tlbmisc", - "tlbNAPOT", "ieu", "priv", "ebu", @@ -54,6 +53,8 @@ string tvpaths[] = '{ "fpu", "lsu", "vm64check", + "tlbmisc", + "tlbNAPOT", "tlbASID", "tlbGLB", "tlbMP", @@ -67,9 +68,15 @@ string tvpaths[] = '{ "pmpcfg1", "pmpcfg2", "pmppriority", + "pmpcbo", "pmpadrdecs" }; + string buildroot[] = '{ + `BUILDROOT, + "buildroot" + }; + string coremark[] = '{ `COREMARK, "coremark.bare.riscv" @@ -862,6 +869,10 @@ string imperas32f[] = '{ "rv32i_m/I/XORI-01" }; + string wally64q[] = '{ + `WALLYTEST, + "rv64i_m/Q/src/WALLY-q-01.S" + }; string wally64a[] = '{ `WALLYTEST, @@ -1125,10 +1136,18 @@ string imperas32f[] = '{ // "rv64i_m/F/src/fnmsub_b15-01.S" }; - string arch64f[] = '{ + string arch64zfh_fma[] = '{ + `RISCVARCHTEST, + "rv64i_m/Zfh/src/fmadd_b15-01.S", + "rv64i_m/Zfh/src/fmsub_b15-01.S", + "rv64i_m/Zfh/src/fnmadd_b15-01.S", + "rv64i_m/Zfh/src/fnmsub_b15-01.S" + }; + + string arch64f_divsqrt[] = '{ `RISCVARCHTEST, - "rv64i_m/F/src/fdiv_b1-01.S", "rv64i_m/F/src/fdiv_b20-01.S", + "rv64i_m/F/src/fdiv_b1-01.S", "rv64i_m/F/src/fdiv_b2-01.S", "rv64i_m/F/src/fdiv_b21-01.S", "rv64i_m/F/src/fdiv_b3-01.S", @@ -1146,7 +1165,11 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsqrt_b5-01.S", "rv64i_m/F/src/fsqrt_b7-01.S", "rv64i_m/F/src/fsqrt_b8-01.S", - "rv64i_m/F/src/fsqrt_b9-01.S", + "rv64i_m/F/src/fsqrt_b9-01.S" + }; + + string arch64f[] = '{ + `RISCVARCHTEST, "rv64i_m/F/src/fadd_b10-01.S", "rv64i_m/F/src/fadd_b1-01.S", "rv64i_m/F/src/fadd_b11-01.S", @@ -1177,17 +1200,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fcvt.wu.s_b27-01.S", "rv64i_m/F/src/fcvt.wu.s_b28-01.S", "rv64i_m/F/src/fcvt.wu.s_b29-01.S", - "rv64i_m/F/src/fdiv_b1-01.S", - "rv64i_m/F/src/fdiv_b20-01.S", - "rv64i_m/F/src/fdiv_b2-01.S", - "rv64i_m/F/src/fdiv_b21-01.S", - "rv64i_m/F/src/fdiv_b3-01.S", - "rv64i_m/F/src/fdiv_b4-01.S", - "rv64i_m/F/src/fdiv_b5-01.S", - "rv64i_m/F/src/fdiv_b6-01.S", - "rv64i_m/F/src/fdiv_b7-01.S", - "rv64i_m/F/src/fdiv_b8-01.S", - "rv64i_m/F/src/fdiv_b9-01.S", "rv64i_m/F/src/feq_b1-01.S", "rv64i_m/F/src/feq_b19-01.S", "rv64i_m/F/src/fle_b1-01.S", @@ -1268,15 +1280,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsgnj_b1-01.S", "rv64i_m/F/src/fsgnjn_b1-01.S", "rv64i_m/F/src/fsgnjx_b1-01.S", - "rv64i_m/F/src/fsqrt_b1-01.S", - "rv64i_m/F/src/fsqrt_b20-01.S", - "rv64i_m/F/src/fsqrt_b2-01.S", - "rv64i_m/F/src/fsqrt_b3-01.S", - "rv64i_m/F/src/fsqrt_b4-01.S", - "rv64i_m/F/src/fsqrt_b5-01.S", - "rv64i_m/F/src/fsqrt_b7-01.S", - "rv64i_m/F/src/fsqrt_b8-01.S", - "rv64i_m/F/src/fsqrt_b9-01.S", "rv64i_m/F/src/fsub_b10-01.S", "rv64i_m/F/src/fsub_b1-01.S", "rv64i_m/F/src/fsub_b11-01.S", @@ -1291,6 +1294,30 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsw-align-01.S" }; + string arch64zfh_divsqrt[] = '{ + `RISCVARCHTEST, + "rv64i_m/Zfh/src/fdiv_b20-01.S", + "rv64i_m/Zfh/src/fdiv_b1-01.S", + "rv64i_m/Zfh/src/fdiv_b2-01.S", + "rv64i_m/Zfh/src/fdiv_b21-01.S", + "rv64i_m/Zfh/src/fdiv_b3-01.S", + "rv64i_m/Zfh/src/fdiv_b4-01.S", + "rv64i_m/Zfh/src/fdiv_b5-01.S", + "rv64i_m/Zfh/src/fdiv_b6-01.S", + "rv64i_m/Zfh/src/fdiv_b7-01.S", + "rv64i_m/Zfh/src/fdiv_b8-01.S", + "rv64i_m/Zfh/src/fdiv_b9-01.S", + "rv64i_m/Zfh/src/fsqrt_b1-01.S", + "rv64i_m/Zfh/src/fsqrt_b20-01.S", + "rv64i_m/Zfh/src/fsqrt_b2-01.S", + "rv64i_m/Zfh/src/fsqrt_b3-01.S", + "rv64i_m/Zfh/src/fsqrt_b4-01.S", + "rv64i_m/Zfh/src/fsqrt_b5-01.S", + "rv64i_m/Zfh/src/fsqrt_b7-01.S", + "rv64i_m/Zfh/src/fsqrt_b8-01.S", + "rv64i_m/Zfh/src/fsqrt_b9-01.S" + }; + string arch64zfh[] = '{ `RISCVARCHTEST, "rv64i_m/Zfh/src/fadd_b10-01.S", @@ -1341,17 +1368,6 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S", "rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S", "rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S", - "rv64i_m/Zfh/src/fdiv_b20-01.S", - "rv64i_m/Zfh/src/fdiv_b1-01.S", - "rv64i_m/Zfh/src/fdiv_b2-01.S", - "rv64i_m/Zfh/src/fdiv_b21-01.S", - "rv64i_m/Zfh/src/fdiv_b3-01.S", - "rv64i_m/Zfh/src/fdiv_b4-01.S", - "rv64i_m/Zfh/src/fdiv_b5-01.S", - "rv64i_m/Zfh/src/fdiv_b6-01.S", - "rv64i_m/Zfh/src/fdiv_b7-01.S", - "rv64i_m/Zfh/src/fdiv_b8-01.S", - "rv64i_m/Zfh/src/fdiv_b9-01.S", "rv64i_m/Zfh/src/feq_b1-01.S", "rv64i_m/Zfh/src/feq_b19-01.S", "rv64i_m/Zfh/src/fle_b1-01.S", @@ -1384,15 +1400,6 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/fsgnj_b1-01.S", "rv64i_m/Zfh/src/fsgnjn_b1-01.S", "rv64i_m/Zfh/src/fsgnjx_b1-01.S", - "rv64i_m/Zfh/src/fsqrt_b1-01.S", - "rv64i_m/Zfh/src/fsqrt_b20-01.S", - "rv64i_m/Zfh/src/fsqrt_b2-01.S", - "rv64i_m/Zfh/src/fsqrt_b3-01.S", - "rv64i_m/Zfh/src/fsqrt_b4-01.S", - "rv64i_m/Zfh/src/fsqrt_b5-01.S", - "rv64i_m/Zfh/src/fsqrt_b7-01.S", - "rv64i_m/Zfh/src/fsqrt_b8-01.S", - "rv64i_m/Zfh/src/fsqrt_b9-01.S", "rv64i_m/Zfh/src/fsub_b10-01.S", "rv64i_m/Zfh/src/fsub_b1-01.S", "rv64i_m/Zfh/src/fsub_b11-01.S", @@ -1404,7 +1411,55 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/fsub_b5-01.S", "rv64i_m/Zfh/src/fsub_b7-01.S", "rv64i_m/Zfh/src/fsub_b8-01.S", - "rv64i_m/Zfh/src/fsh-align-01.S" + "rv64i_m/Zfh/src/fsh-align-01.S", + "rv64i_m/Zfh/src/fmadd_b1-01.S", + "rv64i_m/Zfh/src/fmadd_b14-01.S", + "rv64i_m/Zfh/src/fmadd_b16-01.S", + "rv64i_m/Zfh/src/fmadd_b17-01.S", + "rv64i_m/Zfh/src/fmadd_b18-01.S", + "rv64i_m/Zfh/src/fmadd_b2-01.S", + "rv64i_m/Zfh/src/fmadd_b3-01.S", + "rv64i_m/Zfh/src/fmadd_b4-01.S", + "rv64i_m/Zfh/src/fmadd_b5-01.S", + "rv64i_m/Zfh/src/fmadd_b6-01.S", + "rv64i_m/Zfh/src/fmadd_b7-01.S", + "rv64i_m/Zfh/src/fmadd_b8-01.S", + "rv64i_m/Zfh/src/fmsub_b1-01.S", + "rv64i_m/Zfh/src/fmsub_b14-01.S", + "rv64i_m/Zfh/src/fmsub_b16-01.S", + "rv64i_m/Zfh/src/fmsub_b17-01.S", + "rv64i_m/Zfh/src/fmsub_b18-01.S", + "rv64i_m/Zfh/src/fmsub_b2-01.S", + "rv64i_m/Zfh/src/fmsub_b3-01.S", + "rv64i_m/Zfh/src/fmsub_b4-01.S", + "rv64i_m/Zfh/src/fmsub_b5-01.S", + "rv64i_m/Zfh/src/fmsub_b6-01.S", + "rv64i_m/Zfh/src/fmsub_b7-01.S", + "rv64i_m/Zfh/src/fmsub_b8-01.S", + "rv64i_m/Zfh/src/fnmadd_b1-01.S", + "rv64i_m/Zfh/src/fnmadd_b14-01.S", + "rv64i_m/Zfh/src/fnmadd_b16-01.S", + "rv64i_m/Zfh/src/fnmadd_b17-01.S", + "rv64i_m/Zfh/src/fnmadd_b18-01.S", + "rv64i_m/Zfh/src/fnmadd_b2-01.S", + "rv64i_m/Zfh/src/fnmadd_b3-01.S", + "rv64i_m/Zfh/src/fnmadd_b4-01.S", + "rv64i_m/Zfh/src/fnmadd_b5-01.S", + "rv64i_m/Zfh/src/fnmadd_b6-01.S", + "rv64i_m/Zfh/src/fnmadd_b7-01.S", + "rv64i_m/Zfh/src/fnmadd_b8-01.S", + "rv64i_m/Zfh/src/fnmsub_b1-01.S", + "rv64i_m/Zfh/src/fnmsub_b14-01.S", + "rv64i_m/Zfh/src/fnmsub_b16-01.S", + "rv64i_m/Zfh/src/fnmsub_b17-01.S", + "rv64i_m/Zfh/src/fnmsub_b18-01.S", + "rv64i_m/Zfh/src/fnmsub_b2-01.S", + "rv64i_m/Zfh/src/fnmsub_b3-01.S", + "rv64i_m/Zfh/src/fnmsub_b4-01.S", + "rv64i_m/Zfh/src/fnmsub_b5-01.S", + "rv64i_m/Zfh/src/fnmsub_b6-01.S", + "rv64i_m/Zfh/src/fnmsub_b7-01.S", + "rv64i_m/Zfh/src/fnmsub_b8-01.S" }; @@ -1416,9 +1471,8 @@ string imperas32f[] = '{ // "rv64i_m/D/src/fnmsub.d_b15-01.S" }; - string arch64d[] = '{ + string arch64d_divsqrt[] = '{ `RISCVARCHTEST, - // for speed "rv64i_m/D/src/fdiv.d_b1-01.S", "rv64i_m/D/src/fdiv.d_b20-01.S", "rv64i_m/D/src/fdiv.d_b2-01.S", @@ -1438,8 +1492,13 @@ string imperas32f[] = '{ "rv64i_m/D/src/fsqrt.d_b5-01.S", "rv64i_m/D/src/fsqrt.d_b7-01.S", "rv64i_m/D/src/fsqrt.d_b8-01.S", - "rv64i_m/D/src/fsqrt.d_b9-01.S", - "rv64i_m/D/src/fadd.d_b10-01.S", + "rv64i_m/D/src/fsqrt.d_b9-01.S" + }; + + string arch64d[] = '{ + `RISCVARCHTEST, + // for speed + "rv64i_m/D/src/fadd.d_b10-01.S", "rv64i_m/D/src/fadd.d_b1-01.S", "rv64i_m/D/src/fadd.d_b11-01.S", "rv64i_m/D/src/fadd.d_b12-01.S", @@ -1501,17 +1560,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fcvt.wu.d_b27-01.S", "rv64i_m/D/src/fcvt.wu.d_b28-01.S", "rv64i_m/D/src/fcvt.wu.d_b29-01.S", - "rv64i_m/D/src/fdiv.d_b1-01.S", - "rv64i_m/D/src/fdiv.d_b20-01.S", - "rv64i_m/D/src/fdiv.d_b2-01.S", - "rv64i_m/D/src/fdiv.d_b21-01.S", - "rv64i_m/D/src/fdiv.d_b3-01.S", - "rv64i_m/D/src/fdiv.d_b4-01.S", - "rv64i_m/D/src/fdiv.d_b5-01.S", - "rv64i_m/D/src/fdiv.d_b6-01.S", - "rv64i_m/D/src/fdiv.d_b7-01.S", - "rv64i_m/D/src/fdiv.d_b8-01.S", - "rv64i_m/D/src/fdiv.d_b9-01.S", "rv64i_m/D/src/feq.d_b1-01.S", "rv64i_m/D/src/feq.d_b19-01.S", "rv64i_m/D/src/fle.d_b1-01.S", @@ -1589,15 +1637,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fsgnj.d_b1-01.S", "rv64i_m/D/src/fsgnjn.d_b1-01.S", "rv64i_m/D/src/fsgnjx.d_b1-01.S", - "rv64i_m/D/src/fsqrt.d_b1-01.S", - "rv64i_m/D/src/fsqrt.d_b20-01.S", - "rv64i_m/D/src/fsqrt.d_b2-01.S", - "rv64i_m/D/src/fsqrt.d_b3-01.S", - "rv64i_m/D/src/fsqrt.d_b4-01.S", - "rv64i_m/D/src/fsqrt.d_b5-01.S", - "rv64i_m/D/src/fsqrt.d_b7-01.S", - "rv64i_m/D/src/fsqrt.d_b8-01.S", - "rv64i_m/D/src/fsqrt.d_b9-01.S", "rv64i_m/D/src/fssub.d_b10-01.S", "rv64i_m/D/src/fssub.d_b1-01.S", "rv64i_m/D/src/fssub.d_b11-01.S", @@ -1753,6 +1792,30 @@ string arch64zbs[] = '{ // "rv32i_m/F/src/fnmsub_b15-01.S" }; + string arch32f_divsqrt[] = '{ + `RISCVARCHTEST, + "rv32i_m/F/src/fdiv_b20-01.S", + "rv32i_m/F/src/fdiv_b1-01.S", + "rv32i_m/F/src/fdiv_b2-01.S", + "rv32i_m/F/src/fdiv_b21-01.S", + "rv32i_m/F/src/fdiv_b3-01.S", + "rv32i_m/F/src/fdiv_b4-01.S", + "rv32i_m/F/src/fdiv_b5-01.S", + "rv32i_m/F/src/fdiv_b6-01.S", + "rv32i_m/F/src/fdiv_b7-01.S", + "rv32i_m/F/src/fdiv_b8-01.S", + "rv32i_m/F/src/fdiv_b9-01.S", + "rv32i_m/F/src/fsqrt_b1-01.S", + "rv32i_m/F/src/fsqrt_b20-01.S", + "rv32i_m/F/src/fsqrt_b2-01.S", + "rv32i_m/F/src/fsqrt_b3-01.S", + "rv32i_m/F/src/fsqrt_b4-01.S", + "rv32i_m/F/src/fsqrt_b5-01.S", + "rv32i_m/F/src/fsqrt_b7-01.S", + "rv32i_m/F/src/fsqrt_b8-01.S", + "rv32i_m/F/src/fsqrt_b9-01.S" + }; + string arch32f[] = '{ `RISCVARCHTEST, "rv32i_m/F/src/fadd_b10-01.S", @@ -1785,17 +1848,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fcvt.wu.s_b27-01.S", "rv32i_m/F/src/fcvt.wu.s_b28-01.S", "rv32i_m/F/src/fcvt.wu.s_b29-01.S", - "rv32i_m/F/src/fdiv_b20-01.S", - "rv32i_m/F/src/fdiv_b1-01.S", - "rv32i_m/F/src/fdiv_b2-01.S", - "rv32i_m/F/src/fdiv_b21-01.S", - "rv32i_m/F/src/fdiv_b3-01.S", - "rv32i_m/F/src/fdiv_b4-01.S", - "rv32i_m/F/src/fdiv_b5-01.S", - "rv32i_m/F/src/fdiv_b6-01.S", - "rv32i_m/F/src/fdiv_b7-01.S", - "rv32i_m/F/src/fdiv_b8-01.S", - "rv32i_m/F/src/fdiv_b9-01.S", "rv32i_m/F/src/feq_b1-01.S", "rv32i_m/F/src/feq_b19-01.S", "rv32i_m/F/src/fle_b1-01.S", @@ -1876,15 +1928,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fsgnj_b1-01.S", "rv32i_m/F/src/fsgnjn_b1-01.S", "rv32i_m/F/src/fsgnjx_b1-01.S", - "rv32i_m/F/src/fsqrt_b1-01.S", - "rv32i_m/F/src/fsqrt_b20-01.S", - "rv32i_m/F/src/fsqrt_b2-01.S", - "rv32i_m/F/src/fsqrt_b3-01.S", - "rv32i_m/F/src/fsqrt_b4-01.S", - "rv32i_m/F/src/fsqrt_b5-01.S", - "rv32i_m/F/src/fsqrt_b7-01.S", - "rv32i_m/F/src/fsqrt_b8-01.S", - "rv32i_m/F/src/fsqrt_b9-01.S", "rv32i_m/F/src/fsub_b10-01.S", "rv32i_m/F/src/fsub_b1-01.S", "rv32i_m/F/src/fsub_b11-01.S", @@ -1899,6 +1942,30 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fsw-align-01.S" }; + string arch32zfh_divsqrt[] = '{ + `RISCVARCHTEST, + "rv32i_m/Zfh/src/fdiv_b20-01.S", + "rv32i_m/Zfh/src/fdiv_b1-01.S", + "rv32i_m/Zfh/src/fdiv_b2-01.S", + "rv32i_m/Zfh/src/fdiv_b21-01.S", + "rv32i_m/Zfh/src/fdiv_b3-01.S", + "rv32i_m/Zfh/src/fdiv_b4-01.S", + "rv32i_m/Zfh/src/fdiv_b5-01.S", + "rv32i_m/Zfh/src/fdiv_b6-01.S", + "rv32i_m/Zfh/src/fdiv_b7-01.S", + "rv32i_m/Zfh/src/fdiv_b8-01.S", + "rv32i_m/Zfh/src/fdiv_b9-01.S", + "rv32i_m/Zfh/src/fsqrt_b1-01.S", + "rv32i_m/Zfh/src/fsqrt_b20-01.S", + "rv32i_m/Zfh/src/fsqrt_b2-01.S", + "rv32i_m/Zfh/src/fsqrt_b3-01.S", + "rv32i_m/Zfh/src/fsqrt_b4-01.S", + "rv32i_m/Zfh/src/fsqrt_b5-01.S", + "rv32i_m/Zfh/src/fsqrt_b7-01.S", + "rv32i_m/Zfh/src/fsqrt_b8-01.S", + "rv32i_m/Zfh/src/fsqrt_b9-01.S" + }; + string arch32zfh[] = '{ `RISCVARCHTEST, "rv32i_m/Zfh/src/fadd_b10-01.S", @@ -1931,17 +1998,6 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S", "rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S", "rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S", - "rv32i_m/Zfh/src/fdiv_b20-01.S", - "rv32i_m/Zfh/src/fdiv_b1-01.S", - "rv32i_m/Zfh/src/fdiv_b2-01.S", - "rv32i_m/Zfh/src/fdiv_b21-01.S", - "rv32i_m/Zfh/src/fdiv_b3-01.S", - "rv32i_m/Zfh/src/fdiv_b4-01.S", - "rv32i_m/Zfh/src/fdiv_b5-01.S", - "rv32i_m/Zfh/src/fdiv_b6-01.S", - "rv32i_m/Zfh/src/fdiv_b7-01.S", - "rv32i_m/Zfh/src/fdiv_b8-01.S", - "rv32i_m/Zfh/src/fdiv_b9-01.S", "rv32i_m/Zfh/src/feq_b1-01.S", "rv32i_m/Zfh/src/feq_b19-01.S", "rv32i_m/Zfh/src/fle_b1-01.S", @@ -1974,15 +2030,6 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/fsgnj_b1-01.S", "rv32i_m/Zfh/src/fsgnjn_b1-01.S", "rv32i_m/Zfh/src/fsgnjx_b1-01.S", - "rv32i_m/Zfh/src/fsqrt_b1-01.S", - "rv32i_m/Zfh/src/fsqrt_b20-01.S", - "rv32i_m/Zfh/src/fsqrt_b2-01.S", - "rv32i_m/Zfh/src/fsqrt_b3-01.S", - "rv32i_m/Zfh/src/fsqrt_b4-01.S", - "rv32i_m/Zfh/src/fsqrt_b5-01.S", - "rv32i_m/Zfh/src/fsqrt_b7-01.S", - "rv32i_m/Zfh/src/fsqrt_b8-01.S", - "rv32i_m/Zfh/src/fsqrt_b9-01.S", "rv32i_m/Zfh/src/fsub_b10-01.S", "rv32i_m/Zfh/src/fsub_b1-01.S", "rv32i_m/Zfh/src/fsub_b11-01.S", @@ -1994,7 +2041,55 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/fsub_b5-01.S", "rv32i_m/Zfh/src/fsub_b7-01.S", "rv32i_m/Zfh/src/fsub_b8-01.S", - "rv32i_m/Zfh/src/fsh-align-01.S" + "rv32i_m/Zfh/src/fsh-align-01.S", + "rv32i_m/Zfh/src/fmadd_b1-01.S", + "rv32i_m/Zfh/src/fmadd_b14-01.S", + "rv32i_m/Zfh/src/fmadd_b16-01.S", + "rv32i_m/Zfh/src/fmadd_b17-01.S", + "rv32i_m/Zfh/src/fmadd_b18-01.S", + "rv32i_m/Zfh/src/fmadd_b2-01.S", + "rv32i_m/Zfh/src/fmadd_b3-01.S", + "rv32i_m/Zfh/src/fmadd_b4-01.S", + "rv32i_m/Zfh/src/fmadd_b5-01.S", + "rv32i_m/Zfh/src/fmadd_b6-01.S", + "rv32i_m/Zfh/src/fmadd_b7-01.S", + "rv32i_m/Zfh/src/fmadd_b8-01.S", + "rv32i_m/Zfh/src/fmsub_b1-01.S", + "rv32i_m/Zfh/src/fmsub_b14-01.S", + "rv32i_m/Zfh/src/fmsub_b16-01.S", + "rv32i_m/Zfh/src/fmsub_b17-01.S", + "rv32i_m/Zfh/src/fmsub_b18-01.S", + "rv32i_m/Zfh/src/fmsub_b2-01.S", + "rv32i_m/Zfh/src/fmsub_b3-01.S", + "rv32i_m/Zfh/src/fmsub_b4-01.S", + "rv32i_m/Zfh/src/fmsub_b5-01.S", + "rv32i_m/Zfh/src/fmsub_b6-01.S", + "rv32i_m/Zfh/src/fmsub_b7-01.S", + "rv32i_m/Zfh/src/fmsub_b8-01.S", + "rv32i_m/Zfh/src/fnmadd_b1-01.S", + "rv32i_m/Zfh/src/fnmadd_b14-01.S", + "rv32i_m/Zfh/src/fnmadd_b16-01.S", + "rv32i_m/Zfh/src/fnmadd_b17-01.S", + "rv32i_m/Zfh/src/fnmadd_b18-01.S", + "rv32i_m/Zfh/src/fnmadd_b2-01.S", + "rv32i_m/Zfh/src/fnmadd_b3-01.S", + "rv32i_m/Zfh/src/fnmadd_b4-01.S", + "rv32i_m/Zfh/src/fnmadd_b5-01.S", + "rv32i_m/Zfh/src/fnmadd_b6-01.S", + "rv32i_m/Zfh/src/fnmadd_b7-01.S", + "rv32i_m/Zfh/src/fnmadd_b8-01.S", + "rv32i_m/Zfh/src/fnmsub_b1-01.S", + "rv32i_m/Zfh/src/fnmsub_b14-01.S", + "rv32i_m/Zfh/src/fnmsub_b16-01.S", + "rv32i_m/Zfh/src/fnmsub_b17-01.S", + "rv32i_m/Zfh/src/fnmsub_b18-01.S", + "rv32i_m/Zfh/src/fnmsub_b2-01.S", + "rv32i_m/Zfh/src/fnmsub_b3-01.S", + "rv32i_m/Zfh/src/fnmsub_b4-01.S", + "rv32i_m/Zfh/src/fnmsub_b5-01.S", + "rv32i_m/Zfh/src/fnmsub_b6-01.S", + "rv32i_m/Zfh/src/fnmsub_b7-01.S", + "rv32i_m/Zfh/src/fnmsub_b8-01.S" }; string arch32zfaf[] = '{ @@ -2065,6 +2160,13 @@ string arch64zbs[] = '{ string arch64zfad[] = '{ `RISCVARCHTEST, + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S", + "rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S", "rv64i_m/D_Zfa/src/fleq_b1-01.S", "rv64i_m/D_Zfa/src/fleq_b19-01.S", "rv64i_m/D_Zfa/src/fli.d-01.S", @@ -2085,6 +2187,38 @@ string arch64zbs[] = '{ "rv32i_m/D/src/fnmsub.d_b15-01.S" }; +string arch32zfh_fma[] = '{ + `RISCVARCHTEST, + "rv32i_m/Zfh/src/fmadd_b15-01.S", + "rv32i_m/Zfh/src/fmsub_b15-01.S", + "rv32i_m/Zfh/src/fnmadd_b15-01.S", + "rv32i_m/Zfh/src/fnmsub_b15-01.S" + }; + + string arch32d_divsqrt[] = '{ + `RISCVARCHTEST, + "rv32i_m/D/src/fdiv.d_b1-01.S", + "rv32i_m/D/src/fdiv.d_b20-01.S", + "rv32i_m/D/src/fdiv.d_b2-01.S", + "rv32i_m/D/src/fdiv.d_b21-01.S", + "rv32i_m/D/src/fdiv.d_b3-01.S", + "rv32i_m/D/src/fdiv.d_b4-01.S", + "rv32i_m/D/src/fdiv.d_b5-01.S", + "rv32i_m/D/src/fdiv.d_b6-01.S", + "rv32i_m/D/src/fdiv.d_b7-01.S", + "rv32i_m/D/src/fdiv.d_b8-01.S", + "rv32i_m/D/src/fdiv.d_b9-01.S", + "rv32i_m/D/src/fsqrt.d_b1-01.S", + "rv32i_m/D/src/fsqrt.d_b20-01.S", + "rv32i_m/D/src/fsqrt.d_b2-01.S", + "rv32i_m/D/src/fsqrt.d_b3-01.S", + "rv32i_m/D/src/fsqrt.d_b4-01.S", + "rv32i_m/D/src/fsqrt.d_b5-01.S", + "rv32i_m/D/src/fsqrt.d_b7-01.S", + "rv32i_m/D/src/fsqrt.d_b8-01.S", + "rv32i_m/D/src/fsqrt.d_b9-01.S" + }; + string arch32d[] = '{ `RISCVARCHTEST, "rv32i_m/D/src/fadd.d_b10-01.S", @@ -2131,17 +2265,6 @@ string arch64zbs[] = '{ "rv32i_m/D/src/fcvt.wu.d_b27-01.S", "rv32i_m/D/src/fcvt.wu.d_b28-01.S", "rv32i_m/D/src/fcvt.wu.d_b29-01.S", - "rv32i_m/D/src/fdiv.d_b1-01.S", - "rv32i_m/D/src/fdiv.d_b20-01.S", - "rv32i_m/D/src/fdiv.d_b2-01.S", - "rv32i_m/D/src/fdiv.d_b21-01.S", - "rv32i_m/D/src/fdiv.d_b3-01.S", - "rv32i_m/D/src/fdiv.d_b4-01.S", - "rv32i_m/D/src/fdiv.d_b5-01.S", - "rv32i_m/D/src/fdiv.d_b6-01.S", - "rv32i_m/D/src/fdiv.d_b7-01.S", - "rv32i_m/D/src/fdiv.d_b8-01.S", - "rv32i_m/D/src/fdiv.d_b9-01.S", "rv32i_m/D/src/feq.d_b1-01.S", "rv32i_m/D/src/feq.d_b19-01.S", "rv32i_m/D/src/fle.d_b1-01.S", @@ -2210,15 +2333,6 @@ string arch64zbs[] = '{ "rv32i_m/D/src/fsgnj.d_b1-01.S", "rv32i_m/D/src/fsgnjn.d_b1-01.S", "rv32i_m/D/src/fsgnjx.d_b1-01.S", - "rv32i_m/D/src/fsqrt.d_b1-01.S", - "rv32i_m/D/src/fsqrt.d_b20-01.S", - "rv32i_m/D/src/fsqrt.d_b2-01.S", - "rv32i_m/D/src/fsqrt.d_b3-01.S", - "rv32i_m/D/src/fsqrt.d_b4-01.S", - "rv32i_m/D/src/fsqrt.d_b5-01.S", - "rv32i_m/D/src/fsqrt.d_b7-01.S", - "rv32i_m/D/src/fsqrt.d_b8-01.S", - "rv32i_m/D/src/fsqrt.d_b9-01.S", "rv32i_m/D/src/fssub.d_b10-01.S", "rv32i_m/D/src/fssub.d_b1-01.S", "rv32i_m/D/src/fssub.d_b11-01.S", @@ -2487,7 +2601,12 @@ string arch64zbs[] = '{ }; - string ahb[] = '{ + string ahb64[] = '{ `RISCVARCHTEST, "rv64i_m/F/src/fadd_b11-01.S" }; + + string ahb32[] = '{ + `RISCVARCHTEST, + "rv32i_m/F/src/fadd_b11-01.S" + }; diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 2f6002efc..6e13dc000 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -17,9 +17,9 @@ all: $(OBJECTS) # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \ + riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../examples/link/link.ld $< - riscv64-unknown-elf-objdump -S $@ > $@.objdump + riscv64-unknown-elf-objdump -S -D $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile extractFunctionRadix.sh $@.objdump diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 55bfcf4e5..edf867240 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -6,6 +6,7 @@ // Purpose: Initialize stack, handle interrupts, terminate test case // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -24,6 +25,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// // load code to initalize stack, handle interrupts, terminate +// The PMP tests are sensitive to the exact addresses in this code, so unfortunately +// modifying anything breaks those tests. .section .text.init .global rvtest_entry_point @@ -36,7 +39,11 @@ rvtest_entry_point: csrw mtvec, t0 # Initialize MTVEC to trap_handler csrw mideleg, zero # Don't delegate interrupts csrw medeleg, zero # Don't delegate exceptions +# li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again +# li t1, 0x02004000 # MTIMECMP in CLINT +# sd t0, 0(t1) li t0, 0x80 +# li t0, 0x00 csrw mie, t0 # Enable machine timer interrupt la t0, topoftrapstack csrw mscratch, t0 # MSCRATCH holds trap stack pointer diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index ce5639bd7..3fe499abd 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -6,6 +6,7 @@ // Purpose: Test writes to CSRs // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/dcache2.S b/tests/coverage/dcache2.S index 58f97a2e4..7d5905288 100644 --- a/tests/coverage/dcache2.S +++ b/tests/coverage/dcache2.S @@ -7,6 +7,7 @@ // (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S index 8c69f9d11..fa7927d95 100644 --- a/tests/coverage/ebu.S +++ b/tests/coverage/ebu.S @@ -1,11 +1,12 @@ /////////////////////////////////////////// // ebu.S // -// Written: David_Harris@hmc.edu 23 March 2023 +// Written: David_Harris@hmc.edu 21 January 2024 // // Purpose: Test coverage for EBU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -24,22 +25,289 @@ //////////////////////////////////////////////////////////////////////////////////////////////// // load code to initalize stack, handle interrupts, terminate + #include "WALLY-init-lib.h" +# run-elf.bash find this in project description main: + li t5, 0x1 + slli t5, t5, 62 + ori t5, t5, 0xF0 + csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1 - # Test clz with all bits being 0 - li t0, 0 - clz t1, t0 - li t0, -1 - clz t1, t0 - li t0, 1 - clz t1, t0 + # Page table root address at 0x80010000; SV48 + li t5, 0x9000000000080010 + csrw satp, t5 - # Test forwarding from store conditional - lr.w t0, 0(a0) - sc.w t0, a1, 0(a0) - addi t0, t0, 1 + # sfence.vma x0, x0 + # switch to supervisor mode + li a0, 1 + ecall + + # + +# Tricky case to cover. I$ miss concurrent with DTLB miss. HPTW has to hit the first +# access in the cache and miss a later one. Trigger this by doing a load that touches +# a page not in the DTLB but where the top-level PTE is already there. Has to happen +# near the end of the 16-instruction I$ line. +# +# Condition Coverage for instance /core/ebu/ebu/ebufsmarb -- +# +# File ../src/ebu/ebufsmarb.sv +#----------------Focused Condition View------------------- +#Line 72 Item 1 ((HREADY & FinalBeatD) & (LSUReq ~& IFUReq)) +#Condition totals: 2 of 4 input terms covered = 50.00% +# +# Input Term Covered Reason for no coverage Hint +# ----------- -------- ----------------------- -------------- +# HREADY Y +# FinalBeatD Y +# LSUReq N '_1' not hit Hit '_1' +# IFUReq N No hits Hit '_0' and '_1' +# +# Rows: Hits FEC Target Non-masking condition(s) +# --------- --------- -------------------- ------------------------- +# Row 1: 2 HREADY_0 ((LSUReq ~& IFUReq) && FinalBeatD) +# Row 2: 14 HREADY_1 ((LSUReq ~& IFUReq) && FinalBeatD) +# Row 3: 1 FinalBeatD_0 ((LSUReq ~& IFUReq) && HREADY) +# Row 4: 14 FinalBeatD_1 ((LSUReq ~& IFUReq) && HREADY) +# Row 5: 14 LSUReq_0 ((HREADY & FinalBeatD) && IFUReq) +# Row 6: ***0*** LSUReq_1 ((HREADY & FinalBeatD) && IFUReq) +# Row 7: ***0*** IFUReq_0 ((HREADY & FinalBeatD) && LSUReq) +# Row 8: ***0*** IFUReq_1 ((HREADY & FinalBeatD) && LSUReq) + + + li a0, 0x80000000 + li a1, 0x80A00000 + j label1 + +.align 6 # start on multiple of 64 bytes / 16 instruction cache line +label1: + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + lw t0, 0x234(a1) # trigger DTLB miss + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + addi t2, t3, 0x10F # occupy part of cache line + +# next multiple of 16 + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x334(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10B # occupy part of cache line + lw t0, 0x334(a1) # trigger DTLB miss + addi t2, t3, 0x10D # occupy part of cache line + addi t2, t3, 0x10E # occupy part of cache line + addi t2, t3, 0x10F # occupy part of cache line + +# next multiple of 16 + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x434(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10B # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + lw t0, 0x434(a1) # trigger DTLB miss + addi t2, t3, 0x10E # occupy part of cache line + addi t2, t3, 0x10F # occupy part of cache line + +# next multiple of 16 + addi t2, t3, 0x100 # occupy part of cache line + sfence.vma # flush tlb + lw t0, 0x534(a0) # load to get an entry in the DTLB accessing top-level PTE + addi t2, t3, 0x103 # occupy part of cache line + addi t2, t3, 0x104 # occupy part of cache line + addi t2, t3, 0x105 # occupy part of cache line + addi t2, t3, 0x106 # occupy part of cache line + addi t2, t3, 0x107 # occupy part of cache line + addi t2, t3, 0x108 # occupy part of cache line + addi t2, t3, 0x109 # occupy part of cache line + addi t2, t3, 0x10A # occupy part of cache line + addi t2, t3, 0x10B # occupy part of cache line + addi t2, t3, 0x10C # occupy part of cache line + addi t2, t3, 0x10D # occupy part of cache line + lw t0, 0x534(a1) # trigger DTLB miss + addi t2, t3, 0x10F # occupy part of cache line + + # wrap up + li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry + ecall j done + + +.data + +.align 16 +# root Page table situated at 0x80010000 +pagetable: + .8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid + .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 + +# next page table at 0x80011000 +.align 12 + .8byte 0x00000000000010CF # misaligned gigapage at 0x00000000 + .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 + .8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000 + + +# Next page table at 0x80012000 for gigapage at 0x80000000 +.align 12 + .8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages) + .8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage) + .8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages) + .8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) + .8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz) + .8byte 0x00000000200058C1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000) + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 + +# Leaf page table at 0x80013000 with NAPOT pages +.align 12 + #80000000 + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + .8byte 0x80000000200060CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + .8byte 0x800000002000A0CF + + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + + .8byte 0x800000002000E0CF + .8byte 0x800000002000E0CF + +# Leaf page table at 0x80014000 with PBMT pages +.align 12 + #80400000 + .8byte 0x60000000200020CF # reserved entry + +# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ +.align 12 + #80800000 + .8byte 0x00000000200000CF # valid rwx for VA 80800000 + .8byte 0x00000000200000CB # valid r x for VA 80801000 + .8byte 0x00000000200000C3 # valid r for VA 80802000 + .8byte 0x00000000200000C9 # valid x for VA 80803000 + .8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol) + .8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA + .8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT + +# Leaf page table at 0x80016000 with NAPOT pages +.align 12 + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF + .8byte 0xA0000000200020CF diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 29ad9b418..497ba0207 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for FPU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -36,6 +37,26 @@ main: flw ft0, 0(t0) fclass.s t1, ft0 + # zfa instructions (because Zfa tests aren't running yet) + fli.d fs0, 16 + fcvtmod.w.d t0, fs0, rtz +# fminm.d fs1, fs0, fs0 +# fmaxm.d fs1, fs0, fs0 +# fltq.d t0, fs1, ft0 +# fleq.d t0, fs1, ft0 + fcvt.d.q fs1, fs0 + fcvt.h.q fs1, fs0 + fcvt.s.q fs1, fs0 + # round for now because these tests are excluded from Zfa until rounding is implemented + fround.s fs1, fs0 + froundnx.s fs1, fs0 + fround.d fs1, fs0 + froundnx.d fs1, fs0 + fround.h fs1, fs0 + froundnx.h fs1, fs0 + fround.s fs1, fs0 + froundnx.s fs1, fs0 + #Result Sign Test Coverage la t0, TestData2 flw ft0, 0(t0) @@ -108,6 +129,12 @@ main: # fcvt.w.q a0, ft0 # fcvt.q.d ft3, ft0 + # half-precision NaN boxing + la t0, TestData3 + fld ft2, 0(t0) // bad NaN-boxed number + fmadd.h ft1, ft2, ft2, ft2 // Test NaN boxing + fmadd.s ft1, ft2, ft2, ft2 // Test NaN boxing + // fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives) // This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes. li t0, 0x3F812345 # random value slightly bigger than 1 @@ -139,7 +166,7 @@ main: .word 0xc5000007 // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to .word 0xe0101053 // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2) .word 0xe0100053 // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2) - .word 0x40500053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. + .word 0x40D00053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. .word 0x40300053 // toggling SupportFmt2 to 0 on line 145 in fctrl. .word 0x42100053 // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr .word 0xf0100053 // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr @@ -155,6 +182,21 @@ main: .word 0xF0007053 // illegal fmv (bad Funct3) .word 0x43007053 // illegal fcvt.d.* (bad Rs2D) .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1]) + .word 0xD5F00053 // illegal fcvt.h.* (bad Rs2D) + .word 0xC5F00053 // illegal fcvt.*.h (bad Rs2D) + .word 0x04000043 // illegal fmadd.h (h not supported) + .word 0xC2800053 // illegal fcvtmod.w.d with rm rne + .word 0xF0101053 // illegal fli with Funct3D not 0 + .word 0xF0400053 // illegal fli with Rs2D not 1 + .word 0x44200053 // illegal instruction for f.cvt.h.h + + // Test divide by zero with rounding mode toward zero + li t0, 1 + csrw frm, t0 // set rounding mode = 1 + li t0, 0x3f800000 + fcvt.s.w ft1, t0 + fcvt.s.w ft2, zero + fdiv.s ft3, ft1, ft2 # Test floating point convert to integer and using result fcvt.w.s t0, f0 @@ -172,4 +214,6 @@ TestData2: .int 0xbf800000 #FP -1.0 .int 0x7fa00000 #SNaN .int 0x3fffffff #OverFlow Test +TestData3: +.dword 0xABCD543212345678 # NaN box test DivTestData: diff --git a/tests/coverage/fround.S b/tests/coverage/fround.S new file mode 100644 index 000000000..7d469d773 --- /dev/null +++ b/tests/coverage/fround.S @@ -0,0 +1,18 @@ +// fround.s + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + + bseti t0, zero, 14 # turn on FPU + csrs mstatus, t0 + + # test fround behavior on NaN + li t0, 0x7FC00001 + fmv.w.x ft0, t0 + fround.s ft1, ft0 + j done + +.align 10 +data_start: diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 1e32a24ab..7ec318632 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for IEU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index f387774bf..4b085d845 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for IFU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -74,8 +75,31 @@ main: .hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else + # exercise all the cache ways + j way0code +# stress test cache ways by loading stuff from each one and then doing fence.i to invalidate +.align 12 +way0code: + jal way1code + fence.i + j done +.align 12 +way1code: + j way2code + +.align 12 +way2code: + j way3code + +.align 12 +way3code: + j way00code + +.align 12 +way00code: + ret j done diff --git a/tests/coverage/ifuCamlineWrite.S b/tests/coverage/ifuCamlineWrite.S index 4c11bf183..db873dec4 100644 --- a/tests/coverage/ifuCamlineWrite.S +++ b/tests/coverage/ifuCamlineWrite.S @@ -9,6 +9,7 @@ // Purpose: Test coverage for TLBCamlines in IFU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S index c50b79eb7..0e065010e 100644 --- a/tests/coverage/lsu.S +++ b/tests/coverage/lsu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for lsu // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -30,4 +31,7 @@ main: sfence.vma x0, x0 // sfence.vma to assert TLBFlush + li a0, 0x80000001 # misaligned address + amoadd.w t0, a0, (a0) # amo access to misaligned address + j done \ No newline at end of file diff --git a/tests/coverage/pmpcbo.S b/tests/coverage/pmpcbo.S new file mode 100644 index 000000000..2e7eab642 --- /dev/null +++ b/tests/coverage/pmpcbo.S @@ -0,0 +1,31 @@ +// pmpcbo.S +// David_Harris@hmc.edu 1/21/24 +// Cover PMP checks of cache management instructions + +#include "WALLY-init-lib.h" +main: + + # set up PMP so user and supervisor mode can access partial address space + li t0, 0x080F; +# li t0, 0x0808; + csrw pmpcfg0, t0 # configure PMP0 to TOR RWX and PMP1 to TOR no access + li t0, 0x2003FFFF + li t1, 0xFFFFFFFF + csrw pmpaddr0, t0 # configure PMP0 top of range to 0x800FFFFF to allow all 32-bit addresses + csrw pmpaddr1, t1 # configure PMP1 top of range to 0xFFFFFFFF to prohibit accesses above + + # enable cbo instructions + li t0, 0xF0 + csrw menvcfg, t0 + csrw senvcfg, t0 + + # switch to supervisor mode + li a0, 1 + ecall + + # cbo instructions to PMP-forbidded address + li a0, 0x81000000 # forbidden address + cbo.zero (a0) + cbo.inval (a0) + + j done \ No newline at end of file diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 39b3a8aeb..105a61e11 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for EBU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S index 278568147..25cf650ca 100644 --- a/tests/coverage/tlbASID.S +++ b/tests/coverage/tlbASID.S @@ -4,9 +4,11 @@ // Written: mmendozamanriquez@hmc.edu 4 April 2023 // nlimpert@hmc.edu // -// Purpose: Test coverage for LSU +// Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd +// numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -24,6 +26,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// + + // load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -42,11 +46,12 @@ main: li t0, 0xC0000000 - li t2, 0 # i = 0 + li t2, 0 # i = 0 li t5, 0 # j = 0 // now use as a counter for new asid loop - li t3, 32 # Max amount of Loops = 32 + li t3, 32 # Max amount of Loops = 32 loop: bge t2, t3, finished # exit loop if i >= loops + sfence.vma li t1, 0x00008067 #load in jalr sw t1, 0(t0) fence.I @@ -54,7 +59,7 @@ loop: bge t2, t3, finished # exit loop if i >= loops li t5, 0x9001000000080080 // try making asid = 1 csrw satp, t5 jalr t0 - li t5, 0x9000000000080080 // try making asid = 0 + li t5, 0x9000000000080080 // try making asid = 0 csrw satp, t5 li t4, 0x1000 add t0, t0, t4 @@ -70,7 +75,7 @@ finished: pagetable: .8byte 0x200204C1 -.align 12 // level 2 page table, contains direction to a gigapageg +.align 12 // level 2 page table, contains direction to a gigapage .8byte 0x0 .8byte 0x0 .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000 diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S index e6ae534bd..de1541610 100644 --- a/tests/coverage/tlbGLB.S +++ b/tests/coverage/tlbGLB.S @@ -8,6 +8,7 @@ // Purpose: Coverage for the Page Table Entry Global flag check. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S index ede79f13e..bbdb703b4 100644 --- a/tests/coverage/tlbGP.S +++ b/tests/coverage/tlbGP.S @@ -7,6 +7,7 @@ // Purpose: Create Page tables and access gigapages // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbKP.S b/tests/coverage/tlbKP.S index 5aaf5c195..4382673ea 100644 --- a/tests/coverage/tlbKP.S +++ b/tests/coverage/tlbKP.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbM3.S b/tests/coverage/tlbM3.S index ececa1f34..eba37ae99 100644 --- a/tests/coverage/tlbM3.S +++ b/tests/coverage/tlbM3.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S index 043e5dc4a..f6dc4c597 100644 --- a/tests/coverage/tlbMP.S +++ b/tests/coverage/tlbMP.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S index 15af7ea30..508eb057c 100644 --- a/tests/coverage/tlbNAPOT.S +++ b/tests/coverage/tlbNAPOT.S @@ -8,6 +8,7 @@ // Purpose: Test coverage for LSU NAPOT // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -54,14 +55,24 @@ main: li t4, 0x1000 # address step size li a2, 0x80216000 # Test NAPOT pages jal a1, looptest + + sfence.vma + li t4, 0x200000 # address step size + li a2, 0x80215240 # Test NAPOT pages + jal a1, looptest + li a2, 0xC0215240 # Test ill-formed NAPOT pages + jal a1, looptest + li a2, 0x40215240 # Test properly formed pages with 1 in PPN[3] that are not NAPOT + jal a1, looptest + li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry ecall j done looptest: mv t0, a2 # base address - li t2, 0 # i = 0 - li t3, 35 # Max amount of Loops = 34 + li t2, 0 # i = 0 + li t3, 32 # Max amount of Loops = 32 li t5, 0x8082 # return instruction opcode loop: bge t2, t3, finished # exit loop if i >= loops diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S index 54857afbd..f4b0a142e 100644 --- a/tests/coverage/tlbTP.S +++ b/tests/coverage/tlbTP.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index 67971dd06..f64645689 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for other TLB issues // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // @@ -62,15 +63,32 @@ main: jalr ra, t0 # jump to misaligned gigapage li t0, 0x80200000 jalr ra, t0 # jump to misaligned megapage + li t0, 0x7FFFFFFF80000000 - # exercise ebufsmarb (not yet providing coverage 1/1/24 DH & RT) - li t0, 0x80000000 - lw t1, 0(t0) # fetch from an address to warm up tlb entries - li t0, 0x80A00000 - lw t1, 0(t0) # trigger TLB miss on a non-first entry - jal backandforth + + jalr ra, t0 # jump to page with UpperBitsUnequal + li t0, 0x0000000080C00000 + jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE + + # test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE, + li a0, 3 + ecall # switch to machine mode + li t0, 1 + slli t0, t0, 61 + csrs menvcfg, t0 # set menvcfg.ADUE + li a0, 1 + ecall # switch back to supervisor mode + li t0, 0x0000000080E00000 + jalr ra, t0 # jump to page without accessed bit yet set + li a0, 3 + ecall # switch to machine mode + li t0, 1 + slli t0, t0, 61 + csrc menvcfg, t0 # clear menvcfg.ADUE + li a0, 1 + ecall # switch back to supervisor mode - # exercise malformed PBMT pages + # exercise malformed PBMT pages # page has PBMT = 3 (reserved) li t0, 0x80400000 @@ -78,7 +96,50 @@ main: sw t1, 0(t0) # write to page jalr ra, t0 # jump to page - # Nonleaf PTE has PBMT != 0 # this should cause a page fault during page walking. However, as of issue 546 1/1/24, both ImperasDV and Wally don't detect this + # AMO at page has PBMT = 2 or 1 (uncached) + li t0, 0x80401000 + li t1, 10 + amoadd.w t1, t1, (t0) + + la t2, SpecialPage + li t0, 0x200000000 # an address to a specific 1 GiB page + j ConcurrentICacheMissDTLBMiss + +.align 6 +ConcurrentICacheMissDTLBMiss: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + lw t1, 0(t0) + + # write a cacheline length (512 bits) to memory in uncached region + li t0, 0x80401000 + cbo.zero (t0) + + # Nonleaf PTE has PBMT != 0 causes a page fault during page walking. H li t0, 0x80600000 lw t1, 0(t0) # read from page sw t1, 0(t0) # write to page @@ -87,21 +148,68 @@ main: # jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0 li t0, 0x80805000 jalr ra, t0 + li t0, 0x80807000 # again, triggering setting access bit + jalr ra, t0 + + # atomic access to uncachable memory + #li t0, 0x80806000 + #sd zero, 0(t0) + #amoadd.w t1, t0, (t0) # Good PBMT with menvcfg.PBMTE = 0 - li t0, 3 + li a0, 3 ecall # switch to machine mode li t5, 0x1 slli t5, t5, 62 csrc menvcfg, t5 # menvcfg.PBMTE = 0 - li t0, 1 + li a0, 1 ecall # switch back to supervisor mode li t0, 0x80806000 - jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_BPMTE=0 + jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0 + + # Load and AMO operation on page table entry that causes access fault + li t0, 0x81000000 + lw t1, 0(t0) + sfence.vma + amoadd.w t0, t0, 0(t0) + + # Access fault on top level PTE + li t0, 0x1000000000 + lw t1, 0(t0) + + # Bad PBMT on top level PTE + li t0, 0x1800000000 + lw t1, 0(t0) + + # Access fault on megapage + li t0, 0x81400000 + lw t1, 0(t0) + + # Access fault walking page tables at megapage level + li t0, 0xC0000000 + lw t1, 0(t0) + + # AMO operation on page table entry that causes page fault due to malformed PBMT + li t0, 0x81200000 + jalr t0 # Attempt to fetch instruction from address causing faulty page walk + lw t1, 0(t0) + sfence.vma + amoadd.w t0, t0, 0(t0) + + # point top-level page table to an illegal address and verify it faults + li t0, 0x9000000000070000 # trap handler at non-existing memory location + csrw satp, t0 # should cause trap + sfence.vma + nop + # change back to default trap handler after checking everything that might cause an instruction page fault jal changetodefaulthandler + # uncachable AMO access + li t0, 0x80401000 # PBMT sets as uncachable + amoadd.w t0, t0, 0(t0) + # exercise CBOM instructions with various permissions li t0, 0x80800000 cbo.zero (t0) @@ -154,6 +262,9 @@ main: li a0, 1 ecall + + + # wrap up li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry ecall @@ -184,12 +295,14 @@ instructionpagefaulthandler: csrw mepc, ra # go back to calling function mret -.align 4 # trap handlers must be aligned to multiple of 4 +.align 4 # trap handlers must be aligned to multiple of 16 ipf_handler: # Load trap handler stack pointer tp csrrw tp, mscratch, tp # swap MSCRATCH and tp sd t0, 0(tp) # Save t0 and t1 on the stack sd t1, -8(tp) + li t5, 0x9000000000080010 + csrw satp, t5 # make sure we are pointing to the root page table csrr t0, mcause # Check the cause li t1, 8 # is it an ecall trap? andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11 @@ -206,37 +319,49 @@ ipf: csrrw tp, mscratch, tp # restore tp mret # return from trap +.align 4 # trap handlers must be aligned to multiple of 16 +fixsatptraphandler: + li t5, 0x9000000000080010 # fix satp entry to normal page table root + csrw satp, t5 + mret + .data .align 16 # root Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid + .8byte 0x200044C1 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 + .8byte 0x00000000000000CF # access fault terapage at 0x100_00000000 + .8byte 0x40000000200044C1 # Bad PBMT at VA 0x180_0000000 # next page table at 0x80011000 .align 12 .8byte 0x00000000000010CF # misaligned gigapage at 0x00000000 - .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 + .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 pointing to 0x80150000 .8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000 + .8byte 0x00000000000000C1 # gigapage at VA 0xC0000000 causes access fault + .8byte 0x0 + .8byte 0x0 + .8byte 0x0 + .8byte 0x0 +SpecialPage: + .8byte 0x00000000200000CF # 0x2_0000_0000 1GiB page1 # Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 - .8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages) + .8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages Page table at 80013000) .8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage) - .8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages) + .8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages page table at 0x80014000) .8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) - .8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz) - .8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000) - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 + .8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz . page table at 0x80015000) + .8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000. page table at 0x80013000) + .8byte 0x0F00000020004CCF # for VA starting at 80C00000 (bad reserved field in bits 60:54) + .8byte 0x000000002000000F # for VA starting at 80E00000 (megapage not dirty or accessed) + .8byte 0x0000000000004CC1 # for VA starting at 81000000 (nonleaf pointing to unimplemented memory causes access fault) + .8byte 0x4000000020004CC1 # for VA starting at 81200000 (nonleaf with PBMT nonzero causes page fault) + .8byte 0x00000000000000CF # for VA starting at 81400000 (megapage with access fault) .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 @@ -262,7 +387,7 @@ pagetable: .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 -# Leaf page table at 0x80013000 with NAPOT pages +# Leaf page table at 0x80013000 with 64 KiB NAPOT pages .align 12 #80000000 .8byte 0xA0000000200020CF @@ -336,7 +461,8 @@ pagetable: # Leaf page table at 0x80014000 with PBMT pages .align 12 #80400000 - .8byte 0x60000000200020CF # reserved entry + .8byte 0x60000000200020CF # reserved entry VA 80400000 + .8byte 0x40000000201000CF # non-cache non-idempotent VA 80401000 # Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ .align 12 @@ -346,6 +472,7 @@ pagetable: .8byte 0x00000000200000C3 # valid r for VA 80802000 .8byte 0x00000000200000C9 # valid x for VA 80803000 .8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol) - .8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA + .8byte 0x00000000200000CF # valid rwx for VA 80805000 for covering ITLB translate .8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT + .8byte 0x000000002000000F # valid rwx for VA 80807000 for covering UpdateDA diff --git a/tests/coverage/vm64check.S b/tests/coverage/vm64check.S index 55c4db959..2e03a4e1a 100644 --- a/tests/coverage/vm64check.S +++ b/tests/coverage/vm64check.S @@ -6,6 +6,7 @@ // Purpose: vm64check coverage // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/custom/cacheSimTest/CacheSimTest.py b/tests/custom/cacheSimTest/CacheSimTest.py index 44cc00b06..e81b87d55 100755 --- a/tests/custom/cacheSimTest/CacheSimTest.py +++ b/tests/custom/cacheSimTest/CacheSimTest.py @@ -10,6 +10,7 @@ ## Purpose: Confirm that the cache simulator behaves as expected. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 4374ad07c..7bbcaf9e5 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -2,12 +2,12 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb + ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] misa: - reset-val: 0x800000000014112D + reset-val: 0x800000000015112D rv32: accessible: false rv64: diff --git a/tests/wally-riscv-arch-test/Makefile b/tests/wally-riscv-arch-test/Makefile deleted file mode 100644 index 168f03c3c..000000000 --- a/tests/wally-riscv-arch-test/Makefile +++ /dev/null @@ -1,123 +0,0 @@ -# -# Ensure the compiler and necessary executables are on the search PATH -# - -# -# Ensure you have set the following Variables -# -# -export ROOTDIR = $(shell pwd) -export WORK ?= $(ROOTDIR)/work - -include Makefile.include - -pipe:= | -empty:= -comma:= , -space:= $(empty) $(empty) - -RISCV_ISA_ALL = $(shell ls $(TARGETDIR)/$(RISCV_TARGET)/device/rv$(XLEN)i_m) -RISCV_ISA_OPT = $(subst $(space),$(pipe),$(RISCV_ISA_ALL)) - -RISCV_ISA_ALL := $(filter-out Makefile.include,$(RISCV_ISA_ALL)) - -ifeq ($(RISCV_DEVICE),) - RISCV_DEVICE = I - DEFAULT_TARGET=all_variant -else - DEFAULT_TARGET=variant -endif -export SUITEDIR = $(ROOTDIR)/riscv-test-suite/rv$(XLEN)i_m/$(RISCV_DEVICE) - -$(info ) -$(info ============================ VARIABLE INFO ==================================) -$(info ROOTDIR: ${ROOTDIR} [origin: $(origin ROOTDIR)]) -$(info WORK: ${WORK} [origin: $(origin WORK)]) -$(info TARGETDIR: ${TARGETDIR} [origin: $(origin TARGETDIR)]) -$(info RISCV_TARGET: ${RISCV_TARGET} [origin: $(origin RISCV_TARGET)]) -$(info XLEN: ${XLEN} [origin: $(origin XLEN)]) -$(info RISCV_DEVICE: ${RISCV_DEVICE} [origin: $(origin RISCV_DEVICE)]) -$(info =============================================================================) -$(info ) - -RVTEST_DEFINES = -ifeq ($(RISCV_ASSERT),1) - RVTEST_DEFINES += -DRVMODEL_ASSERT -endif -export RVTEST_DEFINES - -VERBOSE ?= 0 -ifeq ($(VERBOSE),1) - export V= - export REDIR1 = - export REDIR2 = -else - export V=@ - export REDIR1 = 1>/dev/null - export REDIR2 = 2>/dev/null -endif - -default: $(DEFAULT_TARGET) - -variant: compile simulate verify - -all_variant: - @for isa in $(RISCV_ISA_ALL); do \ - $(MAKE) $(JOBS) RISCV_TARGET=$(RISCV_TARGET) RISCV_TARGET_FLAGS="$(RISCV_TARGET_FLAGS)" RISCV_DEVICE=$$isa variant; \ - rc=$$?; \ - if [ $$rc -ne 0 ]; then \ - exit $$rc; \ - fi \ - done - -build: compile -run: simulate -clean_all: clean - -compile: - $(MAKE) $(JOBS) \ - RISCV_TARGET=$(RISCV_TARGET) \ - RISCV_DEVICE=$(RISCV_DEVICE) \ - compile -C $(SUITEDIR) - -simulate: - $(MAKE) $(JOBS) \ - RISCV_TARGET=$(RISCV_TARGET) \ - RISCV_DEVICE=$(RISCV_DEVICE) \ - run -C $(SUITEDIR) - -verify: simulate - riscv-test-env/verify.sh - -postverify: -ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),) - $(info No post verify script found $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh) -else - $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh -endif - -clean: - $(MAKE) $(JOBS) \ - RISCV_TARGET=$(RISCV_TARGET) \ - RISCV_DEVICE=$(RISCV_DEVICE) \ - clean -C $(SUITEDIR) - -help: - @echo "RISC-V Architectural Tests" - @echo "" - @echo " Makefile Environment Variables to be set per Target" - @echo " -- TARGETDIR=''" - @echo " -- XLEN=''" - @echo " -- RISCV_TARGET=''" - @echo " -- RISCV_TARGET_FLAGS=''" - @echo " -- RISCV_DEVICE='$(RISCV_ISA_OPT)' [ leave empty to run all devices ]" - @echo " -- RISCV_TEST='>>>>>>>>>>>>>>>>>>>>>>>>>>>) - $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) - $(V) echo "Copying References without simulating for the following tests: $(target_tests_nosim)" - $(V) for test in $(target_tests_nosim); do grep -o '^[^#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done - -compile: $(combined_elf) -run: $(target_log) -# note that run doesnt use the combined elf so it doesnt run the nosim tests. - -#------------------------------------------------------------ -# Clean up - -clean: - rm -rf $(work_dir) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefile deleted file mode 100644 index d8449d851..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv32ic -mabi=ilp32 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefrag deleted file mode 100644 index 79d1bd169..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefrag +++ /dev/null @@ -1,34 +0,0 @@ -# RISC-V Architecture Test RV32I Makefrag -# -# Copyright (c) 2017, Codasip Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV32I architectural tests - -rv32i_sc_tests = \ - -rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) - -target_tests += $(rv32i_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefile deleted file mode 100644 index 4079d3013..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv32if -mabi=ilp32 -DXLEN=$(XLEN) -DFLEN=32)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefrag deleted file mode 100644 index 253e9e0d3..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefrag +++ /dev/null @@ -1,14 +0,0 @@ -# RISC-V Architecture Test RV32IF Makefrag -# -# Copyright (c) 2021. IIT Madras. All rights reserved. -# SPDX-License-Identifier: BSD-3-Clause -# -# Description: Makefrag for RV32IF architectural tests - -rv32if_sc_tests = \ - - - -rv32if_tests = $(addsuffix .elf, $(rv32if_sc_tests)) - -target_tests += $(rv32if_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefile deleted file mode 100644 index 74d788175..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag deleted file mode 100644 index 792ea2e24..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag +++ /dev/null @@ -1,76 +0,0 @@ -# RISC-V Architecture Test RV32I Makefrag -# -# Copyright (c) 2017, Codasip Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV32I architectural tests - -rv32i_sc_tests = \ - E-add-01 \ - E-addi-01 \ - E-and-01 \ - E-andi-01 \ - E-auipc-01 \ - E-beq-01 \ - E-bge-01 \ - E-bgeu-01 \ - E-blt-01 \ - E-bltu-01 \ - E-bne-01 \ - E-jal-01 \ - E-jalr-01 \ - E-lb-align-01 \ - E-lbu-align-01 \ - E-lh-align-01 \ - E-lhu-align-01 \ - E-lui-01 \ - E-lw-align-01 \ - E-or-01 \ - E-ori-01 \ - E-sb-align-01 \ - E-sh-align-01 \ - E-sll-01 \ - E-slli-01 \ - E-slt-01 \ - E-slti-01 \ - E-sltiu-01 \ - E-sltu-01 \ - E-sra-01 \ - E-srai-01 \ - E-srl-01 \ - E-srli-01 \ - E-sub-01 \ - E-sw-align-01 \ - E-xor-01 \ - E-xori-01 \ - WALLY-ADD \ - WALLY-SLT \ - WALLY-SLTU \ - WALLY-SUB \ - WALLY-XOR - -rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) - -target_tests += $(rv32i_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefile deleted file mode 100644 index 17df4991f..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv32im -mabi=ilp32 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefrag deleted file mode 100644 index 1426cad31..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefrag +++ /dev/null @@ -1,35 +0,0 @@ -# RISC-V Architecture Test RV32IM Makefrag -# -# Copyright (c) 2018, Imperas Software Ltd. -# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Imperas Software Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV32IM architectural tests - -rv32im_sc_tests = \ - -rv32im_tests = $(addsuffix .elf, $(rv32im_sc_tests)) - -target_tests += $(rv32im_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile deleted file mode 100644 index 0c60cf417..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -include ../../Makefile.include - -RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests - -$(eval $(call compile_template,-march=rv32iaf -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag deleted file mode 100644 index 67f7c2f93..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ /dev/null @@ -1,66 +0,0 @@ -# RISC-V Architecture Test RV32I Makefrag -# -# Copyright (c) 2017, Codasip Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV32I architectural tests - -rv32i_sc_tests = \ - WALLY-mmu-sv32 \ - WALLY-pm-01 \ - WALLY-csr-permission-s-01 \ - WALLY-csr-permission-u-01 \ - WALLY-misa-01 \ - WALLY-lrsc-01 \ - WALLY-status-mie-01 \ - WALLY-trap-sret-01 \ - - -target_tests_nosim = \ - WALLY-pma-01 \ - WALLY-minfo-01 \ - WALLY-mtvec-01 \ - WALLY-stvec-01 \ - WALLY-mie-01 \ - WALLY-sie-01 \ - WALLY-trap-01 \ - WALLY-trap-s-01 \ - WALLY-trap-u-01 \ - WALLY-wfi-01 \ - WALLY-status-fp-enabled-01 \ - WALLY-status-sie-01 \ - WALLY-status-tw-01 \ - WALLY-gpio-01 \ - WALLY-clint-01 \ - WALLY-plic-01 \ - WALLY-uart-01 \ - WALLY-spi-01 \ - WALLY-cbom-01 \ - WALLY-cboz-01 \ - - -rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) - -target_tests += $(rv32i_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output index f0468cead..53a480fec 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output @@ -1,3 +1,3 @@ 0000000b # Test *** Number: Ecall from going from M mode to S mode -00000002 # illegal instruction from truining on virtual memory with invalid satp address +00000001 # Instruction access fault (was illegal instruction) from turning on virtual memory with invalid satp address 00000009 # ecall from ending tests in S mode. \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S index 84191b25d..7194b59a4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-32.h" RVTEST_ISA("RV32I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-s) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-s) INIT_TESTS @@ -195,4 +195,4 @@ WRITE_READ_CSR mhpmevent31, 0x111 END_TESTS -TEST_STACK_AND_DATA \ No newline at end of file +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S index 382f0d642..0835c8c1b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-32.h" RVTEST_ISA("RV32I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-u) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-u) INIT_TESTS @@ -174,4 +174,4 @@ WRITE_READ_CSR mhpmevent31, 0xAAA END_TESTS -TEST_STACK_AND_DATA \ No newline at end of file +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S index 06e419eb2..b5d8f271a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-32.h" RVTEST_ISA("RV32I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",misa) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",misa) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S index 3f43f9950..d18fbd76e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-32.h" RVTEST_ISA("RV32I_Zicsr_Zifencei") -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",mmu) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mmu) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S index 1c7d0edb0..246d6e96d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-32.h" RVTEST_ISA("RV32I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;def NO_SAIL=True;",satp-invalid) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S index 75afdb0b8..67e11bc31 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-32.h" RVTEST_ISA("RV32IAF_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",status-fp-enabled) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled) INIT_TESTS @@ -77,4 +77,4 @@ fmv.s ft0, ft0 // should be an illegal instruction with fs set to 00 END_TESTS -TEST_STACK_AND_DATA \ No newline at end of file +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S index bb3c1d738..20f74d660 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-32.h" RVTEST_ISA("RV32I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",status-mie) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-mie) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S index 8f323c1c2..224420cb3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S @@ -25,7 +25,7 @@ #include "WALLY-TEST-LIB-32.h" RVTEST_ISA("RV32I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;", status-tvm) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;", status-tvm) INIT_TESTS @@ -42,4 +42,4 @@ sfence.vma x0, x0 // attempt to call sfence should cause illegal instruction wit END_TESTS -TEST_STACK_AND_DATA \ No newline at end of file +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefile deleted file mode 100644 index 38d7cba9d..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv64ic -mabi=lp64 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefrag deleted file mode 100644 index d7032fc71..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefrag +++ /dev/null @@ -1,35 +0,0 @@ -# RISC-V Architecture Test RV64I Makefrag -# -# Copyright (c) 2017, Codasip Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV64I architectural tests - -rv64i_sc_tests = \ - - -rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) - -target_tests += $(rv64i_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile deleted file mode 100644 index a474441d6..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv64id -mabi=lp64 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag deleted file mode 100644 index 261a9a852..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag +++ /dev/null @@ -1,35 +0,0 @@ -# RISC-V Architecture Test RV64IM Makefrag -# -# Copyright (c) 2018, Imperas Software Ltd. -# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Imperas Software Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV64IM architectural tests - -rv64im_sc_tests = \ - -rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests)) - -target_tests += $(rv64im_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefile deleted file mode 100644 index 18dc245c8..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv64i -mabi=lp64 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag deleted file mode 100644 index 19bb5bd01..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag +++ /dev/null @@ -1,40 +0,0 @@ -# RISC-V Architecture Test RV64I Makefrag -# -# Copyright (c) 2017, Codasip Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV64I architectural tests - -rv64i_sc_tests = \ - WALLY-ADD \ - WALLY-SUB \ - WALLY-SLT \ - WALLY-SLTU \ - WALLY-XOR \ - - -rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) - -target_tests += $(rv64i_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefile deleted file mode 100644 index f767da3a4..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv64im -mabi=lp64 -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefrag deleted file mode 100644 index 261a9a852..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefrag +++ /dev/null @@ -1,35 +0,0 @@ -# RISC-V Architecture Test RV64IM Makefrag -# -# Copyright (c) 2018, Imperas Software Ltd. -# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Imperas Software Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV64IM architectural tests - -rv64im_sc_tests = \ - -rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests)) - -target_tests += $(rv64im_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output new file mode 100644 index 000000000..6f8523bbf --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output @@ -0,0 +1,36 @@ +00000000 # fsq of 1 +00000000 +00000000 +3fff0000 +dead4000 # fsh of 1 +deadbeef +deadbeef +deadbeef +00000000 # fsq of 3 +00000000 +00000000 +40008000 +00000000 # fsq of -1 +00000000 +00000000 +bfff0000 +00000000 # fsq of 6 +00000000 +00000000 +40018000 +00000000 # fsq of -4 +00000000 +00000000 +C0010000 +00000000 # fsq of -2 +00000000 +00000000 +C0000000 +00000000 # fsq of 4 +00000000 +00000000 +40010000 +00000000 # fsq of 2 +00000000 +00000000 +40000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S new file mode 100644 index 000000000..ea8bd15d5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S @@ -0,0 +1,154 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S +// David_Harris@hmc.edu & Rose Thompson +// Created 07 March 2024 +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDQZfh_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*Q.*);def TEST_CASE_1=True;def NO_SAIL=True",flq-align) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +#endif + +# turn on the floating point unit +li x7, 1 +slli x7, x7, 13 +csrw mstatus, x7 + +li x4, 1 # 3fff 0000 0000 0000 0000 0000 0000 0000 +li x2, 2 # 4000 0000 0000 0000 0000 0000 0000 0000 +fcvt.q.w f2, x2 +fcvt.q.w f4, x4 + +fcvt.h.w f5, x2 # 4000 + +# test quad load/store +fsq f4, 0(x3) +flq f7, 0(x3) +fsq f7, 0(x1) + +# test half load/store +fsh f5, 16(x3) +flh f6, 16(x3) +fsh f6, 16(x1) + +# 1 + 2 = 3 # 4000 8000 0000 0000 0000 0000 0000 0000 +fadd.q f8, f2, f4 +fsq f8, 32(x1) + +# 1 - 2 = -1 +fsub.q f9, f4, f2 # bfff 0000000000000000000000000000 +fsq f9, 48(x1) + +# 2 * 3 = 6 +fmul.q f10, f2, f8 # 4001 8000000000000000000000000000 +fsq f10, 64(x1) + +# 6 * (-1) + 2 = -4 +fmadd.q f11, f10, f9, f2 # C001 0000000000000000000000000000 +fsq f11, 80(x1) + +# -4 / 2 = -2 +fdiv.q f12, f11, f2 # C000 0000000000000000000000000000 +fsq f12, 96(x1) + +# sign injection (-4, 1) = 4 +fsgnj.q f13, f11, f4 # 4001 0000000000000000000000000000 +fsq f13, 112(x1) + +# sqrt(4) = 2 +fsqrt.q f14, f13 # 4000 0000000000000000000000000000 +fsq f14, 128(x1) + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +test_dataset_0: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_1: +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: + + + + +signature_x1_1: + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile deleted file mode 100644 index 7404f07c1..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -include ../../Makefile.include - -RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests - -$(eval $(call compile_template,-march=rv64iaf -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag deleted file mode 100644 index a640e0c06..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ /dev/null @@ -1,73 +0,0 @@ -# RISC-V Architecture Test RV64I Makefrag -# -# Copyright (c) 2017, Codasip Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV64I architectural tests - -rv64i_sc_tests = \ - WALLY-mmu-sv39-01 \ - WALLY-mmu-sv48-01 \ - WALLY-pmp-01 \ - WALLY-csr-permission-s-01 \ - WALLY-csr-permission-u-01 \ - WALLY-misa-01 \ - WALLY-lrsc-01 \ - WALLY-trap-sret-01 \ - WALLY-status-mie-01 \ - WALLY-status-sie-01 \ - WALLY-status-tw-01 \ - - -# Don't simulate these because they rely on SoC features that Spike does not offer. -target_tests_nosim = \ - WALLY-pma-01 \ - WALLY-minfo-01 \ - WALLY-periph-01 \ - WALLY-mtvec-01 \ - WALLY-stvec-01 \ - WALLY-mie-01 \ - WALLY-sie-01 \ - WALLY-trap-01 \ - WALLY-trap-s-01 \ - WALLY-trap-u-01 \ - WALLY-status-fp-enabled-01 \ - WALLY-spi-01 \ - WALLY-gpio-01 \ - WALLY-uart-01 \ - WALLY-wfi-01 \ - WALLY-cbom-01 \ - WALLY-cboz-01 \ - WALLY-misaligned-access-01 \ - - -# unclear why status-fp-enabled and wfi aren't simulating ok -# DH 10/9/23: minfo needs Privileged Spec 1.12 for the mconfigptr register, but -# we don't have the right ISA string so it's compiling at 1.11 -# and Sail throws an illegal instruction exception on csrr mconfigptr - -rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) - -target_tests += $(rv64i_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output index e6728f2e0..8ad794f1d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output @@ -1,6 +1,6 @@ 0000000b # Test *** Number: Ecall from going from M mode to S mode 00000000 -00000002 # illegal instruction from truining on virtual memory with invalid satp address +00000001 # Instruction access fault from turning on virtual memory with invalid satp address 00000000 00000009 # ecall from ending tests in S mode. 00000000 \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S index 615163250..410dd78ea 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-s) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-s) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S index bb7cc8379..b03d44a92 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-u) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-u) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S index 543df7cbf..fbbc4d18e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",misa) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",misa) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S index d9ef62141..0690b1282 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr_Zifencei") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",mmu-sv39) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",mmu-sv39) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S index 2fbdf48ca..c086c934f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr_Zifencei") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",mmu-sv39) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",mmu-sv39) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S index b6161fb8b..f84e68109 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr_Zifencei") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sv48) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",sv48) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S index a711e4729..01b3736bc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;def NO_SAIL=True;",satp-invalid) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S index 7ce55f79a..c2ad3ef11 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64IAF_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;",status-fp-enabled) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S index 2d24f92b4..0b90a59ae 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S @@ -23,7 +23,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",status-mie) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-mie) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S index efef21093..0eca80ebb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S @@ -25,7 +25,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;", status-tvm) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;", status-tvm) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S index 1fba96a74..96bf81f8b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S @@ -24,7 +24,7 @@ #include "WALLY-TEST-LIB-64.h" RVTEST_ISA("RV64I_Zicsr") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xlen) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",xlen) INIT_TESTS