VCU108 is not synthesizing at 50MHz. Still running into a few problems

with the new SPI sd card device.

fpga/constraints/marked_debug.txt

@@ -3,8 +3,5 @@ wally/wallypipelinedcore.sv: logic    TrapM
 wally/wallypipelinedcore.sv: logic                InstrValidM
 wally/wallypipelinedcore.sv: logic                 InstrM
 lsu/lsu.sv: logic        IEUAdrM
-lsu/lsu.sv: logic        PAdrM
-lsu/lsu.sv: logic        ReadDataM
-lsu/lsu.sv: logic        WriteDataM
 lsu/lsu.sv: logic       MemRWM
-privileged/csrc.sv: logic      HPMCOUNTER_REGW
+mmu/hptw.sv: logic	   SATP_REGW

fpga/constraints/vcu-small-debug.xdc

@@ -1,6 +1,6 @@
 create_debug_core u_ila_0 ila
 
-set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
 set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
 set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
 set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]

fpga/src/fpgaTop.sv

@@ -48,7 +48,6 @@ module fpgaTop
    input         SDCCD,
    input         SDCWP,         
 
-   output          calib,
    output          cpu_reset,
    output          ahblite_resetn,
 
@@ -188,7 +187,6 @@ module fpgaTop
   assign GPO = GPIOOUT[4:0];
   assign ahblite_resetn = peripheral_aresetn;
   assign cpu_reset = bus_struct_reset;
-  assign calib = c0_init_calib_complete;
   
   logic [3:0] SDCCSin;
   assign SDCCS = SDCCSin[0];