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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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bbracker 2021-06-24 01:42:41 -04:00
commit 13df69abdb
8 changed files with 135 additions and 176 deletions
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32
wally-pipelined/src/cache/ICacheCntrl.sv vendored
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@ -33,15 +33,15 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
// Input the address to read // Input the address to read
// The upper bits of the physical pc // The upper bits of the physical pc
input logic [`XLEN-1:0] PCNextF, input logic [`PA_BITS-1:0] PCNextF,
input logic [`XLEN-1:0] PCPF, input logic [`PA_BITS-1:0] PCPF,
// Signals to/from cache memory // Signals to/from cache memory
// The read coming out of it // The read coming out of it
input logic [31:0] ICacheMemReadData, input logic [31:0] ICacheMemReadData,
input logic ICacheMemReadValid, input logic ICacheMemReadValid,
// The address at which we want to search the cache memory // The address at which we want to search the cache memory
output logic [`XLEN-1:0] PCTagF, output logic [`PA_BITS-1:0] PCTagF,
output logic [`XLEN-1:0] PCNextIndexF, output logic [`PA_BITS-1:0] PCNextIndexF,
output logic ICacheReadEn, output logic ICacheReadEn,
// Load data into the cache // Load data into the cache
output logic ICacheMemWriteEnable, output logic ICacheMemWriteEnable,
@ -52,7 +52,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
output logic CompressedF, output logic CompressedF,
// The instruction that was requested // The instruction that was requested
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
output logic [31:0] InstrRawD, output logic [31:0] FinalInstrRawF,
// Outputs to pipeline control stuff // Outputs to pipeline control stuff
output logic ICacheStallF, EndFetchState, output logic ICacheStallF, EndFetchState,
@ -62,7 +62,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
input logic [`XLEN-1:0] InstrInF, input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF, input logic InstrAckF,
// The read we request from main memory // The read we request from main memory
output logic [`XLEN-1:0] InstrPAdrF, output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF output logic InstrReadF
); );
@ -119,6 +119,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
localparam WORDSPERLINE = BLOCKLEN/`XLEN; localparam WORDSPERLINE = BLOCKLEN/`XLEN;
localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGWPL = $clog2(WORDSPERLINE);
localparam integer PA_WIDTH = `PA_BITS - 2;
logic [4:0] CurrState, NextState; logic [4:0] CurrState, NextState;
logic hit, spill; logic hit, spill;
@ -133,12 +135,10 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
logic [LOGWPL:0] FetchCount, NextFetchCount; logic [LOGWPL:0] FetchCount, NextFetchCount;
logic [`XLEN-1:0] PCPreFinalF, PCPFinalF, PCSpillF; logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF;
logic [`XLEN-1:OFFSETWIDTH] PCPTrunkF; logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF;
logic [31:0] FinalInstrRawF;
logic [15:0] SpillDataBlock0; logic [15:0] SpillDataBlock0;
localparam [31:0] NOP = 32'h13; localparam [31:0] NOP = 32'h13;
@ -156,11 +156,11 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
// on spill we want to get the first 2 bytes of the next cache block. // on spill we want to get the first 2 bytes of the next cache block.
// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can // the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
// simply add 2 to land on the next cache block. // simply add 2 to land on the next cache block.
assign PCSpillF = PCPF + `XLEN'b10; assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width.
// now we have to select between these three PCs // now we have to select between these three PCs
assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF; assign PCNextIndexF = PCMux[1] ? PCPSpillF : PCPreFinalF;
// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later. // this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
// *** read enable may not be necessary. // *** read enable may not be necessary.
@ -170,11 +170,10 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
.d(PCMux), .d(PCMux),
.q(PCMux_q)); .q(PCMux_q));
assign PCTagF = PCMux_q[1] ? PCSpillF : PCPF; assign PCTagF = PCMux_q[1] ? PCPSpillF : PCPF;
assign PCNextIndexF = PCPFinalF;
// truncate the offset from PCPF for memory address generation // truncate the offset from PCPF for memory address generation
assign PCPTrunkF = PCTagF[`XLEN-1:OFFSETWIDTH]; assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH];
// Detect if the instruction is compressed // Detect if the instruction is compressed
assign CompressedF = FinalInstrRawF[1:0] != 2'b11; assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
@ -395,7 +394,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
// we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros. // we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros.
// fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with // fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with
// more zeros after the addition. This will be the number of offset bits less the AHBByteLength. // more zeros after the addition. This will be the number of offset bits less the AHBByteLength.
logic [`XLEN-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ; logic [`PA_BITS-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ;
assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}}; assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}};
// verilator lint_off WIDTH // verilator lint_off WIDTH
@ -454,6 +453,5 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
.d(reset), .d(reset),
.q(reset_q)); .q(reset_q));
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? NOP : FinalInstrRawF, NOP, InstrRawD);
endmodule endmodule

10
wally-pipelined/src/cache/ICacheMem.sv vendored
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@ -8,8 +8,8 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
// If flush is high, invalidate the entire cache // If flush is high, invalidate the entire cache
input logic flush, input logic flush,
input logic [`XLEN-1:0] PCTagF, // physical address input logic [`PA_BITS-1:0] PCTagF, // physical address
input logic [`XLEN-1:0] PCNextIndexF, // virtual address input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address
input logic WriteEnable, input logic WriteEnable,
input logic [BLOCKLEN-1:0] WriteLine, input logic [BLOCKLEN-1:0] WriteLine,
output logic [BLOCKLEN-1:0] ReadLineF, output logic [BLOCKLEN-1:0] ReadLineF,
@ -21,7 +21,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
localparam OFFSETLEN = $clog2(BLOCKBYTELEN); localparam OFFSETLEN = $clog2(BLOCKBYTELEN);
localparam INDEXLEN = $clog2(NUMLINES); localparam INDEXLEN = $clog2(NUMLINES);
// *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48 // *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48
localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN; localparam TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
logic [TAGLEN-1:0] LookupTag; logic [TAGLEN-1:0] LookupTag;
logic [NUMLINES-1:0] ValidOut; logic [NUMLINES-1:0] ValidOut;
@ -39,7 +39,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
cachetags (.*, cachetags (.*,
.Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.ReadData(LookupTag), .ReadData(LookupTag),
.WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]) .WriteData(PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN])
); );
// Correctly handle the valid bits // Correctly handle the valid bits
@ -55,5 +55,5 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
end end
DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]]; DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]];
end end
assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]); assign HitF = DataValidBit && (LookupTag == PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]);
endmodule endmodule

10
wally-pipelined/src/cache/icache.sv vendored
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@ -31,13 +31,13 @@ module icache
input logic clk, reset, input logic clk, reset,
input logic StallF, StallD, input logic StallF, StallD,
input logic FlushD, input logic FlushD,
input logic [`XLEN-1:0] PCNextF, input logic [`PA_BITS-1:0] PCNextF,
input logic [`XLEN-1:0] PCPF, input logic [`PA_BITS-1:0] PCPF,
// Data read in from the ebu unit // Data read in from the ebu unit
input logic [`XLEN-1:0] InstrInF, input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF, input logic InstrAckF,
// Read requested from the ebu unit // Read requested from the ebu unit
output logic [`XLEN-1:0] InstrPAdrF, output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF, output logic InstrReadF,
// High if the instruction currently in the fetch stage is compressed // High if the instruction currently in the fetch stage is compressed
output logic CompressedF, output logic CompressedF,
@ -45,7 +45,7 @@ module icache
output logic ICacheStallF, output logic ICacheStallF,
// The raw (not decompressed) instruction that was requested // The raw (not decompressed) instruction that was requested
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
output logic [31:0] InstrRawD output logic [31:0] FinalInstrRawF
); );
// Configuration parameters // Configuration parameters
@ -58,7 +58,7 @@ module icache
logic ICacheMemWriteEnable; logic ICacheMemWriteEnable;
logic [BLOCKLEN-1:0] ICacheMemWriteData; logic [BLOCKLEN-1:0] ICacheMemWriteData;
logic EndFetchState; logic EndFetchState;
logic [`XLEN-1:0] PCTagF, PCNextIndexF; logic [`PA_BITS-1:0] PCTagF, PCNextIndexF;
// Output signals from cache memory // Output signals from cache memory
logic [31:0] ICacheMemReadData; logic [31:0] ICacheMemReadData;
logic ICacheMemReadValid; logic ICacheMemReadValid;

2
wally-pipelined/src/ebu/ahblite.sv
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@ -42,7 +42,7 @@ module ahblite (
input logic [1:0] AtomicMaskedM, input logic [1:0] AtomicMaskedM,
input logic [6:0] Funct7M, input logic [6:0] Funct7M,
// Signals from Instruction Cache // Signals from Instruction Cache
input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram
input logic InstrReadF, input logic InstrReadF,
output logic [`XLEN-1:0] InstrRData, output logic [`XLEN-1:0] InstrRData,
output logic InstrAckF, output logic InstrAckF,

227
wally-pipelined/src/fpu/fpu.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// //
// Written: // Written: Katherine Parry, Bret Mathis
// Modified: // Modified: 6/23/2021
// //
// Purpose: FPU // Purpose: FPU
// //
@ -25,23 +25,23 @@
`include "wally-config.vh" `include "wally-config.vh"
module fpu ( module fpu (
input logic [2:0] FRM_REGW, // Rounding mode from CSR
input logic reset,
input logic clk, input logic clk,
input logic reset,
input logic [2:0] FRM_REGW, // Rounding mode from CSR
input logic [31:0] InstrD, input logic [31:0] InstrD,
input logic [`XLEN-1:0] ReadDataW, // Read data from memory
input logic RegWriteD, // register write enable from ieu
input logic [`XLEN-1:0] SrcAE, // Integer input being processed input logic [`XLEN-1:0] SrcAE, // Integer input being processed
input logic [`XLEN-1:0] SrcAM, // Integer input being written into fpreg input logic [`XLEN-1:0] SrcAM, // Integer input being written into fpreg
input logic StallE, StallM, StallW, input logic StallE, StallM, StallW,
input logic FlushE, FlushM, FlushW, input logic FlushE, FlushM, FlushW,
input logic [`XLEN-1:0] ReadDataW, // Read data from memory
input logic RegWriteD, // register write enable from ieu
output logic [4:0] SetFflagsM, // FPU flags
output logic [1:0] FMemRWM, // Read/write enable for memory {read, write} output logic [1:0] FMemRWM, // Read/write enable for memory {read, write}
output logic FStallD, // Stall the decode stage if Div/Sqrt instruction output logic FStallD, // Stall the decode stage if Div/Sqrt instruction
output logic FWriteIntE, FWriteIntM, FWriteIntW, // Write integer register enable output logic FWriteIntE, FWriteIntM, FWriteIntW, // Write integer register enable
output logic [`XLEN-1:0] FWriteDataM, // Data to be written to memory output logic [`XLEN-1:0] FWriteDataM, // Data to be written to memory
output logic FDivBusyE, // Is the divison/sqrt unit busy output logic FDivBusyE, // Is the divison/sqrt unit busy
output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
output logic [4:0] SetFflagsM, // FPU flags
output logic [`XLEN-1:0] FPUResultW); // FPU result output logic [`XLEN-1:0] FPUResultW); // FPU result
// control logic signal instantiation // control logic signal instantiation
@ -58,10 +58,10 @@ module fpu (
logic FInput2UsedD; // Is input 2 used logic FInput2UsedD; // Is input 2 used
logic FInput3UsedD; // Is input 3 used logic FInput3UsedD; // Is input 3 used
logic [2:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select FP result logic [2:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select FP result
logic [3:0] FOpCtrlD, FOpCtrlE, FOpCtrlM, FOpCtrlW; // Select which opperation to do in each component logic [3:0] FOpCtrlD, FOpCtrlE, FOpCtrlM, FOpCtrlW; // Select which opperation to do in each component
logic SelLoadInputE, SelLoadInputM; // Select which adress to load when single precision logic SelLoadInputE, SelLoadInputM; // Select which adress to load when single precision
// regfile signals //*** KEP lint warning - changed `XLEN-1 to 63 // regfile signals
logic [4:0] RdE, RdM, RdW; // what adress to write to // ***Can take from ieu insted of pipelining logic [4:0] RdE, RdM, RdW; // what adress to write to // ***Can take from ieu insted of pipelining
logic [63:0] FWDM; // Write data for FP register logic [63:0] FWDM; // Write data for FP register
logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
@ -147,26 +147,6 @@ module fpu (
logic [63:0] FPUResult64W, FPUResult64E; logic [63:0] FPUResult64W, FPUResult64E;
logic [4:0] FPUFlagsW; logic [4:0] FPUFlagsW;
// pipeline control logic
logic PipeEnableDE;
logic PipeEnableEM;
logic PipeEnableMW;
logic PipeClearDE;
logic PipeClearEM;
logic PipeClearMW;
// temporarily assign pipe clear and enable signals
// to never flush & always be running
localparam PipeClear = 1'b0;
localparam PipeEnable = 1'b1;
always_comb begin
PipeEnableDE = ~StallE;
PipeEnableEM = ~StallM;
PipeEnableMW = ~StallW;
PipeClearDE = FlushE;
PipeClearEM = FlushM;
PipeClearMW = FlushW;
end
//DECODE STAGE //DECODE STAGE
@ -185,28 +165,17 @@ module fpu (
//***************** //*****************
// fpregfile D/E pipe registers // fpregfile D/E pipe registers
//***************** //*****************
flopenrc #(64) DEReg1(clk, reset, PipeClearDE, PipeEnableDE, FRD1D, FRD1E); flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
flopenrc #(64) DEReg2(clk, reset, PipeClearDE, PipeEnableDE, FRD2D, FRD2E); flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
flopenrc #(64) DEReg3(clk, reset, PipeClearDE, PipeEnableDE, FRD3D, FRD3E); flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
//***************** //*****************
// other D/E pipe registers // other D/E pipe registers
//***************** //*****************
flopenrc #(1) DEReg4(clk, reset, PipeClearDE, PipeEnableDE, FWriteEnD, FWriteEnE); flopenrc #(64) DEReg14(clk, reset, FlushE, ~StallE, FPUResult64W, FPUResult64E);
flopenrc #(3) DEReg5(clk, reset, PipeClearDE, PipeEnableDE, FResultSelD, FResultSelE); flopenrc #(28) CtrlRegE(clk, reset, FlushE, ~StallE,
flopenrc #(3) DEReg6(clk, reset, PipeClearDE, PipeEnableDE, FrmD, FrmE); {FWriteEnD, FResultSelD, FrmD, FmtD, InstrD[11:7], FOpCtrlD, FDivStartD, FForwardInput1D, FForwardInput2D, FForwardInput3D, FWriteIntD, FOutputInput2D, FMemRWD, InstrD[15]},
flopenrc #(1) DEReg7(clk, reset, PipeClearDE, PipeEnableDE, FmtD, FmtE); {FWriteEnE, FResultSelE, FrmE, FmtE, RdE, FOpCtrlE, FDivStartE, FForwardInput1E, FForwardInput2E, FForwardInput3E, FWriteIntE, FOutputInput2E, FMemRWE, SelLoadInputE});
flopenrc #(5) DEReg8(clk, reset, PipeClearDE, PipeEnableDE, InstrD[11:7], RdE);
flopenrc #(4) DEReg9(clk, reset, PipeClearDE, PipeEnableDE, FOpCtrlD, FOpCtrlE);
flopenrc #(1) DEReg10(clk, reset, PipeClearDE, PipeEnableDE, FDivStartD, FDivStartE);
flopenrc #(2) DEReg11(clk, reset, PipeClearDE, PipeEnableDE, FForwardInput1D, FForwardInput1E);
flopenrc #(2) DEReg12(clk, reset, PipeClearDE, PipeEnableDE, FForwardInput2D, FForwardInput2E);
flopenrc #(1) DEReg13(clk, reset, PipeClearDE, PipeEnableDE, FForwardInput3D, FForwardInput3E);
flopenrc #(64) DEReg14(clk, reset, PipeClearDE, PipeEnableDE, FPUResult64W, FPUResult64E);
flopenrc #(1) DEReg15(clk, reset, PipeClearDE, PipeEnableDE, FWriteIntD, FWriteIntE);
flopenrc #(1) DEReg16(clk, reset, PipeClearDE, PipeEnableDE, FOutputInput2D, FOutputInput2E);
flopenrc #(2) DEReg17(clk, reset, PipeClearDE, PipeEnableDE, FMemRWD, FMemRWE);
flopenrc #(1) DEReg18(clk, reset, PipeClearDE, PipeEnableDE, InstrD[15], SelLoadInputE);
//EXECUTION STAGE //EXECUTION STAGE
@ -253,91 +222,91 @@ module fpu (
//***************** //*****************
//fpregfile D/E pipe registers //fpregfile D/E pipe registers
//***************** //*****************
flopenrc #(64) EMFpReg1(clk, reset, PipeClearEM, PipeEnableEM, FInput1E, FInput1M); flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FInput1E, FInput1M);
flopenrc #(64) EMFpReg2(clk, reset, PipeClearEM, PipeEnableEM, FInput2E, FInput2M); flopenrc #(64) EMFpReg2(clk, reset, FlushM, ~StallM, FInput2E, FInput2M);
flopenrc #(64) EMFpReg3(clk, reset, PipeClearEM, PipeEnableEM, FInput3E, FInput3M); flopenrc #(64) EMFpReg3(clk, reset, FlushM, ~StallM, FInput3E, FInput3M);
//***************** //*****************
// fma E/M pipe registers // fma E/M pipe registers
//***************** //*****************
flopenrc #(106) EMRegFma3(clk, reset, PipeClearEM, PipeEnableEM, ProdManE, ProdManM); flopenrc #(106) EMRegFma3(clk, reset, FlushM, ~StallM, ProdManE, ProdManM);
flopenrc #(162) EMRegFma4(clk, reset, PipeClearEM, PipeEnableEM, AlignedAddendE, AlignedAddendM); flopenrc #(162) EMRegFma4(clk, reset, FlushM, ~StallM, AlignedAddendE, AlignedAddendM);
flopenrc #(13) EMRegFma6(clk, reset, PipeClearEM, PipeEnableEM, ProdExpE, ProdExpM); flopenrc #(13) EMRegFma6(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM);
flopenrc #(1) EMRegFma7(clk, reset, PipeClearEM, PipeEnableEM, AddendStickyE, AddendStickyM); flopenrc #(1) EMRegFma7(clk, reset, FlushM, ~StallM, AddendStickyE, AddendStickyM);
flopenrc #(1) EMRegFma8(clk, reset, PipeClearEM, PipeEnableEM, KillProdE, KillProdM); flopenrc #(1) EMRegFma8(clk, reset, FlushM, ~StallM, KillProdE, KillProdM);
flopenrc #(1) EMRegFma10(clk, reset, PipeClearEM, PipeEnableEM, XZeroE, XZeroM); flopenrc #(1) EMRegFma10(clk, reset, FlushM, ~StallM, XZeroE, XZeroM);
flopenrc #(1) EMRegFma11(clk, reset, PipeClearEM, PipeEnableEM, YZeroE, YZeroM); flopenrc #(1) EMRegFma11(clk, reset, FlushM, ~StallM, YZeroE, YZeroM);
flopenrc #(1) EMRegFma12(clk, reset, PipeClearEM, PipeEnableEM, ZZeroE, ZZeroM); flopenrc #(1) EMRegFma12(clk, reset, FlushM, ~StallM, ZZeroE, ZZeroM);
flopenrc #(1) EMRegFma16(clk, reset, PipeClearEM, PipeEnableEM, XInfE, XInfM); flopenrc #(1) EMRegFma16(clk, reset, FlushM, ~StallM, XInfE, XInfM);
flopenrc #(1) EMRegFma17(clk, reset, PipeClearEM, PipeEnableEM, YInfE, YInfM); flopenrc #(1) EMRegFma17(clk, reset, FlushM, ~StallM, YInfE, YInfM);
flopenrc #(1) EMRegFma18(clk, reset, PipeClearEM, PipeEnableEM, ZInfE, ZInfM); flopenrc #(1) EMRegFma18(clk, reset, FlushM, ~StallM, ZInfE, ZInfM);
flopenrc #(1) EMRegFma19(clk, reset, PipeClearEM, PipeEnableEM, XNaNE, XNaNM); flopenrc #(1) EMRegFma19(clk, reset, FlushM, ~StallM, XNaNE, XNaNM);
flopenrc #(1) EMRegFma20(clk, reset, PipeClearEM, PipeEnableEM, YNaNE, YNaNM); flopenrc #(1) EMRegFma20(clk, reset, FlushM, ~StallM, YNaNE, YNaNM);
flopenrc #(1) EMRegFma21(clk, reset, PipeClearEM, PipeEnableEM, ZNaNE, ZNaNM); flopenrc #(1) EMRegFma21(clk, reset, FlushM, ~StallM, ZNaNE, ZNaNM);
//***************** //*****************
// fpadd E/M pipe registers // fpadd E/M pipe registers
//***************** //*****************
flopenrc #(64) EMRegAdd1(clk, reset, PipeClearEM, PipeEnableEM, AddSumE, AddSumM); flopenrc #(64) EMRegAdd1(clk, reset, FlushM, ~StallM, AddSumE, AddSumM);
flopenrc #(64) EMRegAdd2(clk, reset, PipeClearEM, PipeEnableEM, AddSumTcE, AddSumTcM); flopenrc #(64) EMRegAdd2(clk, reset, FlushM, ~StallM, AddSumTcE, AddSumTcM);
flopenrc #(4) EMRegAdd3(clk, reset, PipeClearEM, PipeEnableEM, AddSelInvE, AddSelInvM); flopenrc #(4) EMRegAdd3(clk, reset, FlushM, ~StallM, AddSelInvE, AddSelInvM);
flopenrc #(11) EMRegAdd4(clk, reset, PipeClearEM, PipeEnableEM, AddExpPostSumE, AddExpPostSumM); flopenrc #(11) EMRegAdd4(clk, reset, FlushM, ~StallM, AddExpPostSumE, AddExpPostSumM);
flopenrc #(1) EMRegAdd5(clk, reset, PipeClearEM, PipeEnableEM, AddCorrSignE, AddCorrSignM); flopenrc #(1) EMRegAdd5(clk, reset, FlushM, ~StallM, AddCorrSignE, AddCorrSignM);
flopenrc #(1) EMRegAdd6(clk, reset, PipeClearEM, PipeEnableEM, AddOp1NormE, AddOp1NormM); flopenrc #(1) EMRegAdd6(clk, reset, FlushM, ~StallM, AddOp1NormE, AddOp1NormM);
flopenrc #(1) EMRegAdd7(clk, reset, PipeClearEM, PipeEnableEM, AddOp2NormE, AddOp2NormM); flopenrc #(1) EMRegAdd7(clk, reset, FlushM, ~StallM, AddOp2NormE, AddOp2NormM);
flopenrc #(1) EMRegAdd8(clk, reset, PipeClearEM, PipeEnableEM, AddOpANormE, AddOpANormM); flopenrc #(1) EMRegAdd8(clk, reset, FlushM, ~StallM, AddOpANormE, AddOpANormM);
flopenrc #(1) EMRegAdd9(clk, reset, PipeClearEM, PipeEnableEM, AddOpBNormE, AddOpBNormM); flopenrc #(1) EMRegAdd9(clk, reset, FlushM, ~StallM, AddOpBNormE, AddOpBNormM);
flopenrc #(1) EMRegAdd10(clk, reset, PipeClearEM, PipeEnableEM, AddInvalidE, AddInvalidM); flopenrc #(1) EMRegAdd10(clk, reset, FlushM, ~StallM, AddInvalidE, AddInvalidM);
flopenrc #(1) EMRegAdd11(clk, reset, PipeClearEM, PipeEnableEM, AddDenormInE, AddDenormInM); flopenrc #(1) EMRegAdd11(clk, reset, FlushM, ~StallM, AddDenormInE, AddDenormInM);
flopenrc #(1) EMRegAdd12(clk, reset, PipeClearEM, PipeEnableEM, AddConvertE, AddConvertM); flopenrc #(1) EMRegAdd12(clk, reset, FlushM, ~StallM, AddConvertE, AddConvertM);
flopenrc #(1) EMRegAdd13(clk, reset, PipeClearEM, PipeEnableEM, AddSwapE, AddSwapM); flopenrc #(1) EMRegAdd13(clk, reset, FlushM, ~StallM, AddSwapE, AddSwapM);
flopenrc #(1) EMRegAdd14(clk, reset, PipeClearEM, PipeEnableEM, AddNormOvflowE, AddNormOvflowM); flopenrc #(1) EMRegAdd14(clk, reset, FlushM, ~StallM, AddNormOvflowE, AddNormOvflowM);
flopenrc #(1) EMRegAdd15(clk, reset, PipeClearEM, PipeEnableEM, AddSignAE, AddSignAM); flopenrc #(1) EMRegAdd15(clk, reset, FlushM, ~StallM, AddSignAE, AddSignAM);
flopenrc #(64) EMRegAdd16(clk, reset, PipeClearEM, PipeEnableEM, AddFloat1E, AddFloat1M); flopenrc #(64) EMRegAdd16(clk, reset, FlushM, ~StallM, AddFloat1E, AddFloat1M);
flopenrc #(64) EMRegAdd17(clk, reset, PipeClearEM, PipeEnableEM, AddFloat2E, AddFloat2M); flopenrc #(64) EMRegAdd17(clk, reset, FlushM, ~StallM, AddFloat2E, AddFloat2M);
flopenrc #(12) EMRegAdd18(clk, reset, PipeClearEM, PipeEnableEM, AddExp1DenormE, AddExp1DenormM); flopenrc #(12) EMRegAdd18(clk, reset, FlushM, ~StallM, AddExp1DenormE, AddExp1DenormM);
flopenrc #(12) EMRegAdd19(clk, reset, PipeClearEM, PipeEnableEM, AddExp2DenormE, AddExp2DenormM); flopenrc #(12) EMRegAdd19(clk, reset, FlushM, ~StallM, AddExp2DenormE, AddExp2DenormM);
flopenrc #(11) EMRegAdd20(clk, reset, PipeClearEM, PipeEnableEM, AddExponentE, AddExponentM); flopenrc #(11) EMRegAdd20(clk, reset, FlushM, ~StallM, AddExponentE, AddExponentM);
flopenrc #(3) EMRegAdd23(clk, reset, PipeClearEM, PipeEnableEM, AddRmE, AddRmM); flopenrc #(3) EMRegAdd23(clk, reset, FlushM, ~StallM, AddRmE, AddRmM);
flopenrc #(4) EMRegAdd24(clk, reset, PipeClearEM, PipeEnableEM, AddOpTypeE, AddOpTypeM); flopenrc #(4) EMRegAdd24(clk, reset, FlushM, ~StallM, AddOpTypeE, AddOpTypeM);
flopenrc #(1) EMRegAdd25(clk, reset, PipeClearEM, PipeEnableEM, AddPE, AddPM); flopenrc #(1) EMRegAdd25(clk, reset, FlushM, ~StallM, AddPE, AddPM);
flopenrc #(1) EMRegAdd26(clk, reset, PipeClearEM, PipeEnableEM, AddOvEnE, AddOvEnM); flopenrc #(1) EMRegAdd26(clk, reset, FlushM, ~StallM, AddOvEnE, AddOvEnM);
flopenrc #(1) EMRegAdd27(clk, reset, PipeClearEM, PipeEnableEM, AddUnEnE, AddUnEnM); flopenrc #(1) EMRegAdd27(clk, reset, FlushM, ~StallM, AddUnEnE, AddUnEnM);
//***************** //*****************
// fpcmp E/M pipe registers // fpcmp E/M pipe registers
//***************** //*****************
flopenrc #(8) EMRegCmp1(clk, reset, PipeClearEM, PipeEnableEM, WE, WM); flopenrc #(8) EMRegCmp1(clk, reset, FlushM, ~StallM, WE, WM);
flopenrc #(8) EMRegCmp2(clk, reset, PipeClearEM, PipeEnableEM, XE, XM); flopenrc #(8) EMRegCmp2(clk, reset, FlushM, ~StallM, XE, XM);
flopenrc #(1) EMRegcmp3(clk, reset, PipeClearEM, PipeEnableEM, ANaNE, ANaNM); flopenrc #(1) EMRegcmp3(clk, reset, FlushM, ~StallM, ANaNE, ANaNM);
flopenrc #(1) EMRegCmp4(clk, reset, PipeClearEM, PipeEnableEM, BNaNE, BNaNM); flopenrc #(1) EMRegCmp4(clk, reset, FlushM, ~StallM, BNaNE, BNaNM);
flopenrc #(1) EMRegCmp5(clk, reset, PipeClearEM, PipeEnableEM, AzeroE, AzeroM); flopenrc #(1) EMRegCmp5(clk, reset, FlushM, ~StallM, AzeroE, AzeroM);
flopenrc #(1) EMRegCmp6(clk, reset, PipeClearEM, PipeEnableEM, BzeroE, BzeroM); flopenrc #(1) EMRegCmp6(clk, reset, FlushM, ~StallM, BzeroE, BzeroM);
// put this in for the event we want to delay fsgn - will otherwise bypass // put this in for the event we want to delay fsgn - will otherwise bypass
//***************** //*****************
// fpsgn E/M pipe registers // fpsgn E/M pipe registers
//***************** //*****************
flopenrc #(64) EMRegSgn2(clk, reset, PipeClearEM, PipeEnableEM, SgnResultE, SgnResultM); flopenrc #(64) EMRegSgn2(clk, reset, FlushM, ~StallM, SgnResultE, SgnResultM);
flopenrc #(5) EMRegSgn3(clk, reset, PipeClearEM, PipeEnableEM, SgnFlagsE, SgnFlagsM); flopenrc #(5) EMRegSgn3(clk, reset, FlushM, ~StallM, SgnFlagsE, SgnFlagsM);
//***************** //*****************
// other E/M pipe registers // other E/M pipe registers
//***************** //*****************
flopenrc #(1) EMReg1(clk, reset, PipeClearEM, PipeEnableEM, FWriteEnE, FWriteEnM); flopenrc #(1) EMReg1(clk, reset, FlushM, ~StallM, FWriteEnE, FWriteEnM);
flopenrc #(3) EMReg2(clk, reset, PipeClearEM, PipeEnableEM, FResultSelE, FResultSelM); flopenrc #(3) EMReg2(clk, reset, FlushM, ~StallM, FResultSelE, FResultSelM);
flopenrc #(3) EMReg3(clk, reset, PipeClearEM, PipeEnableEM, FrmE, FrmM); flopenrc #(3) EMReg3(clk, reset, FlushM, ~StallM, FrmE, FrmM);
flopenrc #(1) EMReg4(clk, reset, PipeClearEM, PipeEnableEM, FmtE, FmtM); flopenrc #(1) EMReg4(clk, reset, FlushM, ~StallM, FmtE, FmtM);
flopenrc #(5) EMReg5(clk, reset, PipeClearEM, PipeEnableEM, RdE, RdM); flopenrc #(5) EMReg5(clk, reset, FlushM, ~StallM, RdE, RdM);
flopenrc #(4) EMReg6(clk, reset, PipeClearEM, PipeEnableEM, FOpCtrlE, FOpCtrlM); flopenrc #(4) EMReg6(clk, reset, FlushM, ~StallM, FOpCtrlE, FOpCtrlM);
flopenrc #(1) EMReg7(clk, reset, PipeClearEM, PipeEnableEM, FWriteIntE, FWriteIntM); flopenrc #(1) EMReg7(clk, reset, FlushM, ~StallM, FWriteIntE, FWriteIntM);
flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM); flopenrc #(2) EMReg8(clk, reset, FlushM, ~StallM, FMemRWE, FMemRWM);
flopenrc #(1) EMReg9(clk, reset, PipeClearEM, PipeEnableEM, SelLoadInputE, SelLoadInputM); flopenrc #(1) EMReg9(clk, reset, FlushM, ~StallM, SelLoadInputE, SelLoadInputM);
//***************** //*****************
// fpuclassify E/M pipe registers // fpuclassify E/M pipe registers
//***************** //*****************
flopenrc #(64) EMRegClass(clk, reset, PipeClearEM, PipeEnableEM, ClassResultE, ClassResultM); flopenrc #(64) EMRegClass(clk, reset, FlushM, ~StallM, ClassResultE, ClassResultM);
//BEGIN MEMORY STAGE //BEGIN MEMORY STAGE
@ -366,56 +335,56 @@ module fpu (
//***************** //*****************
//fpregfile M/W pipe registers //fpregfile M/W pipe registers
//***************** //*****************
flopenrc #(64) MWFpReg1(clk, reset, PipeClearMW, PipeEnableMW, FInput1M, FInput1W); flopenrc #(64) MWFpReg1(clk, reset, FlushW, ~StallW, FInput1M, FInput1W);
//***************** //*****************
// fma M/W pipe registers // fma M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegFma1(clk, reset, PipeClearMW, PipeEnableMW, FmaResultM, FmaResultW); flopenrc #(64) MWRegFma1(clk, reset, FlushW, ~StallW, FmaResultM, FmaResultW);
flopenrc #(5) MWRegFma2(clk, reset, PipeClearMW, PipeEnableMW, FmaFlagsM, FmaFlagsW); flopenrc #(5) MWRegFma2(clk, reset, FlushW, ~StallW, FmaFlagsM, FmaFlagsW);
//***************** //*****************
// fpdiv M/W pipe registers // fpdiv M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegDiv1(clk, reset, PipeClearMW, PipeEnableMW, FDivResultM, FDivResultW); flopenrc #(64) MWRegDiv1(clk, reset, FlushW, ~StallW, FDivResultM, FDivResultW);
flopenrc #(5) MWRegDiv2(clk, reset, PipeClearMW, PipeEnableMW, FDivFlagsM, FDivFlagsW); flopenrc #(5) MWRegDiv2(clk, reset, FlushW, ~StallW, FDivFlagsM, FDivFlagsW);
flopenrc #(1) MWRegDiv3(clk, reset, PipeClearMW, PipeEnableMW, DivDenormM, DivDenormW); flopenrc #(1) MWRegDiv3(clk, reset, FlushW, ~StallW, DivDenormM, DivDenormW);
//***************** //*****************
// fpadd M/W pipe registers // fpadd M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegAdd1(clk, reset, PipeClearMW, PipeEnableMW, FAddResultM, FAddResultW); flopenrc #(64) MWRegAdd1(clk, reset, FlushW, ~StallW, FAddResultM, FAddResultW);
flopenrc #(5) MWRegAdd2(clk, reset, PipeClearMW, PipeEnableMW, FAddFlagsM, FAddFlagsW); flopenrc #(5) MWRegAdd2(clk, reset, FlushW, ~StallW, FAddFlagsM, FAddFlagsW);
//***************** //*****************
// fpcmp M/W pipe registers // fpcmp M/W pipe registers
//***************** //*****************
flopenrc #(1) MWRegCmp1(clk, reset, PipeClearMW, PipeEnableMW, CmpInvalidM, CmpInvalidW); flopenrc #(1) MWRegCmp1(clk, reset, FlushW, ~StallW, CmpInvalidM, CmpInvalidW);
flopenrc #(2) MWRegCmp2(clk, reset, PipeClearMW, PipeEnableMW, CmpFCCM, CmpFCCW); flopenrc #(2) MWRegCmp2(clk, reset, FlushW, ~StallW, CmpFCCM, CmpFCCW);
flopenrc #(64) MWRegCmp3(clk, reset, PipeClearMW, PipeEnableMW, FCmpResultM, FCmpResultW); flopenrc #(64) MWRegCmp3(clk, reset, FlushW, ~StallW, FCmpResultM, FCmpResultW);
//***************** //*****************
// fpsgn M/W pipe registers // fpsgn M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegSgn1(clk, reset, PipeClearMW, PipeEnableMW, SgnResultM, SgnResultW); flopenrc #(64) MWRegSgn1(clk, reset, FlushW, ~StallW, SgnResultM, SgnResultW);
flopenrc #(5) MWRegSgn2(clk, reset, PipeClearMW, PipeEnableMW, SgnFlagsM, SgnFlagsW); flopenrc #(5) MWRegSgn2(clk, reset, FlushW, ~StallW, SgnFlagsM, SgnFlagsW);
//***************** //*****************
// other M/W pipe registers // other M/W pipe registers
//***************** //*****************
flopenrc #(1) MWReg1(clk, reset, PipeClearMW, PipeEnableMW, FWriteEnM, FWriteEnW); flopenrc #(1) MWReg1(clk, reset, FlushW, ~StallW, FWriteEnM, FWriteEnW);
flopenrc #(3) MWReg2(clk, reset, PipeClearMW, PipeEnableMW, FResultSelM, FResultSelW); flopenrc #(3) MWReg2(clk, reset, FlushW, ~StallW, FResultSelM, FResultSelW);
flopenrc #(1) MWReg3(clk, reset, PipeClearMW, PipeEnableMW, FmtM, FmtW); flopenrc #(1) MWReg3(clk, reset, FlushW, ~StallW, FmtM, FmtW);
flopenrc #(5) MWReg4(clk, reset, PipeClearMW, PipeEnableMW, RdM, RdW); flopenrc #(5) MWReg4(clk, reset, FlushW, ~StallW, RdM, RdW);
flopenrc #(64) MWReg5(clk, reset, PipeClearMW, PipeEnableMW, AlignedSrcAM, SrcAW); flopenrc #(64) MWReg5(clk, reset, FlushW, ~StallW, AlignedSrcAM, SrcAW);
// flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FLoadStoreResultM, FLoadStoreResultW); // flopenrc #(64) MWReg6(clk, reset, FlushW, ~StallW, FLoadStoreResultM, FLoadStoreResultW);
flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW); flopenrc #(1) MWReg7(clk, reset, FlushW, ~StallW, FWriteIntM, FWriteIntW);
flopenrc #(4) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FOpCtrlM, FOpCtrlW); flopenrc #(4) MWReg6(clk, reset, FlushW, ~StallW, FOpCtrlM, FOpCtrlW);
//***************** //*****************
// fpuclassify M/W pipe registers // fpuclassify M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegClass(clk, reset, PipeClearMW, PipeEnableMW, ClassResultM, ClassResultW); flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, ClassResultM, ClassResultW);

24
wally-pipelined/src/ifu/ifu.sv
View File

@ -34,7 +34,7 @@ module ifu (
input logic [`XLEN-1:0] InstrInF, input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF, input logic InstrAckF,
output logic [`XLEN-1:0] PCF, output logic [`XLEN-1:0] PCF,
output logic [`XLEN-1:0] InstrPAdrF, output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF, output logic InstrReadF,
output logic ICacheStallF, output logic ICacheStallF,
// Decode // Decode
@ -92,10 +92,10 @@ module ifu (
logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
logic PrivilegedChangePCM; logic PrivilegedChangePCM;
logic IllegalCompInstrD; logic IllegalCompInstrD;
logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCNextPF, PCPF; logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCPF;
logic [`XLEN-3:0] PCPlusUpperF; logic [`XLEN-3:0] PCPlusUpperF;
logic CompressedF; logic CompressedF;
logic [31:0] InstrRawD; logic [31:0] InstrRawD, FinalInstrRawF;
localparam [31:0] nop = 32'h00000013; // instruction for NOP localparam [31:0] nop = 32'h00000013; // instruction for NOP
logic reset_q; // *** look at this later. logic reset_q; // *** look at this later.
@ -136,15 +136,15 @@ module ifu (
//assign InstrReadF = ~StallD; // *** & ICacheMissF; add later //assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
// assign InstrReadF = 1; // *** & ICacheMissF; add later // assign InstrReadF = 1; // *** & ICacheMissF; add later
// jarred 2021-03-14 Add instrution cache block to remove rd2 icache icache(.*,
assign PCNextPF = PCNextF; // Temporary workaround until iTLB is live .PCNextF(PCNextF[`PA_BITS-1:0]),
icache icache(.*); .PCPF(PCPFmmu));
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
assign PrivilegedChangePCM = RetM | TrapM; assign PrivilegedChangePCM = RetM | TrapM;
//mux3 #(`XLEN) pcmux(PCPlus2or4F, PCCorrectE, PrivilegedNextPCM, {PrivilegedChangePCM, BPPredWrongE}, UnalignedPCNextF);
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F),
.d1(BPPredPCF), .d1(BPPredPCF),
.s(SelBPPredF), .s(SelBPPredF),
@ -160,15 +160,6 @@ module ifu (
.s(PrivilegedChangePCM), .s(PrivilegedChangePCM),
.y(PCNext2F)); .y(PCNext2F));
// *** try to remove this in the future as it can add a long path.
// StallF may arrive late.
/* -----\/----- EXCLUDED -----\/-----
mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
.d1(PCF),
.s(StallF),
.y(PCNext3F));
-----/\----- EXCLUDED -----/\----- */
mux2 #(`XLEN) pcmux4(.d0(PCNext2F), mux2 #(`XLEN) pcmux4(.d0(PCNext2F),
.d1(`RESET_VECTOR), .d1(`RESET_VECTOR),
.s(reset_q), .s(reset_q),
@ -253,6 +244,7 @@ module ifu (
// pipeline misaligned faults to M stage // pipeline misaligned faults to M stage
assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned
flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, BranchMisalignedFaultM); flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, BranchMisalignedFaultM);
// *** Ross Thompson. Check InstrMisalignedAdrM as I believe it is the same as PCF. Should be able to remove.
flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM); flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM; assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM;
assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path

2
wally-pipelined/src/wally/wallypipelinedhart.sv
View File

@ -137,7 +137,7 @@ module wallypipelinedhart (
logic [`XLEN-1:0] MemAdrM, WriteDataM; logic [`XLEN-1:0] MemAdrM, WriteDataM;
logic [`PA_BITS-1:0] MemPAdrM; logic [`PA_BITS-1:0] MemPAdrM;
logic [`XLEN-1:0] ReadDataW; logic [`XLEN-1:0] ReadDataW;
logic [`XLEN-1:0] InstrPAdrF; logic [`PA_BITS-1:0] InstrPAdrF;
logic [`XLEN-1:0] InstrRData; logic [`XLEN-1:0] InstrRData;
logic InstrReadF; logic InstrReadF;
logic DataStall; logic DataStall;

2
wally-pipelined/testbench/testbench-imperas.sv
View File

@ -554,7 +554,7 @@ string tests32f[] = '{
if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
else tests = {tests, tests32iNOc}; else tests = {tests, tests32iNOc};
if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
// if (`F_SUPPORTED) tests = {tests32f, tests}; if (`F_SUPPORTED) tests = {tests32f, tests};
if (`A_SUPPORTED) tests = {tests, tests32a}; if (`A_SUPPORTED) tests = {tests, tests32a};
if (`MEM_VIRTMEM) tests = {tests, tests32mmu}; if (`MEM_VIRTMEM) tests = {tests, tests32mmu};
end end