mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
bbracker
commit
13df69abdb
32
wally-pipelined/src/cache/ICacheCntrl.sv
vendored
32
wally-pipelined/src/cache/ICacheCntrl.sv
vendored
@ -33,15 +33,15 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
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// Input the address to read
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// The upper bits of the physical pc
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input logic [`XLEN-1:0] PCNextF,
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input logic [`XLEN-1:0] PCPF,
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input logic [`PA_BITS-1:0] PCNextF,
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input logic [`PA_BITS-1:0] PCPF,
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// Signals to/from cache memory
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// The read coming out of it
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input logic [31:0] ICacheMemReadData,
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input logic ICacheMemReadValid,
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// The address at which we want to search the cache memory
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output logic [`XLEN-1:0] PCTagF,
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output logic [`XLEN-1:0] PCNextIndexF,
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output logic [`PA_BITS-1:0] PCTagF,
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output logic [`PA_BITS-1:0] PCNextIndexF,
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output logic ICacheReadEn,
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// Load data into the cache
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output logic ICacheMemWriteEnable,
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@ -52,7 +52,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
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output logic CompressedF,
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// The instruction that was requested
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// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
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output logic [31:0] InstrRawD,
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output logic [31:0] FinalInstrRawF,
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// Outputs to pipeline control stuff
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output logic ICacheStallF, EndFetchState,
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@ -62,7 +62,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
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input logic [`XLEN-1:0] InstrInF,
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input logic InstrAckF,
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// The read we request from main memory
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output logic [`XLEN-1:0] InstrPAdrF,
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output logic [`PA_BITS-1:0] InstrPAdrF,
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output logic InstrReadF
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);
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@ -119,6 +119,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
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localparam WORDSPERLINE = BLOCKLEN/`XLEN;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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localparam integer PA_WIDTH = `PA_BITS - 2;
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logic [4:0] CurrState, NextState;
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logic hit, spill;
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@ -133,12 +135,10 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
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logic [LOGWPL:0] FetchCount, NextFetchCount;
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logic [`XLEN-1:0] PCPreFinalF, PCPFinalF, PCSpillF;
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logic [`XLEN-1:OFFSETWIDTH] PCPTrunkF;
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logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF;
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logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF;
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logic [31:0] FinalInstrRawF;
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logic [15:0] SpillDataBlock0;
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localparam [31:0] NOP = 32'h13;
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@ -156,11 +156,11 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
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// on spill we want to get the first 2 bytes of the next cache block.
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// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
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// simply add 2 to land on the next cache block.
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assign PCSpillF = PCPF + `XLEN'b10;
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assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width.
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// now we have to select between these three PCs
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assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
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assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF;
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assign PCNextIndexF = PCMux[1] ? PCPSpillF : PCPreFinalF;
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// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
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// *** read enable may not be necessary.
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@ -170,11 +170,10 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
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.d(PCMux),
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.q(PCMux_q));
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assign PCTagF = PCMux_q[1] ? PCSpillF : PCPF;
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assign PCNextIndexF = PCPFinalF;
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assign PCTagF = PCMux_q[1] ? PCPSpillF : PCPF;
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// truncate the offset from PCPF for memory address generation
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assign PCPTrunkF = PCTagF[`XLEN-1:OFFSETWIDTH];
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assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH];
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// Detect if the instruction is compressed
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assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
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@ -395,7 +394,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
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// we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros.
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// fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with
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// more zeros after the addition. This will be the number of offset bits less the AHBByteLength.
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logic [`XLEN-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ;
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logic [`PA_BITS-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ;
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assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}};
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// verilator lint_off WIDTH
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@ -454,6 +453,5 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
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.d(reset),
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.q(reset_q));
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? NOP : FinalInstrRawF, NOP, InstrRawD);
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endmodule
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10
wally-pipelined/src/cache/ICacheMem.sv
vendored
10
wally-pipelined/src/cache/ICacheMem.sv
vendored
@ -8,8 +8,8 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
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// If flush is high, invalidate the entire cache
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input logic flush,
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input logic [`XLEN-1:0] PCTagF, // physical address
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input logic [`XLEN-1:0] PCNextIndexF, // virtual address
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input logic [`PA_BITS-1:0] PCTagF, // physical address
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input logic [`PA_BITS-1:0] PCNextIndexF, // virtual address
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input logic WriteEnable,
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input logic [BLOCKLEN-1:0] WriteLine,
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output logic [BLOCKLEN-1:0] ReadLineF,
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@ -21,7 +21,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
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localparam OFFSETLEN = $clog2(BLOCKBYTELEN);
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localparam INDEXLEN = $clog2(NUMLINES);
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// *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48
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localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN;
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localparam TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
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logic [TAGLEN-1:0] LookupTag;
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logic [NUMLINES-1:0] ValidOut;
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@ -39,7 +39,7 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
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cachetags (.*,
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.Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.ReadData(LookupTag),
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.WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN])
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.WriteData(PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN])
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);
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// Correctly handle the valid bits
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@ -55,5 +55,5 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
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end
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DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]];
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end
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assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]);
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assign HitF = DataValidBit && (LookupTag == PCTagF[`PA_BITS-1:INDEXLEN+OFFSETLEN]);
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endmodule
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10
wally-pipelined/src/cache/icache.sv
vendored
10
wally-pipelined/src/cache/icache.sv
vendored
@ -31,13 +31,13 @@ module icache
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input logic clk, reset,
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input logic StallF, StallD,
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input logic FlushD,
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input logic [`XLEN-1:0] PCNextF,
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input logic [`XLEN-1:0] PCPF,
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input logic [`PA_BITS-1:0] PCNextF,
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input logic [`PA_BITS-1:0] PCPF,
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// Data read in from the ebu unit
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input logic [`XLEN-1:0] InstrInF,
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input logic InstrAckF,
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// Read requested from the ebu unit
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output logic [`XLEN-1:0] InstrPAdrF,
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output logic [`PA_BITS-1:0] InstrPAdrF,
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output logic InstrReadF,
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// High if the instruction currently in the fetch stage is compressed
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output logic CompressedF,
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@ -45,7 +45,7 @@ module icache
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output logic ICacheStallF,
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// The raw (not decompressed) instruction that was requested
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// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
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output logic [31:0] InstrRawD
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output logic [31:0] FinalInstrRawF
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);
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// Configuration parameters
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@ -58,7 +58,7 @@ module icache
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logic ICacheMemWriteEnable;
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logic [BLOCKLEN-1:0] ICacheMemWriteData;
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logic EndFetchState;
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logic [`XLEN-1:0] PCTagF, PCNextIndexF;
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logic [`PA_BITS-1:0] PCTagF, PCNextIndexF;
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// Output signals from cache memory
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logic [31:0] ICacheMemReadData;
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logic ICacheMemReadValid;
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@ -42,7 +42,7 @@ module ahblite (
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input logic [1:0] AtomicMaskedM,
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input logic [6:0] Funct7M,
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// Signals from Instruction Cache
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input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram
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input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram
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input logic InstrReadF,
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output logic [`XLEN-1:0] InstrRData,
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output logic InstrAckF,
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@ -1,7 +1,7 @@
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///////////////////////////////////////////
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//
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// Written:
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// Modified:
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// Written: Katherine Parry, Bret Mathis
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// Modified: 6/23/2021
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//
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// Purpose: FPU
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//
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@ -25,23 +25,23 @@
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`include "wally-config.vh"
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module fpu (
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input logic [2:0] FRM_REGW, // Rounding mode from CSR
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input logic reset,
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input logic clk,
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input logic reset,
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input logic [2:0] FRM_REGW, // Rounding mode from CSR
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input logic [31:0] InstrD,
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input logic [`XLEN-1:0] ReadDataW, // Read data from memory
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input logic RegWriteD, // register write enable from ieu
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input logic [`XLEN-1:0] SrcAE, // Integer input being processed
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input logic [`XLEN-1:0] SrcAM, // Integer input being written into fpreg
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input logic StallE, StallM, StallW,
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input logic FlushE, FlushM, FlushW,
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input logic [`XLEN-1:0] ReadDataW, // Read data from memory
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input logic RegWriteD, // register write enable from ieu
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output logic [4:0] SetFflagsM, // FPU flags
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output logic [1:0] FMemRWM, // Read/write enable for memory {read, write}
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output logic FStallD, // Stall the decode stage if Div/Sqrt instruction
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output logic FWriteIntE, FWriteIntM, FWriteIntW, // Write integer register enable
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output logic [`XLEN-1:0] FWriteDataM, // Data to be written to memory
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output logic FDivBusyE, // Is the divison/sqrt unit busy
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
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output logic [4:0] SetFflagsM, // FPU flags
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output logic [`XLEN-1:0] FPUResultW); // FPU result
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// control logic signal instantiation
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@ -58,10 +58,10 @@ module fpu (
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logic FInput2UsedD; // Is input 2 used
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logic FInput3UsedD; // Is input 3 used
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logic [2:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select FP result
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logic [3:0] FOpCtrlD, FOpCtrlE, FOpCtrlM, FOpCtrlW; // Select which opperation to do in each component
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logic [3:0] FOpCtrlD, FOpCtrlE, FOpCtrlM, FOpCtrlW; // Select which opperation to do in each component
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logic SelLoadInputE, SelLoadInputM; // Select which adress to load when single precision
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// regfile signals //*** KEP lint warning - changed `XLEN-1 to 63
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// regfile signals
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logic [4:0] RdE, RdM, RdW; // what adress to write to // ***Can take from ieu insted of pipelining
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logic [63:0] FWDM; // Write data for FP register
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logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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@ -147,26 +147,6 @@ module fpu (
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logic [63:0] FPUResult64W, FPUResult64E;
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logic [4:0] FPUFlagsW;
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// pipeline control logic
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logic PipeEnableDE;
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logic PipeEnableEM;
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logic PipeEnableMW;
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logic PipeClearDE;
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logic PipeClearEM;
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logic PipeClearMW;
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// temporarily assign pipe clear and enable signals
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// to never flush & always be running
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localparam PipeClear = 1'b0;
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localparam PipeEnable = 1'b1;
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always_comb begin
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||||
PipeEnableDE = ~StallE;
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PipeEnableEM = ~StallM;
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PipeEnableMW = ~StallW;
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PipeClearDE = FlushE;
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PipeClearEM = FlushM;
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PipeClearMW = FlushW;
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end
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//DECODE STAGE
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@ -185,29 +165,18 @@ module fpu (
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//*****************
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// fpregfile D/E pipe registers
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//*****************
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flopenrc #(64) DEReg1(clk, reset, PipeClearDE, PipeEnableDE, FRD1D, FRD1E);
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flopenrc #(64) DEReg2(clk, reset, PipeClearDE, PipeEnableDE, FRD2D, FRD2E);
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flopenrc #(64) DEReg3(clk, reset, PipeClearDE, PipeEnableDE, FRD3D, FRD3E);
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||||
flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
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||||
flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
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||||
flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
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||||
|
||||
//*****************
|
||||
// other D/E pipe registers
|
||||
//*****************
|
||||
flopenrc #(1) DEReg4(clk, reset, PipeClearDE, PipeEnableDE, FWriteEnD, FWriteEnE);
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||||
flopenrc #(3) DEReg5(clk, reset, PipeClearDE, PipeEnableDE, FResultSelD, FResultSelE);
|
||||
flopenrc #(3) DEReg6(clk, reset, PipeClearDE, PipeEnableDE, FrmD, FrmE);
|
||||
flopenrc #(1) DEReg7(clk, reset, PipeClearDE, PipeEnableDE, FmtD, FmtE);
|
||||
flopenrc #(5) DEReg8(clk, reset, PipeClearDE, PipeEnableDE, InstrD[11:7], RdE);
|
||||
flopenrc #(4) DEReg9(clk, reset, PipeClearDE, PipeEnableDE, FOpCtrlD, FOpCtrlE);
|
||||
flopenrc #(1) DEReg10(clk, reset, PipeClearDE, PipeEnableDE, FDivStartD, FDivStartE);
|
||||
flopenrc #(2) DEReg11(clk, reset, PipeClearDE, PipeEnableDE, FForwardInput1D, FForwardInput1E);
|
||||
flopenrc #(2) DEReg12(clk, reset, PipeClearDE, PipeEnableDE, FForwardInput2D, FForwardInput2E);
|
||||
flopenrc #(1) DEReg13(clk, reset, PipeClearDE, PipeEnableDE, FForwardInput3D, FForwardInput3E);
|
||||
flopenrc #(64) DEReg14(clk, reset, PipeClearDE, PipeEnableDE, FPUResult64W, FPUResult64E);
|
||||
flopenrc #(1) DEReg15(clk, reset, PipeClearDE, PipeEnableDE, FWriteIntD, FWriteIntE);
|
||||
flopenrc #(1) DEReg16(clk, reset, PipeClearDE, PipeEnableDE, FOutputInput2D, FOutputInput2E);
|
||||
flopenrc #(2) DEReg17(clk, reset, PipeClearDE, PipeEnableDE, FMemRWD, FMemRWE);
|
||||
flopenrc #(1) DEReg18(clk, reset, PipeClearDE, PipeEnableDE, InstrD[15], SelLoadInputE);
|
||||
|
||||
flopenrc #(64) DEReg14(clk, reset, FlushE, ~StallE, FPUResult64W, FPUResult64E);
|
||||
flopenrc #(28) CtrlRegE(clk, reset, FlushE, ~StallE,
|
||||
{FWriteEnD, FResultSelD, FrmD, FmtD, InstrD[11:7], FOpCtrlD, FDivStartD, FForwardInput1D, FForwardInput2D, FForwardInput3D, FWriteIntD, FOutputInput2D, FMemRWD, InstrD[15]},
|
||||
{FWriteEnE, FResultSelE, FrmE, FmtE, RdE, FOpCtrlE, FDivStartE, FForwardInput1E, FForwardInput2E, FForwardInput3E, FWriteIntE, FOutputInput2E, FMemRWE, SelLoadInputE});
|
||||
|
||||
//EXECUTION STAGE
|
||||
|
||||
// input muxs for forwarding
|
||||
@ -253,91 +222,91 @@ module fpu (
|
||||
//*****************
|
||||
//fpregfile D/E pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) EMFpReg1(clk, reset, PipeClearEM, PipeEnableEM, FInput1E, FInput1M);
|
||||
flopenrc #(64) EMFpReg2(clk, reset, PipeClearEM, PipeEnableEM, FInput2E, FInput2M);
|
||||
flopenrc #(64) EMFpReg3(clk, reset, PipeClearEM, PipeEnableEM, FInput3E, FInput3M);
|
||||
flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FInput1E, FInput1M);
|
||||
flopenrc #(64) EMFpReg2(clk, reset, FlushM, ~StallM, FInput2E, FInput2M);
|
||||
flopenrc #(64) EMFpReg3(clk, reset, FlushM, ~StallM, FInput3E, FInput3M);
|
||||
|
||||
//*****************
|
||||
// fma E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(106) EMRegFma3(clk, reset, PipeClearEM, PipeEnableEM, ProdManE, ProdManM);
|
||||
flopenrc #(162) EMRegFma4(clk, reset, PipeClearEM, PipeEnableEM, AlignedAddendE, AlignedAddendM);
|
||||
flopenrc #(13) EMRegFma6(clk, reset, PipeClearEM, PipeEnableEM, ProdExpE, ProdExpM);
|
||||
flopenrc #(1) EMRegFma7(clk, reset, PipeClearEM, PipeEnableEM, AddendStickyE, AddendStickyM);
|
||||
flopenrc #(1) EMRegFma8(clk, reset, PipeClearEM, PipeEnableEM, KillProdE, KillProdM);
|
||||
flopenrc #(1) EMRegFma10(clk, reset, PipeClearEM, PipeEnableEM, XZeroE, XZeroM);
|
||||
flopenrc #(1) EMRegFma11(clk, reset, PipeClearEM, PipeEnableEM, YZeroE, YZeroM);
|
||||
flopenrc #(1) EMRegFma12(clk, reset, PipeClearEM, PipeEnableEM, ZZeroE, ZZeroM);
|
||||
flopenrc #(1) EMRegFma16(clk, reset, PipeClearEM, PipeEnableEM, XInfE, XInfM);
|
||||
flopenrc #(1) EMRegFma17(clk, reset, PipeClearEM, PipeEnableEM, YInfE, YInfM);
|
||||
flopenrc #(1) EMRegFma18(clk, reset, PipeClearEM, PipeEnableEM, ZInfE, ZInfM);
|
||||
flopenrc #(1) EMRegFma19(clk, reset, PipeClearEM, PipeEnableEM, XNaNE, XNaNM);
|
||||
flopenrc #(1) EMRegFma20(clk, reset, PipeClearEM, PipeEnableEM, YNaNE, YNaNM);
|
||||
flopenrc #(1) EMRegFma21(clk, reset, PipeClearEM, PipeEnableEM, ZNaNE, ZNaNM);
|
||||
flopenrc #(106) EMRegFma3(clk, reset, FlushM, ~StallM, ProdManE, ProdManM);
|
||||
flopenrc #(162) EMRegFma4(clk, reset, FlushM, ~StallM, AlignedAddendE, AlignedAddendM);
|
||||
flopenrc #(13) EMRegFma6(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM);
|
||||
flopenrc #(1) EMRegFma7(clk, reset, FlushM, ~StallM, AddendStickyE, AddendStickyM);
|
||||
flopenrc #(1) EMRegFma8(clk, reset, FlushM, ~StallM, KillProdE, KillProdM);
|
||||
flopenrc #(1) EMRegFma10(clk, reset, FlushM, ~StallM, XZeroE, XZeroM);
|
||||
flopenrc #(1) EMRegFma11(clk, reset, FlushM, ~StallM, YZeroE, YZeroM);
|
||||
flopenrc #(1) EMRegFma12(clk, reset, FlushM, ~StallM, ZZeroE, ZZeroM);
|
||||
flopenrc #(1) EMRegFma16(clk, reset, FlushM, ~StallM, XInfE, XInfM);
|
||||
flopenrc #(1) EMRegFma17(clk, reset, FlushM, ~StallM, YInfE, YInfM);
|
||||
flopenrc #(1) EMRegFma18(clk, reset, FlushM, ~StallM, ZInfE, ZInfM);
|
||||
flopenrc #(1) EMRegFma19(clk, reset, FlushM, ~StallM, XNaNE, XNaNM);
|
||||
flopenrc #(1) EMRegFma20(clk, reset, FlushM, ~StallM, YNaNE, YNaNM);
|
||||
flopenrc #(1) EMRegFma21(clk, reset, FlushM, ~StallM, ZNaNE, ZNaNM);
|
||||
|
||||
//*****************
|
||||
// fpadd E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) EMRegAdd1(clk, reset, PipeClearEM, PipeEnableEM, AddSumE, AddSumM);
|
||||
flopenrc #(64) EMRegAdd2(clk, reset, PipeClearEM, PipeEnableEM, AddSumTcE, AddSumTcM);
|
||||
flopenrc #(4) EMRegAdd3(clk, reset, PipeClearEM, PipeEnableEM, AddSelInvE, AddSelInvM);
|
||||
flopenrc #(11) EMRegAdd4(clk, reset, PipeClearEM, PipeEnableEM, AddExpPostSumE, AddExpPostSumM);
|
||||
flopenrc #(1) EMRegAdd5(clk, reset, PipeClearEM, PipeEnableEM, AddCorrSignE, AddCorrSignM);
|
||||
flopenrc #(1) EMRegAdd6(clk, reset, PipeClearEM, PipeEnableEM, AddOp1NormE, AddOp1NormM);
|
||||
flopenrc #(1) EMRegAdd7(clk, reset, PipeClearEM, PipeEnableEM, AddOp2NormE, AddOp2NormM);
|
||||
flopenrc #(1) EMRegAdd8(clk, reset, PipeClearEM, PipeEnableEM, AddOpANormE, AddOpANormM);
|
||||
flopenrc #(1) EMRegAdd9(clk, reset, PipeClearEM, PipeEnableEM, AddOpBNormE, AddOpBNormM);
|
||||
flopenrc #(1) EMRegAdd10(clk, reset, PipeClearEM, PipeEnableEM, AddInvalidE, AddInvalidM);
|
||||
flopenrc #(1) EMRegAdd11(clk, reset, PipeClearEM, PipeEnableEM, AddDenormInE, AddDenormInM);
|
||||
flopenrc #(1) EMRegAdd12(clk, reset, PipeClearEM, PipeEnableEM, AddConvertE, AddConvertM);
|
||||
flopenrc #(1) EMRegAdd13(clk, reset, PipeClearEM, PipeEnableEM, AddSwapE, AddSwapM);
|
||||
flopenrc #(1) EMRegAdd14(clk, reset, PipeClearEM, PipeEnableEM, AddNormOvflowE, AddNormOvflowM);
|
||||
flopenrc #(1) EMRegAdd15(clk, reset, PipeClearEM, PipeEnableEM, AddSignAE, AddSignAM);
|
||||
flopenrc #(64) EMRegAdd16(clk, reset, PipeClearEM, PipeEnableEM, AddFloat1E, AddFloat1M);
|
||||
flopenrc #(64) EMRegAdd17(clk, reset, PipeClearEM, PipeEnableEM, AddFloat2E, AddFloat2M);
|
||||
flopenrc #(12) EMRegAdd18(clk, reset, PipeClearEM, PipeEnableEM, AddExp1DenormE, AddExp1DenormM);
|
||||
flopenrc #(12) EMRegAdd19(clk, reset, PipeClearEM, PipeEnableEM, AddExp2DenormE, AddExp2DenormM);
|
||||
flopenrc #(11) EMRegAdd20(clk, reset, PipeClearEM, PipeEnableEM, AddExponentE, AddExponentM);
|
||||
flopenrc #(3) EMRegAdd23(clk, reset, PipeClearEM, PipeEnableEM, AddRmE, AddRmM);
|
||||
flopenrc #(4) EMRegAdd24(clk, reset, PipeClearEM, PipeEnableEM, AddOpTypeE, AddOpTypeM);
|
||||
flopenrc #(1) EMRegAdd25(clk, reset, PipeClearEM, PipeEnableEM, AddPE, AddPM);
|
||||
flopenrc #(1) EMRegAdd26(clk, reset, PipeClearEM, PipeEnableEM, AddOvEnE, AddOvEnM);
|
||||
flopenrc #(1) EMRegAdd27(clk, reset, PipeClearEM, PipeEnableEM, AddUnEnE, AddUnEnM);
|
||||
flopenrc #(64) EMRegAdd1(clk, reset, FlushM, ~StallM, AddSumE, AddSumM);
|
||||
flopenrc #(64) EMRegAdd2(clk, reset, FlushM, ~StallM, AddSumTcE, AddSumTcM);
|
||||
flopenrc #(4) EMRegAdd3(clk, reset, FlushM, ~StallM, AddSelInvE, AddSelInvM);
|
||||
flopenrc #(11) EMRegAdd4(clk, reset, FlushM, ~StallM, AddExpPostSumE, AddExpPostSumM);
|
||||
flopenrc #(1) EMRegAdd5(clk, reset, FlushM, ~StallM, AddCorrSignE, AddCorrSignM);
|
||||
flopenrc #(1) EMRegAdd6(clk, reset, FlushM, ~StallM, AddOp1NormE, AddOp1NormM);
|
||||
flopenrc #(1) EMRegAdd7(clk, reset, FlushM, ~StallM, AddOp2NormE, AddOp2NormM);
|
||||
flopenrc #(1) EMRegAdd8(clk, reset, FlushM, ~StallM, AddOpANormE, AddOpANormM);
|
||||
flopenrc #(1) EMRegAdd9(clk, reset, FlushM, ~StallM, AddOpBNormE, AddOpBNormM);
|
||||
flopenrc #(1) EMRegAdd10(clk, reset, FlushM, ~StallM, AddInvalidE, AddInvalidM);
|
||||
flopenrc #(1) EMRegAdd11(clk, reset, FlushM, ~StallM, AddDenormInE, AddDenormInM);
|
||||
flopenrc #(1) EMRegAdd12(clk, reset, FlushM, ~StallM, AddConvertE, AddConvertM);
|
||||
flopenrc #(1) EMRegAdd13(clk, reset, FlushM, ~StallM, AddSwapE, AddSwapM);
|
||||
flopenrc #(1) EMRegAdd14(clk, reset, FlushM, ~StallM, AddNormOvflowE, AddNormOvflowM);
|
||||
flopenrc #(1) EMRegAdd15(clk, reset, FlushM, ~StallM, AddSignAE, AddSignAM);
|
||||
flopenrc #(64) EMRegAdd16(clk, reset, FlushM, ~StallM, AddFloat1E, AddFloat1M);
|
||||
flopenrc #(64) EMRegAdd17(clk, reset, FlushM, ~StallM, AddFloat2E, AddFloat2M);
|
||||
flopenrc #(12) EMRegAdd18(clk, reset, FlushM, ~StallM, AddExp1DenormE, AddExp1DenormM);
|
||||
flopenrc #(12) EMRegAdd19(clk, reset, FlushM, ~StallM, AddExp2DenormE, AddExp2DenormM);
|
||||
flopenrc #(11) EMRegAdd20(clk, reset, FlushM, ~StallM, AddExponentE, AddExponentM);
|
||||
flopenrc #(3) EMRegAdd23(clk, reset, FlushM, ~StallM, AddRmE, AddRmM);
|
||||
flopenrc #(4) EMRegAdd24(clk, reset, FlushM, ~StallM, AddOpTypeE, AddOpTypeM);
|
||||
flopenrc #(1) EMRegAdd25(clk, reset, FlushM, ~StallM, AddPE, AddPM);
|
||||
flopenrc #(1) EMRegAdd26(clk, reset, FlushM, ~StallM, AddOvEnE, AddOvEnM);
|
||||
flopenrc #(1) EMRegAdd27(clk, reset, FlushM, ~StallM, AddUnEnE, AddUnEnM);
|
||||
|
||||
//*****************
|
||||
// fpcmp E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(8) EMRegCmp1(clk, reset, PipeClearEM, PipeEnableEM, WE, WM);
|
||||
flopenrc #(8) EMRegCmp2(clk, reset, PipeClearEM, PipeEnableEM, XE, XM);
|
||||
flopenrc #(1) EMRegcmp3(clk, reset, PipeClearEM, PipeEnableEM, ANaNE, ANaNM);
|
||||
flopenrc #(1) EMRegCmp4(clk, reset, PipeClearEM, PipeEnableEM, BNaNE, BNaNM);
|
||||
flopenrc #(1) EMRegCmp5(clk, reset, PipeClearEM, PipeEnableEM, AzeroE, AzeroM);
|
||||
flopenrc #(1) EMRegCmp6(clk, reset, PipeClearEM, PipeEnableEM, BzeroE, BzeroM);
|
||||
flopenrc #(8) EMRegCmp1(clk, reset, FlushM, ~StallM, WE, WM);
|
||||
flopenrc #(8) EMRegCmp2(clk, reset, FlushM, ~StallM, XE, XM);
|
||||
flopenrc #(1) EMRegcmp3(clk, reset, FlushM, ~StallM, ANaNE, ANaNM);
|
||||
flopenrc #(1) EMRegCmp4(clk, reset, FlushM, ~StallM, BNaNE, BNaNM);
|
||||
flopenrc #(1) EMRegCmp5(clk, reset, FlushM, ~StallM, AzeroE, AzeroM);
|
||||
flopenrc #(1) EMRegCmp6(clk, reset, FlushM, ~StallM, BzeroE, BzeroM);
|
||||
|
||||
// put this in for the event we want to delay fsgn - will otherwise bypass
|
||||
//*****************
|
||||
// fpsgn E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) EMRegSgn2(clk, reset, PipeClearEM, PipeEnableEM, SgnResultE, SgnResultM);
|
||||
flopenrc #(5) EMRegSgn3(clk, reset, PipeClearEM, PipeEnableEM, SgnFlagsE, SgnFlagsM);
|
||||
flopenrc #(64) EMRegSgn2(clk, reset, FlushM, ~StallM, SgnResultE, SgnResultM);
|
||||
flopenrc #(5) EMRegSgn3(clk, reset, FlushM, ~StallM, SgnFlagsE, SgnFlagsM);
|
||||
|
||||
//*****************
|
||||
// other E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(1) EMReg1(clk, reset, PipeClearEM, PipeEnableEM, FWriteEnE, FWriteEnM);
|
||||
flopenrc #(3) EMReg2(clk, reset, PipeClearEM, PipeEnableEM, FResultSelE, FResultSelM);
|
||||
flopenrc #(3) EMReg3(clk, reset, PipeClearEM, PipeEnableEM, FrmE, FrmM);
|
||||
flopenrc #(1) EMReg4(clk, reset, PipeClearEM, PipeEnableEM, FmtE, FmtM);
|
||||
flopenrc #(5) EMReg5(clk, reset, PipeClearEM, PipeEnableEM, RdE, RdM);
|
||||
flopenrc #(4) EMReg6(clk, reset, PipeClearEM, PipeEnableEM, FOpCtrlE, FOpCtrlM);
|
||||
flopenrc #(1) EMReg7(clk, reset, PipeClearEM, PipeEnableEM, FWriteIntE, FWriteIntM);
|
||||
flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM);
|
||||
flopenrc #(1) EMReg9(clk, reset, PipeClearEM, PipeEnableEM, SelLoadInputE, SelLoadInputM);
|
||||
flopenrc #(1) EMReg1(clk, reset, FlushM, ~StallM, FWriteEnE, FWriteEnM);
|
||||
flopenrc #(3) EMReg2(clk, reset, FlushM, ~StallM, FResultSelE, FResultSelM);
|
||||
flopenrc #(3) EMReg3(clk, reset, FlushM, ~StallM, FrmE, FrmM);
|
||||
flopenrc #(1) EMReg4(clk, reset, FlushM, ~StallM, FmtE, FmtM);
|
||||
flopenrc #(5) EMReg5(clk, reset, FlushM, ~StallM, RdE, RdM);
|
||||
flopenrc #(4) EMReg6(clk, reset, FlushM, ~StallM, FOpCtrlE, FOpCtrlM);
|
||||
flopenrc #(1) EMReg7(clk, reset, FlushM, ~StallM, FWriteIntE, FWriteIntM);
|
||||
flopenrc #(2) EMReg8(clk, reset, FlushM, ~StallM, FMemRWE, FMemRWM);
|
||||
flopenrc #(1) EMReg9(clk, reset, FlushM, ~StallM, SelLoadInputE, SelLoadInputM);
|
||||
|
||||
//*****************
|
||||
// fpuclassify E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) EMRegClass(clk, reset, PipeClearEM, PipeEnableEM, ClassResultE, ClassResultM);
|
||||
flopenrc #(64) EMRegClass(clk, reset, FlushM, ~StallM, ClassResultE, ClassResultM);
|
||||
|
||||
//BEGIN MEMORY STAGE
|
||||
|
||||
@ -366,56 +335,56 @@ module fpu (
|
||||
//*****************
|
||||
//fpregfile M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) MWFpReg1(clk, reset, PipeClearMW, PipeEnableMW, FInput1M, FInput1W);
|
||||
flopenrc #(64) MWFpReg1(clk, reset, FlushW, ~StallW, FInput1M, FInput1W);
|
||||
|
||||
//*****************
|
||||
// fma M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) MWRegFma1(clk, reset, PipeClearMW, PipeEnableMW, FmaResultM, FmaResultW);
|
||||
flopenrc #(5) MWRegFma2(clk, reset, PipeClearMW, PipeEnableMW, FmaFlagsM, FmaFlagsW);
|
||||
flopenrc #(64) MWRegFma1(clk, reset, FlushW, ~StallW, FmaResultM, FmaResultW);
|
||||
flopenrc #(5) MWRegFma2(clk, reset, FlushW, ~StallW, FmaFlagsM, FmaFlagsW);
|
||||
|
||||
//*****************
|
||||
// fpdiv M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) MWRegDiv1(clk, reset, PipeClearMW, PipeEnableMW, FDivResultM, FDivResultW);
|
||||
flopenrc #(5) MWRegDiv2(clk, reset, PipeClearMW, PipeEnableMW, FDivFlagsM, FDivFlagsW);
|
||||
flopenrc #(1) MWRegDiv3(clk, reset, PipeClearMW, PipeEnableMW, DivDenormM, DivDenormW);
|
||||
flopenrc #(64) MWRegDiv1(clk, reset, FlushW, ~StallW, FDivResultM, FDivResultW);
|
||||
flopenrc #(5) MWRegDiv2(clk, reset, FlushW, ~StallW, FDivFlagsM, FDivFlagsW);
|
||||
flopenrc #(1) MWRegDiv3(clk, reset, FlushW, ~StallW, DivDenormM, DivDenormW);
|
||||
|
||||
//*****************
|
||||
// fpadd M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) MWRegAdd1(clk, reset, PipeClearMW, PipeEnableMW, FAddResultM, FAddResultW);
|
||||
flopenrc #(5) MWRegAdd2(clk, reset, PipeClearMW, PipeEnableMW, FAddFlagsM, FAddFlagsW);
|
||||
flopenrc #(64) MWRegAdd1(clk, reset, FlushW, ~StallW, FAddResultM, FAddResultW);
|
||||
flopenrc #(5) MWRegAdd2(clk, reset, FlushW, ~StallW, FAddFlagsM, FAddFlagsW);
|
||||
|
||||
//*****************
|
||||
// fpcmp M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(1) MWRegCmp1(clk, reset, PipeClearMW, PipeEnableMW, CmpInvalidM, CmpInvalidW);
|
||||
flopenrc #(2) MWRegCmp2(clk, reset, PipeClearMW, PipeEnableMW, CmpFCCM, CmpFCCW);
|
||||
flopenrc #(64) MWRegCmp3(clk, reset, PipeClearMW, PipeEnableMW, FCmpResultM, FCmpResultW);
|
||||
flopenrc #(1) MWRegCmp1(clk, reset, FlushW, ~StallW, CmpInvalidM, CmpInvalidW);
|
||||
flopenrc #(2) MWRegCmp2(clk, reset, FlushW, ~StallW, CmpFCCM, CmpFCCW);
|
||||
flopenrc #(64) MWRegCmp3(clk, reset, FlushW, ~StallW, FCmpResultM, FCmpResultW);
|
||||
|
||||
//*****************
|
||||
// fpsgn M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) MWRegSgn1(clk, reset, PipeClearMW, PipeEnableMW, SgnResultM, SgnResultW);
|
||||
flopenrc #(5) MWRegSgn2(clk, reset, PipeClearMW, PipeEnableMW, SgnFlagsM, SgnFlagsW);
|
||||
flopenrc #(64) MWRegSgn1(clk, reset, FlushW, ~StallW, SgnResultM, SgnResultW);
|
||||
flopenrc #(5) MWRegSgn2(clk, reset, FlushW, ~StallW, SgnFlagsM, SgnFlagsW);
|
||||
|
||||
//*****************
|
||||
// other M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(1) MWReg1(clk, reset, PipeClearMW, PipeEnableMW, FWriteEnM, FWriteEnW);
|
||||
flopenrc #(3) MWReg2(clk, reset, PipeClearMW, PipeEnableMW, FResultSelM, FResultSelW);
|
||||
flopenrc #(1) MWReg3(clk, reset, PipeClearMW, PipeEnableMW, FmtM, FmtW);
|
||||
flopenrc #(5) MWReg4(clk, reset, PipeClearMW, PipeEnableMW, RdM, RdW);
|
||||
flopenrc #(64) MWReg5(clk, reset, PipeClearMW, PipeEnableMW, AlignedSrcAM, SrcAW);
|
||||
// flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FLoadStoreResultM, FLoadStoreResultW);
|
||||
flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
|
||||
flopenrc #(4) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FOpCtrlM, FOpCtrlW);
|
||||
flopenrc #(1) MWReg1(clk, reset, FlushW, ~StallW, FWriteEnM, FWriteEnW);
|
||||
flopenrc #(3) MWReg2(clk, reset, FlushW, ~StallW, FResultSelM, FResultSelW);
|
||||
flopenrc #(1) MWReg3(clk, reset, FlushW, ~StallW, FmtM, FmtW);
|
||||
flopenrc #(5) MWReg4(clk, reset, FlushW, ~StallW, RdM, RdW);
|
||||
flopenrc #(64) MWReg5(clk, reset, FlushW, ~StallW, AlignedSrcAM, SrcAW);
|
||||
// flopenrc #(64) MWReg6(clk, reset, FlushW, ~StallW, FLoadStoreResultM, FLoadStoreResultW);
|
||||
flopenrc #(1) MWReg7(clk, reset, FlushW, ~StallW, FWriteIntM, FWriteIntW);
|
||||
flopenrc #(4) MWReg6(clk, reset, FlushW, ~StallW, FOpCtrlM, FOpCtrlW);
|
||||
|
||||
//*****************
|
||||
// fpuclassify M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) MWRegClass(clk, reset, PipeClearMW, PipeEnableMW, ClassResultM, ClassResultW);
|
||||
flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, ClassResultM, ClassResultW);
|
||||
|
||||
|
||||
|
||||
|
||||
@ -34,7 +34,7 @@ module ifu (
|
||||
input logic [`XLEN-1:0] InstrInF,
|
||||
input logic InstrAckF,
|
||||
output logic [`XLEN-1:0] PCF,
|
||||
output logic [`XLEN-1:0] InstrPAdrF,
|
||||
output logic [`PA_BITS-1:0] InstrPAdrF,
|
||||
output logic InstrReadF,
|
||||
output logic ICacheStallF,
|
||||
// Decode
|
||||
@ -92,10 +92,10 @@ module ifu (
|
||||
logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
|
||||
logic PrivilegedChangePCM;
|
||||
logic IllegalCompInstrD;
|
||||
logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCNextPF, PCPF;
|
||||
logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCPF;
|
||||
logic [`XLEN-3:0] PCPlusUpperF;
|
||||
logic CompressedF;
|
||||
logic [31:0] InstrRawD;
|
||||
logic [31:0] InstrRawD, FinalInstrRawF;
|
||||
localparam [31:0] nop = 32'h00000013; // instruction for NOP
|
||||
logic reset_q; // *** look at this later.
|
||||
|
||||
@ -136,15 +136,15 @@ module ifu (
|
||||
//assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
|
||||
// assign InstrReadF = 1; // *** & ICacheMissF; add later
|
||||
|
||||
// jarred 2021-03-14 Add instrution cache block to remove rd2
|
||||
assign PCNextPF = PCNextF; // Temporary workaround until iTLB is live
|
||||
icache icache(.*);
|
||||
icache icache(.*,
|
||||
.PCNextF(PCNextF[`PA_BITS-1:0]),
|
||||
.PCPF(PCPFmmu));
|
||||
|
||||
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
|
||||
|
||||
|
||||
assign PrivilegedChangePCM = RetM | TrapM;
|
||||
|
||||
//mux3 #(`XLEN) pcmux(PCPlus2or4F, PCCorrectE, PrivilegedNextPCM, {PrivilegedChangePCM, BPPredWrongE}, UnalignedPCNextF);
|
||||
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F),
|
||||
.d1(BPPredPCF),
|
||||
.s(SelBPPredF),
|
||||
@ -160,15 +160,6 @@ module ifu (
|
||||
.s(PrivilegedChangePCM),
|
||||
.y(PCNext2F));
|
||||
|
||||
// *** try to remove this in the future as it can add a long path.
|
||||
// StallF may arrive late.
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
|
||||
.d1(PCF),
|
||||
.s(StallF),
|
||||
.y(PCNext3F));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
mux2 #(`XLEN) pcmux4(.d0(PCNext2F),
|
||||
.d1(`RESET_VECTOR),
|
||||
.s(reset_q),
|
||||
@ -253,6 +244,7 @@ module ifu (
|
||||
// pipeline misaligned faults to M stage
|
||||
assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned
|
||||
flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, BranchMisalignedFaultM);
|
||||
// *** Ross Thompson. Check InstrMisalignedAdrM as I believe it is the same as PCF. Should be able to remove.
|
||||
flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
|
||||
assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM;
|
||||
assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path
|
||||
|
||||
@ -137,7 +137,7 @@ module wallypipelinedhart (
|
||||
logic [`XLEN-1:0] MemAdrM, WriteDataM;
|
||||
logic [`PA_BITS-1:0] MemPAdrM;
|
||||
logic [`XLEN-1:0] ReadDataW;
|
||||
logic [`XLEN-1:0] InstrPAdrF;
|
||||
logic [`PA_BITS-1:0] InstrPAdrF;
|
||||
logic [`XLEN-1:0] InstrRData;
|
||||
logic InstrReadF;
|
||||
logic DataStall;
|
||||
|
||||
@ -554,7 +554,7 @@ string tests32f[] = '{
|
||||
if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
|
||||
else tests = {tests, tests32iNOc};
|
||||
if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
|
||||
// if (`F_SUPPORTED) tests = {tests32f, tests};
|
||||
if (`F_SUPPORTED) tests = {tests32f, tests};
|
||||
if (`A_SUPPORTED) tests = {tests, tests32a};
|
||||
if (`MEM_VIRTMEM) tests = {tests, tests32mmu};
|
||||
end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user