mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added generate around virtual memory hardware in LSU.
This commit is contained in:
Ross Thompson
parent
f09b10a393
commit
13b4201198
@ -203,13 +203,13 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/InterlockCurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncached
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit
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@ -220,7 +220,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr
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@ -328,9 +328,14 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCFetchLine
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCWriteLine
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BUSACK
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/VAdr
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add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
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@ -371,19 +376,16 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pm
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L
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add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWAdr
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
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add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
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add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
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add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
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add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
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add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
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add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
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add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
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add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
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add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
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add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
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@ -462,29 +464,8 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
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add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
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add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
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add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate /testbench/dut/hart/ifu/PCCorrectE
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add wave -noupdate /testbench/dut/hart/ifu/PCSrcE
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add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE
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add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
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add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
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add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM
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add wave -noupdate /testbench/dut/hart/ifu/PCF
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add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR
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add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM
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add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB
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add wave -noupdate /testbench/dut/hart/ifu/temp
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add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM
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add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM
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add wave -noupdate /testbench/dut/hart/lsu/BusCurrState
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add wave -noupdate /testbench/dut/hart/lsu/BasePAdrM
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add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBPAdrM
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add wave -noupdate /testbench/dut/hart/lsu/FetchCountFlag
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add wave -noupdate /testbench/dut/hart/lsu/FetchCount
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add wave -noupdate /testbench/dut/hart/lsu/DCfromAHBAck
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add wave -noupdate /testbench/dut/hart/lsu/BUSACK
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add wave -noupdate /testbench/dut/hart/lsu/DCFetchLine
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {2947 ns} 0}
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WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {207375 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 314
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@ -500,4 +481,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {2791 ns} {3081 ns}
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WaveRestoreZoom {207017 ns} {208185 ns}
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2
wally-pipelined/src/cache/dcache.sv
vendored
2
wally-pipelined/src/cache/dcache.sv
vendored
@ -131,7 +131,7 @@ module dcache
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mux4 #(INDEXLEN)
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AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.d1(0), // *** REMOVE
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.d1(7'b0), // *** REMOVE
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.d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.d3(FlushAdr),
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.s(SelAdrM),
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@ -94,9 +94,7 @@ module lsu
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logic [`XLEN+1:0] IEUAdrExtM;
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logic DTLBMissM;
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logic DTLBWriteM;
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logic HPTWStall;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic HPTWRead;
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logic [1:0] DCRWM;
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logic [1:0] LsuRWM;
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logic [2:0] LsuFunct3M;
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@ -110,17 +108,29 @@ module lsu
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logic CacheableM;
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logic SelHPTW;
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logic [2:0] HPTWSize;
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logic DCCommittedM;
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logic CommittedMfromBus;
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logic AnyCPUReqM;
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logic MemAfterIWalkDone;
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logic BusStall;
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logic InterlockStall;
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logic IgnoreRequest;
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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generate
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if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
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logic AnyCPUReqM;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic HPTWRead;
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logic [2:0] HPTWSize;
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logic SelReplayCPURequest;
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typedef enum {STATE_T0_READY,
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STATE_T0_REPLAY,
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STATE_T3_DTLB_MISS,
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@ -129,11 +139,6 @@ module lsu
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STATE_T7_DITLB_MISS} statetype;
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statetype InterlockCurrState, InterlockNextState;
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logic InterlockStall;
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logic SelReplayCPURequest;
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logic IgnoreRequest;
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assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
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@ -195,7 +200,6 @@ module lsu
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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// *** add generate to conditionally create hptw, lsuArb, and mmu
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// based on `MEM_VIRTMEM
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@ -206,12 +210,6 @@ module lsu
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.HPTWReadPTE(ReadDataM),
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.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM);
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assign LSUStall = DCacheStall | InterlockStall | BusStall;
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// arbiter between IEU and hptw
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// multiplex the outputs to LSU
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@ -219,7 +217,6 @@ module lsu
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mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M);
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mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM);
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mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM);
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assign CPUBusy = StallW & ~SelHPTW;
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@ -235,6 +232,40 @@ module lsu
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//assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM;
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//assign LsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0];
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// Specify which type of page fault is occurring
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// *** `MEM_VIRTMEM
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assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1];
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assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0];
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assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE;
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end // if (`MEM_VIRTMEM)
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else begin
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assign InterlockStall = 1'b0;
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assign DCAdrE = LsuAdrE;
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assign SelHPTW = 1'b0;
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assign IgnoreRequest = 1'b0;
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assign PTE = '0;
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assign PageType = '0;
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assign DTLBWriteM = 1'b0;
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assign ITLBWriteF = 1'b0;
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assign LsuRWM = MemRWM;
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assign LsuFunct3M = Funct3M;
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assign LsuAtomicM = AtomicM;
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assign LsuAdrE = IEUAdrE[11:0];
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assign LsuPAdrM = IEUAdrExtM;
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assign CPUBusy = StallW;
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assign CommittedM = CommittedMfromBus;
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assign DTLBLoadPageFaultM = 1'b0;
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assign DTLBStorePageFaultM = 1'b0;
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end
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endgenerate
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mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
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dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation(SelHPTW),
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@ -256,6 +287,13 @@ module lsu
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
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); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
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assign LSUStall = DCacheStall | InterlockStall | BusStall;
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// If the CPU's (not HPTW's) request is a page fault.
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assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
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assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
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// Move generate from lrsc to outside this module.
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generate
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@ -269,10 +307,6 @@ module lsu
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end
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endgenerate
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// Specify which type of page fault is occurring
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// *** `MEM_VIRTMEM
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assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1];
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assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0];
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// Determine if an Unaligned access is taking place
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// hptw guarantees alignment, only check inputs from IEU.
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@ -284,15 +318,11 @@ module lsu
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2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd
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endcase
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// If the CPU's (not HPTW's) request is a page fault.
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assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
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assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
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// conditional
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// 1. ram // controlled by `MEM_DTIM
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// 2. cache `MEM_DCACHE
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// 3. wire pass-through
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assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE[11:0];
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localparam integer WORDSPERLINE = `DCACHE_BLOCKLENINBITS/`XLEN;
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localparam integer LOGWPL = $clog2(WORDSPERLINE);
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