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vcs testbench

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This commit is contained in:
Divya2030 2024-04-03 10:39:02 -07:00
parent bec35ecd33
commit 135f3b6f8f
2 changed files with 32 additions and 4 deletions
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24
sim/run_vcs.sh Executable file
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@ -0,0 +1,24 @@
#!/bin/bash
# Set CONFIG_VARIANT from the first script argument
#CONFIG_VARIANT=${1:-rv64i}
CONFIG_VARIANT=${1}
# Set TESTSUITE from the second script argument
TESTSUITE=$2
INCLUDE_DIRS=$(find ../src -type d | xargs -I {} echo -n "{} ")
SOURCE_PATH="+incdir+../config/${CONFIG_VARIANT} +incdir+../config/deriv/${CONFIG_VARIANT} +incdir+../config/shared +define+ +define+P.XLEN=64 +define+FPGA=0 +incdir+../testbench ../src/cvw.sv +incdir+../src"
SIMFILES="$INCLUDE_DIRS $(find ../src -name "*.sv" ! -path "../src/generic/clockgater.sv" ! -path "../src/generic/mem/rom1p1r_128x64.sv" ! -path "../src/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "../src/generic/mem/rom1p1r_128x32.sv" ! -path "../src/generic/mem/ram2p1r1wbe_512x64.sv") ../testbench/testbench.sv $(find ../testbench/common -name "*.sv" ! -path "../testbench/common/wallyTracer.sv")"
OUTPUT="sim_out"
clean() {
rm -rf obj_dir work transcript vsim.wlf $OUTPUT *.vcd csrc ucli.key vc_hdrs.h program.out
rm -rf simv* *.daidir dve *.vpd *.dump DVEfiles/ verdi* novas* *fsdb* *.vg *.rep *.db *.chk *.log *.out profileReport* simprofile_dir*
}
# Clean and run simulation with VCS
clean
vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
./$OUTPUT | tee program.out

12
testbench/testbench.sv
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@ -299,9 +299,11 @@ module testbench;
// Find the test vector files and populate the PC to function label converter // Find the test vector files and populate the PC to function label converter
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
logic [P.XLEN-1:0] testadr; logic [P.XLEN-1:0] testadr;
assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; always_comb begin
assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"]; begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
assign signature_size = end_signature_addr - begin_signature_addr; end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
signature_size = end_signature_addr - begin_signature_addr;
end
always @(posedge clk) begin always @(posedge clk) begin
if(SelectTest) begin if(SelectTest) begin
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
@ -556,7 +558,8 @@ module testbench;
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
else assign ecf = 0; else assign ecf = 0;
assign TestComplete = ecf & always_comb begin
TestComplete = ecf &
(dut.core.ieu.dp.regf.rf[3] == 1 | (dut.core.ieu.dp.regf.rf[3] == 1 |
(dut.core.ieu.dp.regf.we3 & (dut.core.ieu.dp.regf.we3 &
dut.core.ieu.dp.regf.a3 == 3 & dut.core.ieu.dp.regf.a3 == 3 &
@ -564,6 +567,7 @@ module testbench;
((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
//assign DCacheFlushStart = TestComplete; //assign DCacheFlushStart = TestComplete;
end
DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));