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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-02-08 14:22:19 -06:00
commit 13561c67bd
3 changed files with 11 additions and 14 deletions
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4
pipelined/config/rv32e/wally-config.vh
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@ -49,8 +49,8 @@
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// *** replace with MEM_BUS
`define DMEM `MEM_CACHE
`define IMEM `MEM_CACHE
`define DMEM `MEM_BUS
`define IMEM `MEM_BUS
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 0

1
pipelined/src/cache/sram1rw.sv vendored
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@ -46,6 +46,7 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
logic WriteEnableD;
//*** model as single port
// *** merge with simpleram
always_ff @(posedge clk) begin
AddrD <= Adr;
WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay. Implement alternative cache stall to avoid this. Eliminates a bunch of delay flops elsewhere

18
pipelined/src/generic/flop/simpleram.sv
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@ -40,18 +40,14 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
/* verilator lint_off WIDTH */
if (`XLEN == 64) begin:ramrw
// discard bottom 2 or 3 bits of address offset within word or doubleword
localparam adrlsb = (`XLEN==64) ? 3 : 2;
logic [31:adrlsb] adrmsbs;
assign adrmsbs = a[31:adrlsb];
always_ff @(posedge clk) begin
rd <= RAM[a[31:3]];
if (we) RAM[a[31:3]] <= #1 wd;
rd <= RAM[adrmsbs];
if (we) RAM[adrmsbs] <= #1 wd;
end
end else begin
always_ff @(posedge clk) begin:ramrw
rd <= RAM[a[31:2]];
if (we) RAM[a[31:2]] <= #1 wd;
end
end
/* verilator lint_on WIDTH */
endmodule