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	Make entire cache write path conditional on READ_ONLY_CACHE
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								src/cache/cache.sv
									
									
									
									
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								src/cache/cache.sv
									
									
									
									
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							@ -96,8 +96,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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  logic [LINELEN-1:0]            ReadDataLine, ReadDataLineCache;
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					  logic [LINELEN-1:0]            ReadDataLine, ReadDataLineCache;
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  logic                          SelFetchBuffer;
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					  logic                          SelFetchBuffer;
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  logic                          CacheEn;
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					  logic                          CacheEn;
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  logic [CACHEWORDSPERLINE-1:0]  MemPAdrDecoded;
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					  logic [LINELEN/8-1:0]          LineByteMask;
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  logic [LINELEN/8-1:0]          LineByteMask, DemuxedByteMask, FetchBufferByteSel;
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  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
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					  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
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  genvar                         index;
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					  genvar                         index;
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@ -161,15 +160,17 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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  /////////////////////////////////////////////////////////////////////////////////////////////
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					  /////////////////////////////////////////////////////////////////////////////////////////////
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  // Write Path
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					  // Write Path
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  /////////////////////////////////////////////////////////////////////////////////////////////
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					  /////////////////////////////////////////////////////////////////////////////////////////////
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  // Adjust byte mask from word to cache line
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  onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
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  for(index = 0; index < 2**LOGCWPL; index++) begin
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    assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
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  end
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  assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask;  // If load miss set all muxes to 1.
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  if(!READ_ONLY_CACHE) begin:WriteSelLogic
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					  if(!READ_ONLY_CACHE) begin:WriteSelLogic
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					    logic [CACHEWORDSPERLINE-1:0]  MemPAdrDecoded;
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					    logic [LINELEN/8-1:0]          DemuxedByteMask, FetchBufferByteSel;
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					    // Adjust byte mask from word to cache line
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					    onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
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					    for(index = 0; index < 2**LOGCWPL; index++) begin
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					       assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
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					    end
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					    assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask;  // If load miss set all muxes to 1.
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    // Merge write data into fetched cache line for store miss
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					    // Merge write data into fetched cache line for store miss
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    for(index = 0; index < LINELEN/8; index++) begin
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					    for(index = 0; index < LINELEN/8; index++) begin
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       mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
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					       mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
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