diff --git a/.gitignore b/.gitignore
index cd827ed9d..4225869cd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,6 +8,7 @@ __pycache__/
 
 #External repos
 addins
+addins/riscv-arch-test/Makefile.include
 
 #vsim work files to ignore
 transcript
@@ -43,3 +44,7 @@ fpga/generator/WallyFPGA*
 fpga/generator/reports/
 fpga/generator/*.log
 fpga/generator/*.jou
+*.objdump*
+*.signature.output
+examples/asm/sumtest/sumtest
+
diff --git a/.gitmodules b/.gitmodules
index 9dcec4f5d..0182e1388 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,6 +4,7 @@
 [submodule "addins/riscv-arch-test"]
 	path = addins/riscv-arch-test
 	url = https://github.com/riscv-non-isa/riscv-arch-test
+	ignore = dirty
 [submodule "addins/imperas-riscv-tests"]
 	path = addins/imperas-riscv-tests
 	url = https://github.com/riscv-ovpsim/imperas-riscv-tests