Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 17:55:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

Synthesis with derived configs

Browse Source
This commit is contained in:
David Harris 2024-04-27 17:06:44 -07:00
parent 2b50b30f23
commit 12c5879467
4 changed files with 20 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
config/derivlist.txt
View File

@ -89,29 +89,29 @@ deriv syn_sram_rv64i rv64i syn_sram_rv32e
deriv syn_sram_rv64gc rv64gc syn_sram_rv32e deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
# The following syn configurations gradually turn off features # The following syn configurations gradually turn off features
deriv syn_pmp0_rv64gc syn_rv64gc deriv syn_rv64gc_pmp0 syn_rv64gc
PMP_ENTRIES 32'd0 PMP_ENTRIES 32'd0
deriv syn_sram_pmp0_rv64gc syn_sram_rv64gc deriv syn_sram_rv64gc_pmp0 syn_sram_rv64gc
PMP_ENTRIES 32'd0 PMP_ENTRIES 32'd0
deriv syn_noPriv_rv64gc syn_pmp0_rv64gc deriv syn_rv64gc_noPriv syn_rv64gc_pmp0
ZICSR_SUPPORTED 0 ZICSR_SUPPORTED 0
deriv syn_sram_noPriv_rv64gc syn_sram_pmp0_rv64gc deriv syn_sram_rv64gc_noPriv syn_sram_rv64gc_pmp0
ZICSR_SUPPORTED 0 ZICSR_SUPPORTED 0
deriv syn_noFPU_rv64gc syn_noPriv_rv64gc deriv syn_rv64gc_noFPU syn_rv64gc_noPriv
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
deriv syn_sram_noFPU_rv64gc syn_sram_noPriv_rv64gc deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
deriv syn_noMulDiv_rv64gc syn_noFPU_rv64gc deriv syn_rv64gc_noMulDiv syn_rv64gc_noFPU
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
deriv syn_sram_noMulDiv_rv64gc syn_sram_noFPU_rv64gc deriv syn_sram_rv64gc_noMulDiv syn_sram_rv64gc_noFPU
MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
deriv syn_noAtomic_rv64gc syn_noMulDiv_rv64gc deriv syn_rv64gc_noAtomic syn_rv64gc_noMulDiv
MISA (32'h00000104 | 1 << 18 | 1 << 20) MISA (32'h00000104 | 1 << 18 | 1 << 20)
deriv syn_sram_noAtomic_rv64gc syn_sram_noMulDiv_rv64gc deriv syn_sram_rv64gc_noAtomic syn_sram_rv64gc_noMulDiv
MISA (32'h00000104 | 1 << 18 | 1 << 20) MISA (32'h00000104 | 1 << 18 | 1 << 20)
# Divider variants to check logical correctness # Divider variants to check logical correctness

4
synthDC/Makefile
View File

@ -44,7 +44,11 @@ configs: $(CONFIG)
$(CONFIG): $(CONFIG):
@echo $(CONFIG) @echo $(CONFIG)
cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR) cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
ifeq ($(MOD), orig)
cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)/config.vh $(CONFIGDIR) | true cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)/config.vh $(CONFIGDIR) | true
else
cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)_$(MOD)/config.vh $(CONFIGDIR) | true
endif
ifeq ($(SAIFPOWER), 1) ifeq ($(SAIFPOWER), 1)
cp -f ../sim/power.saif . cp -f ../sim/power.saif .

5
synthDC/extractSummary.py
View File

@ -33,6 +33,9 @@ def synthsintocsv():
for oneSynth in allSynths: for oneSynth in allSynths:
descrip = specReg.findall(oneSynth) descrip = specReg.findall(oneSynth)
print("From " + oneSynth + " Find ")
for d in descrip:
print(d)
if (descrip[3] == "sram"): if (descrip[3] == "sram"):
base = 4 base = 4
else: else:
@ -46,10 +49,12 @@ def synthsintocsv():
descrip = descrip[1:] descrip = descrip[1:]
tech = descrip[base+1][:-2] tech = descrip[base+1][:-2]
freq = descrip[base+2] freq = descrip[base+2]
# print(width, config, mod, tech, freq)
metrics = [] metrics = []
for phrase in ['Path Slack', 'Design Area']: for phrase in ['Path Slack', 'Design Area']:
bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*' bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*'
bashCommand = bashCommand.format(phrase) bashCommand = bashCommand.format(phrase)
print(bashCommand)
try: try:
output = subprocess.check_output(['bash','-c', bashCommand]) output = subprocess.check_output(['bash','-c', bashCommand])
nums = metricReg.findall(str(output)) nums = metricReg.findall(str(output))

4
synthDC/wallySynth.py
View File

@ -11,8 +11,6 @@ def runSynth(config, mod, tech, freq, maxopt, usesram):
prefix = "syn_sram_" prefix = "syn_sram_"
else: else:
prefix = "syn_" prefix = "syn_"
if (mod != "orig"):
prefix = prefix+mod+"_"
cfg = prefix + config cfg = prefix + config
command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(cfg, mod, tech, freq, maxopt, usesram) command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(cfg, mod, tech, freq, maxopt, usesram)
pool.map(mask, [command]) pool.map(mask, [command])
@ -63,7 +61,7 @@ if __name__ == '__main__':
defaultfreq = 500 if tech == 'sky90' else 1500 defaultfreq = 500 if tech == 'sky90' else 1500
freq = args.targetfreq if args.targetfreq else defaultfreq freq = args.targetfreq if args.targetfreq else defaultfreq
config = args.version if args.version else 'rv64gc' config = args.version if args.version else 'rv64gc'
for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'PMP0']: for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'pmp0']:
runSynth(config, mod, tech, freq, maxopt, usesram) runSynth(config, mod, tech, freq, maxopt, usesram)
else: else:
defaultfreq = 500 if tech == 'sky90' else 1500 defaultfreq = 500 if tech == 'sky90' else 1500