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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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Ross Thompson 2022-10-22 16:27:30 -05:00
commit 12c5525807
1 changed files with 1 additions and 1 deletions
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pipelined/src/uncore/uartPC16550D.sv
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@ -357,7 +357,7 @@ module uartPC16550D(
(rxfifohead + 16 - rxfifotail); (rxfifohead + 16 - rxfifotail);
// verilator lint_on WIDTH // verilator lint_on WIDTH
assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel; assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel;
assign rxfifotimeout = rxtimeoutcnt[6]; // time out after 4 character periods; *** probably not right yet assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; *** probably not right yet
//assign rxfifotimeout = 0; // disabled pending fix //assign rxfifotimeout = 0; // disabled pending fix
// detect any errors in rx fifo // detect any errors in rx fifo