From 12af05da02430c44ef6120b19b3335b2429980dc Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Tue, 13 Jun 2023 22:08:06 -0700 Subject: [PATCH] Update csrm.sv Program clean up --- src/privileged/csrm.sv | 49 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 54cc288c5..4d17f0cfd 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -47,14 +47,19 @@ module csrm import cvw::*; #(parameter cvw_t P) ( output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0], output logic WriteMSTATUSM, WriteMSTATUSHM, - output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM + output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM, + output logic MENVCFG_STCE ); logic [P.XLEN-1:0] MISA_REGW, MHARTID_REGW; logic [P.XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW; + logic [63:0] MENVCFG_REGW; + logic [P.XLEN-1:0] MENVCFGH_REGW; + logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; + logic WriteMENVCFGM; // Machine CSRs localparam MVENDORID = 12'hF11; @@ -69,7 +74,9 @@ module csrm import cvw::*; #(parameter cvw_t P) ( localparam MIE = 12'h304; localparam MTVEC = 12'h305; localparam MCOUNTEREN = 12'h306; + localparam MENVCFG = 12'h30A; localparam MSTATUSH = 12'h310; + localparam MENVCFGH = 12'h31A; localparam MCOUNTINHIBIT = 12'h320; localparam MSCRATCH = 12'h340; localparam MEPC = 12'h341; @@ -90,7 +97,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( localparam DSCRATCH0 = 12'h7B2; localparam DSCRATCH1 = 12'h7B3; // Constants - localparam ZERO = {(P.XLEN){1'b0}}; + localparam ZERO = {(P.XLEN){1'b0}}; localparam MEDELEG_MASK = 16'hB3FF; localparam MIDELEG_MASK = 12'h222; // we choose to not make machine interrupts delegable @@ -131,7 +138,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( // Write machine Mode CSRs assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS); - assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH)& (P.XLEN==32); + assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH) & (P.XLEN==32); assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC); assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG); assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG); @@ -140,6 +147,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)); assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)); assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN); + assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG); assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT); assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID); @@ -161,6 +169,39 @@ module csrm import cvw::*; #(parameter cvw_t P) ( flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); end else assign MCOUNTEREN_REGW = '0; + // MENVCFG is always 64 bits even for RV32 + assign MENVCFG_WriteValM = { + MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED, + MENVCFG_PreWriteValM[62] & P.SVPBMT_SUPPORTED, + 54'b0, + MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED, + MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}}, + 3'b0, + MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED + }; + + if (P.XLEN == 64) begin + assign MENVCFG_PreWriteValM = CSRWriteValM; + flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW); + assign MENVCFGH_REGW = 0; + end else begin + logic WriteMENVCFGHM; + assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM}; + assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32); + flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM[31:0], MENVCFG_REGW[31:0]); + flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]); + assign MENVCFGH_REGW = MENVCFG_REGW[63:32]; + end + + // Extract bit fields + assign MENVCFG_STCE = MENVCFG_REGW[63]; + // Uncomment these other fields when they are defined + // assign MENVCFG_PBMTE = MENVCFG_REGW[62]; + // assign MENVCFG_CBZE = MENVCFG_REGW[7]; + // assign MENVCFG_CBCFE = MENVCFG_REGW[6]; + // assign MENVCFG_CBIE = MENVCFG_REGW[5:4]; + // assign MENVCFG_FIOM = MENVCFG_REGW[0]; + // Read machine mode CSRs // verilator lint_off WIDTH logic [5:0] entry; @@ -200,6 +241,8 @@ module csrm import cvw::*; #(parameter cvw_t P) ( MTVAL: CSRMReadValM = MTVAL_REGW; MTINST: CSRMReadValM = 0; // implemented as trivial zero MCOUNTEREN: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW}; + MENVCFG: CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0]; + MENVCFGH: CSRMReadValM = MENVCFGH_REGW; MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW}; default: begin