diff --git a/sim/imperas.ic b/sim/imperas.ic
index 6ea5725a0..3ad843cf4 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -68,6 +68,9 @@
 --override cpu/PMP_registers=16
 --override cpu/PMP_undefined=T
 
+# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception
+--override cpu/mstatus_fs_mode=rvfs_write_nz
+
 # PMA Settings 
 # 'r': read access allowed
 # 'w': write access allowed
@@ -101,7 +104,7 @@
 
 # Add Imperas simulator application instruction tracing
 # uncomment these to provide tracing
-#--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000
+--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000
 --override cpu/debugflags=6 --override cpu/verbose=1
 --override cpu/show_c_prefix=T
 
diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
index 13dedffa2..ad3dab32d 100644
--- a/src/privileged/csr.sv
+++ b/src/privileged/csr.sv
@@ -110,7 +110,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   logic                    WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
   logic                    CSRMWriteM, CSRSWriteM, CSRUWriteM;
   logic                    UngatedCSRMWriteM;
-  logic                    WriteFRMM, WriteFFLAGSM;
+  logic                    WriteFRMM, SetOrWriteFFLAGSM;
   logic [P.XLEN-1:0]       UnalignedNextEPCM, NextEPCM, NextMtvalM;
   logic [4:0]              NextCauseM;
   logic [11:0]             CSRAdrM;
@@ -222,7 +222,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   csrsr #(P) csrsr(.clk, .reset, .StallW, 
     .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, 
     .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
-    .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .SelHPTW,
+    .mretM, .sretM, .WriteFRMM, .SetOrWriteFFLAGSM, .CSRWriteValM, .SelHPTW,
     .MSTATUS_REGW, .SSTATUS_REGW, .MSTATUSH_REGW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
@@ -267,14 +267,14 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   if (P.F_SUPPORTED) begin:csru
     csru #(P) csru(.clk, .reset, .InstrValidNotFlushedM, 
       .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,  
-      .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
+      .SetFflagsM, .FRM_REGW, .WriteFRMM, .SetOrWriteFFLAGSM,
       .IllegalCSRUAccessM);
   end else begin
     assign FRM_REGW = '0;
     assign CSRUReadValM = '0;
     assign IllegalCSRUAccessM = 1'b1;
     assign WriteFRMM = 1'b0;
-    assign WriteFFLAGSM = 1'b0;
+    assign SetOrWriteFFLAGSM = 1'b0;
   end
   
   if (P.ZICNTR_SUPPORTED) begin:counters
diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
index dc970921e..d0a7b00c6 100644
--- a/src/privileged/csrsr.sv
+++ b/src/privileged/csrsr.sv
@@ -34,7 +34,7 @@ module csrsr import cvw::*;  #(parameter cvw_t P) (
   input  logic              TrapM, FRegWriteM,
   input  logic [1:0]        NextPrivilegeModeM, PrivilegeModeW,
   input  logic              mretM, sretM, 
-  input  logic              WriteFRMM, WriteFFLAGSM,
+  input  logic              WriteFRMM, SetOrWriteFFLAGSM,
   input  logic [P.XLEN-1:0] CSRWriteValM,
   input  logic              SelHPTW,
   output logic [P.XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW,
@@ -209,6 +209,6 @@ module csrsr import cvw::*;  #(parameter cvw_t P) (
         STATUS_SPIE     <= P.S_SUPPORTED & CSRWriteValM[5];
         STATUS_SIE      <= P.S_SUPPORTED & CSRWriteValM[1];
         STATUS_UBE      <= CSRWriteValM[6] & P.U_SUPPORTED & P.BIGENDIAN_SUPPORTED;
-      end else if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= 2'b11; 
+      end else if (FRegWriteM | WriteFRMM | SetOrWriteFFLAGSM) STATUS_FS_INT <= 2'b11; 
     end
 endmodule
diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv
index eeb364a89..86a9089e8 100644
--- a/src/privileged/csru.sv
+++ b/src/privileged/csru.sv
@@ -37,7 +37,7 @@ module csru import cvw::*;  #(parameter cvw_t P) (
   output logic [P.XLEN-1:0] CSRUReadValM,  
   input  logic [4:0]        SetFflagsM,
   output logic [2:0]        FRM_REGW,
-  output logic              WriteFRMM, WriteFFLAGSM,
+  output logic              WriteFRMM, SetOrWriteFFLAGSM,
   output logic              IllegalCSRUAccessM
 );
 
@@ -48,7 +48,7 @@ module csru import cvw::*;  #(parameter cvw_t P) (
   logic [4:0]               FFLAGS_REGW;
   logic [2:0]               NextFRMM;
   logic [4:0]               NextFFLAGSM;
-  logic                     SetOrWriteFFLAGSM;
+  logic                     WriteFFLAGSM;
   
   // Write enables
   assign WriteFRMM    = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR);