Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Removed redundant signals from cache.

Browse Source
This commit is contained in:
Ross Thompson 2022-02-11 22:23:47 -06:00
parent 52894a7a4f
commit 1255e82154
2 changed files with 53 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
pipelined/src/cache/cache.sv vendored
View File

@ -175,9 +175,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
// *** change to structural // *** change to structural
mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, {SelFlush, FSMLineWriteEn}, SelectedWay); mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, {SelFlush, FSMLineWriteEn}, SelectedWay);
assign SetValidWay = SetValid ? SelectedWay : '0; assign SetValidWay = FSMLineWriteEn ? SelectedWay : '0;
assign ClearValidWay = ClearValid ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0;
assign SetDirtyWay = SetDirty ? SelectedWay : '0; assign SetDirtyWay = FSMWordWriteEn ? SelectedWay : '0;
assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; assign ClearDirtyWay = ClearDirty ? SelectedWay : '0;
assign WriteWordWayEn = FSMWordWriteEn ? SelectedWay : '0; assign WriteWordWayEn = FSMWordWriteEn ? SelectedWay : '0;
assign WriteLineWayEn = FSMLineWriteEn ? SelectedWay : '0; assign WriteLineWayEn = FSMLineWriteEn ? SelectedWay : '0;
@ -190,8 +190,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
.RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr, .SetValid, .CacheMiss, .CacheAccess, .SelAdr,
.ClearValid, .SetDirty, .ClearDirty, .FSMWordWriteEn, .ClearValid, .ClearDirty, .FSMWordWriteEn,
.FSMLineWriteEn, .SelEvict, .SelFlush, .FSMLineWriteEn, .SelEvict, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,

109
pipelined/src/cache/cachefsm.sv vendored
View File

@ -62,9 +62,7 @@ module cachefsm
// dcache internals // dcache internals
output logic [1:0] SelAdr, output logic [1:0] SelAdr,
output logic SetValid,
output logic ClearValid, output logic ClearValid,
output logic SetDirty,
output logic ClearDirty, output logic ClearDirty,
output logic FSMWordWriteEn, output logic FSMWordWriteEn,
output logic FSMLineWriteEn, output logic FSMLineWriteEn,
@ -78,12 +76,11 @@ module cachefsm
output logic save, output logic save,
output logic restore); output logic restore);
logic [1:0] PreSelAdr;
logic resetDelay; logic resetDelay;
logic AMO; logic AMO;
logic DoAMO, DoRead, DoWrite, DoFlush; logic DoAMO, DoRead, DoWrite, DoFlush;
logic DoAMOHit, DoReadHit, DoWriteHit, DoAnyUpdateHit, DoAnyHit; logic DoAnyUpdateHit, DoAnyHit;
logic DoAMOMiss, DoReadMiss, DoWriteMiss, DoAnyMiss; logic DoAnyMiss;
logic FlushFlag, FlushWayAndNotAdrFlag; logic FlushFlag, FlushWayAndNotAdrFlag;
typedef enum logic [3:0] {STATE_READY, typedef enum logic [3:0] {STATE_READY,
@ -111,22 +108,15 @@ module cachefsm
// if the command is used in the READY state then the cache needs to be able to supress // if the command is used in the READY state then the cache needs to be able to supress
// using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB. // using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB.
// need to re organize all of these. Low priority though.
assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation. assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation.
assign AMO = Atomic[1] & (&RW); assign AMO = Atomic[1] & (&RW);
assign DoAMO = AMO & ~IgnoreRequest; assign DoAMO = AMO & ~IgnoreRequest;
assign DoAMOHit = DoAMO & CacheHit;
assign DoAMOMiss = DoAMO & ~CacheHit;
assign DoRead = RW[1] & ~IgnoreRequest; assign DoRead = RW[1] & ~IgnoreRequest;
assign DoReadHit = DoRead & CacheHit;
assign DoReadMiss = DoRead & ~CacheHit;
assign DoWrite = RW[0] & ~IgnoreRequest; assign DoWrite = RW[0] & ~IgnoreRequest;
assign DoWriteHit = DoWrite & CacheHit;
assign DoWriteMiss = DoWrite & ~CacheHit;
assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit; assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit;
assign DoAnyUpdateHit = DoAMOHit | DoWriteHit; assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit;
assign DoAnyHit = DoAnyUpdateHit | DoReadHit; assign DoAnyHit = DoAnyUpdateHit | (DoRead & CacheHit);
assign FlushFlag = FlushAdrFlag & FlushWayFlag; assign FlushFlag = FlushAdrFlag & FlushWayFlag;
// outputs for the performance counters. // outputs for the performance counters.
@ -137,7 +127,6 @@ module cachefsm
// PCNextF will no longer be pointing to the correct address. // PCNextF will no longer be pointing to the correct address.
// But PCF will be the reset vector. // But PCF will be the reset vector.
flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay)); flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
assign SelAdr = resetDelay ? 2'b01 : PreSelAdr;
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset) CurrState <= #1 STATE_READY; if (reset) CurrState <= #1 STATE_READY;
@ -146,39 +135,39 @@ module cachefsm
always_comb begin always_comb begin
NextState = STATE_READY; NextState = STATE_READY;
case (CurrState) case (CurrState)
STATE_READY: if(IgnoreRequest) NextState = STATE_READY; STATE_READY: if(IgnoreRequest) NextState = STATE_READY;
else if(DoFlush) NextState = STATE_FLUSH; else if(DoFlush) NextState = STATE_FLUSH;
else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY; else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY;
else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE; STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_FETCH_DONE;
else NextState = STATE_MISS_FETCH_WDV; else NextState = STATE_MISS_FETCH_WDV;
STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
else NextState = STATE_MISS_WRITE_CACHE_LINE; else NextState = STATE_MISS_WRITE_CACHE_LINE;
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD;
STATE_MISS_READ_WORD: if (RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; STATE_MISS_READ_WORD: if(RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD;
else NextState = STATE_MISS_READ_WORD_DELAY; else NextState = STATE_MISS_READ_WORD_DELAY;
STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY; STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY;
else if(CPUBusy) NextState = STATE_CPU_BUSY; else if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
else NextState = STATE_MISS_EVICT_DIRTY; else NextState = STATE_MISS_EVICT_DIRTY;
STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY; STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_FLUSH: NextState = STATE_FLUSH_CHECK; STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK;
else if (FlushFlag) NextState = STATE_READY; else if(FlushFlag) NextState = STATE_READY;
else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
else NextState = STATE_FLUSH_CHECK; else NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY; STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY;
else NextState = STATE_FLUSH_WRITE_BACK; else NextState = STATE_FLUSH_WRITE_BACK;
STATE_FLUSH_CLEAR_DIRTY: if(FlushAdrFlag & FlushWayFlag) NextState = STATE_READY; STATE_FLUSH_CLEAR_DIRTY: if(FlushFlag) NextState = STATE_READY;
else if (FlushWayFlag) NextState = STATE_FLUSH_INCR; else if(FlushWayFlag) NextState = STATE_FLUSH_INCR;
else NextState = STATE_FLUSH_CHECK; else NextState = STATE_FLUSH_CHECK;
default: NextState = STATE_READY; default: NextState = STATE_READY;
endcase endcase
end end
@ -196,21 +185,19 @@ module cachefsm
(CurrState == STATE_FLUSH_WRITE_BACK) | (CurrState == STATE_FLUSH_WRITE_BACK) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
// write enables internal to cache // write enables internal to cache
assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; assign FSMLineWriteEn = CurrState == STATE_MISS_WRITE_CACHE_LINE;
assign ClearValid = '0; assign ClearValid = '0;
assign SetDirty = (CurrState == STATE_READY & DoAMO) | assign FSMWordWriteEn = (CurrState == STATE_READY & DoAnyUpdateHit) |
(CurrState == STATE_READY & DoWrite) |
(CurrState == STATE_MISS_READ_WORD_DELAY & AMO) |
(CurrState == STATE_MISS_WRITE_WORD);
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAnyUpdateHit)) |
(CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) |
(CurrState == STATE_MISS_WRITE_WORD); (CurrState == STATE_MISS_WRITE_WORD);
assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE);
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) | assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) |
(CurrState == STATE_MISS_READ_WORD_DELAY) | (CurrState == STATE_MISS_READ_WORD_DELAY) |
(CurrState == STATE_MISS_WRITE_WORD); (CurrState == STATE_MISS_WRITE_WORD);
// Flush and eviction controls // Flush and eviction controls
assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY); assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY);
assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
@ -220,7 +207,7 @@ module cachefsm
assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayAndNotAdrFlag) | assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayAndNotAdrFlag) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayAndNotAdrFlag); (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayAndNotAdrFlag);
assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) | assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~FlushFlag);
assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushAdrCntRst = (CurrState == STATE_READY);
assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
// Bus interface controls // Bus interface controls
@ -234,7 +221,8 @@ module cachefsm
(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
// **** can this be simplified? // **** can this be simplified?
assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. assign SelAdr = ((CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss.
// use the raw requests as we don't want IgnoreRequestTrapM in the critical path
(CurrState == STATE_READY & (AMO & CacheHit)) | (CurrState == STATE_READY & (AMO & CacheHit)) |
(CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | (CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) |
(CurrState == STATE_READY & (RW[0] & CacheHit)) | (CurrState == STATE_READY & (RW[0] & CacheHit)) |
@ -245,7 +233,8 @@ module cachefsm
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) |
(CurrState == STATE_MISS_WRITE_WORD) | (CurrState == STATE_MISS_WRITE_WORD) |
(CurrState == STATE_MISS_EVICT_DIRTY) | (CurrState == STATE_MISS_EVICT_DIRTY) |
(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY))) ? 2'b01 : (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |
resetDelay) ? 2'b01 :
((CurrState == STATE_FLUSH) | ((CurrState == STATE_FLUSH) |
(CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) | (CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) |
(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_INCR) |