diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
index e838c6ea1..145b2513d 100644
--- a/src/ieu/bmu/bmuctrl.sv
+++ b/src/ieu/bmu/bmuctrl.sv
@@ -41,6 +41,7 @@ module bmuctrl(
   output logic        BRegWriteD,              // Indicates if it is a R type B instruction
   output logic        BW64D,                   // Indiciates if it is a W type B instruction
   output logic        BALUOpD,                 // Indicates if it is an ALU B instruction
+  output logic        IllegalBitmanipInstrD,   // Indicates if it is unrecognized B instruction
   // Execute stage control signals             
   input  logic 	      StallE, FlushE,          // Stall, flush Execute stage
   output logic [2:0]  ALUSelectE,
@@ -54,7 +55,7 @@ module bmuctrl(
   logic [6:0] Funct7D;                         // Funct7 field in Decode stage
   logic [4:0] Rs2D;                            // Rs2 source register in Decode stage
 
-  `define BMUCTRLW 13
+  `define BMUCTRLW 14
 
   logic [`BMUCTRLW-1:0] BMUControlsD;                 // Main B Instructions Decoder control signals
 
@@ -70,92 +71,92 @@ module bmuctrl(
     casez({OpD, Funct7D, Funct3D})
     // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp
       // ZBS
-      17'b0010011_0100100_001:   BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1;  // bclri
+      17'b0010011_0100100_001:   BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0;  // bclri
       17'b0010011_0100101_001: if (`XLEN == 64)
-                                 BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1;  // bclri (rv64)
+                                 BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0;  // bclri (rv64)
                                else
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
-      17'b0010011_0100100_101:   BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1;  // bexti
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
+      17'b0010011_0100100_101:   BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0;  // bexti
       17'b0010011_0100101_101: if (`XLEN == 64)
-                                 BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1;  // bexti (rv64)
+                                 BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0;  // bexti (rv64)
                                else
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
-      17'b0010011_0110100_001:   BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1;  // binvi
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
+      17'b0010011_0110100_001:   BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0;  // binvi
       17'b0010011_0110101_001: if (`XLEN == 64)
-                                 BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1;  // binvi (rv64)
+                                 BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0;  // binvi (rv64)
                                else 
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
-      17'b0010011_0010100_001:   BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1;  // bseti
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
+      17'b0010011_0010100_001:   BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0;  // bseti
       17'b0010011_0010101_001: if (`XLEN == 64) 
-                                 BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1;  // bseti (rv64)
+                                 BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0;  // bseti (rv64)
                                else 
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
-      17'b0110011_0100100_001:   BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1;  // bclr
-      17'b0110011_0100100_101:   BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1;  // bext
-      17'b0110011_0110100_001:   BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1;  // binv
-      17'b0110011_0010100_001:   BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1;  // bset
-      17'b0?1?011_0?0000?_?01:   BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1;  // sra, srai, srl, srli, sll, slli
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
+      17'b0110011_0100100_001:   BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0;  // bclr
+      17'b0110011_0100100_101:   BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0;  // bext
+      17'b0110011_0110100_001:   BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0;  // binv
+      17'b0110011_0010100_001:   BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0;  // bset
+      17'b0?1?011_0?0000?_?01:   BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0;  // sra, srai, srl, srli, sll, slli
       // ZBC
-      17'b0110011_0000101_0??:   BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1;  // ZBC instruction
+      17'b0110011_0000101_0??:   BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0;  // ZBC instruction
       // ZBA
-      17'b0110011_0010000_010:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1;  // sh1add
-      17'b0110011_0010000_100:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1;  // sh2add
-      17'b0110011_0010000_110:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1;  // sh3add
-      17'b0111011_0010000_010:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1;  // sh1add.uw
-      17'b0111011_0010000_100:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1;  // sh2add.uw
-      17'b0111011_0010000_110:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1;  // sh3add.uw
-      17'b0111011_0000100_000:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1;  // add.uw
-      17'b0011011_000010?_001:   BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1;  // slli.uw
+      17'b0110011_0010000_010:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0;  // sh1add
+      17'b0110011_0010000_100:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0;  // sh2add
+      17'b0110011_0010000_110:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0;  // sh3add
+      17'b0111011_0010000_010:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0;  // sh1add.uw
+      17'b0111011_0010000_100:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0;  // sh2add.uw
+      17'b0111011_0010000_110:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0;  // sh3add.uw
+      17'b0111011_0000100_000:   BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0;  // add.uw
+      17'b0011011_000010?_001:   BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0;  // slli.uw
       // ZBB
-      17'b0110011_0110000_001:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1;  // rol
-      17'b0111011_0110000_001:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1;  // rolw
-      17'b0110011_0110000_101:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1;  // ror
-      17'b0111011_0110000_101:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1;  // rorw
-      17'b0010011_0110000_101:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1;  // rori (rv32)
+      17'b0110011_0110000_001:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0;  // rol
+      17'b0111011_0110000_001:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0;  // rolw
+      17'b0110011_0110000_101:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0;  // ror
+      17'b0111011_0110000_101:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0;  // rorw
+      17'b0010011_0110000_101:   BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0;  // rori (rv32)
       17'b0010011_0110001_101: if (`XLEN == 64) 
-                                 BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1;  // rori (rv64)
+                                 BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0;  // rori (rv64)
                                else
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
       17'b0011011_0110000_101: if (`XLEN == 64) 
-                                 BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1;  // roriw 
+                                 BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0;  // roriw 
                                else
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
       17'b0010011_0110000_001: if (Rs2D[2])
-                                 BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1;  // sign extend instruction
+                                 BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0;  // sign extend instruction
                                else 
-                                 BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1;  // count instruction
-      17'b0011011_0110000_001:   BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1;  // count word instruction
+                                 BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0;  // count instruction
+      17'b0011011_0110000_001:   BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0;  // count word instruction
       17'b0111011_0000100_100: if (`XLEN == 64)
-                                 BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1;  // zexth (rv64)
+                                 BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0;  // zexth (rv64)
                                else 
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
       17'b0110011_0000100_100: if (`XLEN == 32)
-                                 BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1;  // zexth (rv32)
+                                 BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0;  // zexth (rv32)
                                else 
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
-      17'b0110011_0100000_111:   BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1;  // andn
-      17'b0110011_0100000_110:   BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1;  // orn
-      17'b0110011_0100000_100:   BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1;  // xnor
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
+      17'b0110011_0100000_111:   BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_0;  // andn
+      17'b0110011_0100000_110:   BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_0;  // orn
+      17'b0110011_0100000_100:   BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_0;  // xnor
       17'b0010011_0110101_101: if (`XLEN == 64) 
-                                 BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1;  // rev8 (rv64)
+                                 BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0;  // rev8 (rv64)
                                else 
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
       17'b0010011_0110100_101: if (`XLEN == 32) 
-                                 BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1;  // rev8 (rv32)
+                                 BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0;  // rev8 (rv32)
                                else 
-                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0;  // illegal instruction
-      17'b0010011_0010100_101:   BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1;  // orc.b
-      17'b0110011_0000101_110:   BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1;  // max
-      17'b0110011_0000101_111:   BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1;  // maxu
-      17'b0110011_0000101_100:   BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1;  // min
-      17'b0110011_0000101_101:   BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1;  // minu
+                                 BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1;  // illegal instruction
+      17'b0010011_0010100_101:   BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0;  // orc.b
+      17'b0110011_0000101_110:   BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0;  // max
+      17'b0110011_0000101_111:   BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0;  // maxu
+      17'b0110011_0000101_100:   BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0;  // min
+      17'b0110011_0000101_101:   BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0;  // minu
                                  
-      default:                   BMUControlsD = {Funct3D, {10'b0}};        // not B instruction or shift
+      default:                   BMUControlsD = {Funct3D, {10'b0}, {1'b1}};        // not B instruction or shift
     endcase
 
   // Unpack Control Signals
 
-  assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD} = BMUControlsD;
+  assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, IllegalBitmanipInstrD} = BMUControlsD;
 
    
 
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 6911f75ee..eaf289896 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -116,6 +116,7 @@ module controller(
   logic        IEURegWriteE;                   // Register write 
   logic        BRegWriteE;                     // Register write from BMU controller in Execute Stage
   logic        IllegalERegAdrD;                // RV32E attempts to write upper 16 registers
+  logic        IllegalBitmanipInstrD;          // Unrecognized B instruction
   logic [1:0]  AtomicE;                        // Atomic instruction 
   logic        FenceD, FenceE, FenceM;         // Fence instruction
   logic        SFenceVmaD;                     // sfence.vma instruction
@@ -191,7 +192,8 @@ module controller(
   // Squash control signals if coming from an illegal compressed instruction
   // On RV32E, can't write to upper 16 registers.  Checking reads to upper 16 is more costly so disregard them.
   assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; 
-  assign IllegalBaseInstrD = ControlsD[0] | IllegalERegAdrD;
+  assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal
+  //assign IllegalBaseInstrD = 1'b0;
   assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
           ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, 
           PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
@@ -243,7 +245,7 @@ module controller(
   assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
 
   if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
-    bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
+    bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
 
     assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers
     assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
@@ -262,6 +264,8 @@ module controller(
     assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
     assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
     assign ALUControlD = {W64D, SubArithD, ALUOpD};
+
+    assign IllegalBitmanipInstrD = 1'b1;
   end
 
   // Fences