TLB cleanup to match diagrams

wally-pipelined/src/mmu/mmu.sv

@@ -75,7 +75,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
 
 );
 
-  logic [`PA_BITS-1:0] TLBPhysicalAddress;
+  logic [`PA_BITS-1:0] TLBPAdr;
   logic [`XLEN+1:0]    AddressExt;
   logic PMPSquashBusAccess, PMASquashBusAccess;
   logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here.
@@ -93,7 +93,10 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
       logic ReadAccess, WriteAccess;
       assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read.  Execute and Read are never active for the same MMU, so safe to mix pipestages
       assign WriteAccess = WriteAccessM;
-      tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(.*);
+      tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) 
+        tlb(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
+            .SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .*);
+
     end else begin // just pass address through as physical
       assign Translate = 0;
       assign TLBMiss = 0;
@@ -104,7 +107,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
 
   // If translation is occuring, select translated physical address from TLB
   assign AddressExt = {2'b00, Address}; // extend length of virtual address if necessary for RV32
-  mux2 #(`PA_BITS) addressmux(AddressExt[`PA_BITS-1:0], TLBPhysicalAddress, Translate, PhysicalAddress);
+  mux2 #(`PA_BITS) addressmux(AddressExt[`PA_BITS-1:0], TLBPAdr, Translate, PhysicalAddress);
   
   ///////////////////////////////////////////
   // Check physical memory accesses

wally-pipelined/src/mmu/tlb.sv

@@ -54,7 +54,8 @@ module tlb #(parameter TLB_ENTRIES = 8,
   input logic              clk, reset,
 
   // Current value of satp CSR (from privileged unit)
-  input logic  [`XLEN-1:0] SATP_REGW,
+  input logic  [`SVMODE_BITS-1:0] SATP_MODE,
+  input logic  [`ASID_BITS-1:0] SATP_ASID,
   input logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
   input logic  [1:0]       STATUS_MPP,
 
@@ -80,7 +81,7 @@ module tlb #(parameter TLB_ENTRIES = 8,
   input logic              TLBFlush,
 
   // Physical address outputs
-  output logic [`PA_BITS-1:0] TLBPhysicalAddress,
+  output logic [`PA_BITS-1:0] TLBPAdr,
   output logic             TLBMiss,
   output logic             TLBHit,
   output logic             Translate,
@@ -89,11 +90,11 @@ module tlb #(parameter TLB_ENTRIES = 8,
   output logic             TLBPageFault
 );
 
-  logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex
+  logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex
 
   // Sections of the virtual and physical addresses
   logic [`VPN_BITS-1:0] VirtualPageNumber;
-  logic [`PPN_BITS-1:0] PhysicalPageNumber, PhysicalPageNumberMixed;
+  logic [`PPN_BITS-1:0] PhysicalPageNumber;
   logic [`XLEN+1:0]     AddressExt;
 
   // Sections of the page table entry
@@ -107,23 +108,20 @@ module tlb #(parameter TLB_ENTRIES = 8,
 
   assign VirtualPageNumber = Address[`VPN_BITS+11:12];
 
-  tlbcontrol tlbcontrol(.SATP_REGW, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+  tlbcontrol tlbcontrol(.SATP_MODE, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
                         .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
                         .PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault, 
                         .SV39Mode, .Translate);
 
   tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables);
   tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) 
-    tlbcam(.clk, .reset, .VirtualPageNumber, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_G, 
+    tlbcam(.clk, .reset, .VirtualPageNumber, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, 
-           .ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .Matches, .HitPageType, .CAMHit);
+           .SATP_ASID, .Matches, .HitPageType, .CAMHit);
-  tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PhysicalPageNumber, .PTEAccessBits, .PTE_G);
+  tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PhysicalPageNumber, .PTEAccessBits, .PTE_Gs);
 
   // Replace segments of the virtual page number with segments of the physical
   // page number. For 4 KB pages, the entire virtual page number is replaced.
   // For superpages, some segments are considered offsets into a larger page.
-  tlbphysicalpagemask PageMask(.VirtualPageNumber, .PhysicalPageNumber, .HitPageType, .PhysicalPageNumberMixed);
+  tlbmixer Mixer(.VirtualPageNumber, .PhysicalPageNumber, .HitPageType, .Address(Address[11:0]), .TLBHit, .TLBPAdr);
 
-  // Output the hit physical address if translation is currently on.
-  // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal
-  mux2 #(`PA_BITS) hitmux('0, {PhysicalPageNumberMixed, Address[11:0]}, TLBHit, TLBPhysicalAddress); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
 endmodule

wally-pipelined/src/mmu/tlbcam.sv

@@ -37,8 +37,8 @@ module tlbcam #(parameter TLB_ENTRIES = 8,
   input  logic                    SV39Mode,
   input logic                     TLBFlush,
   input logic [TLB_ENTRIES-1:0]   WriteEnables,
-  input logic [TLB_ENTRIES-1:0]   PTE_G,
+  input logic [TLB_ENTRIES-1:0]   PTE_Gs,
-  input logic [`ASID_BITS-1:0]    ASID,
+  input logic [`ASID_BITS-1:0]    SATP_ASID,
   output logic [TLB_ENTRIES-1:0]  Matches,
   output logic [1:0]              HitPageType,
   output logic                    CAMHit
@@ -53,7 +53,7 @@ module tlbcam #(parameter TLB_ENTRIES = 8,
   // page number segments.
 
   tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
-    .clk, .reset, .VirtualPageNumber, .ASID, .SV39Mode, .PTE_G, .PageTypeWriteVal, .TLBFlush,
+    .clk, .reset, .VirtualPageNumber, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush,
     .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches));
   assign CAMHit = |Matches & ~TLBFlush;
   assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result

wally-pipelined/src/mmu/tlbcamline.sv

@@ -32,7 +32,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
                     parameter SEGMENT_BITS = 10) (
   input  logic                  clk, reset,
   input  logic [`VPN_BITS-1:0]  VirtualPageNumber, // The requested page number to compare against the key
-  input  logic [`ASID_BITS-1:0] ASID,
+  input  logic [`ASID_BITS-1:0] SATP_ASID,
   input  logic                  SV39Mode,
   input  logic                  WriteEnable,  // Write a new entry to this line
   input  logic                  PTE_G,
@@ -58,7 +58,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
   logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
   logic MatchASID, Match0, Match1;
 
-  assign MatchASID = (ASID == Key_ASID) | PTE_G; 
+  assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G; 
 
   generate
     if (`XLEN == 32) begin
@@ -102,5 +102,5 @@ module tlbcamline #(parameter KEY_BITS = 20,
   // *** Might we want to update stored key right away to output match on the
   // write cycle? (using a mux)
   flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
-  flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {ASID, VirtualPageNumber}, Key);
+  flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VirtualPageNumber}, Key);
 endmodule

wally-pipelined/src/mmu/tlbcontrol.sv

@@ -30,7 +30,7 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
                     parameter ITLB = 0) (
 
   // Current value of satp CSR (from privileged unit)
-  input logic  [`XLEN-1:0] SATP_REGW,
+  input logic  [`SVMODE_BITS-1:0] SATP_MODE,
   input logic  [`XLEN-1:0] Address,
   input logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
   input logic  [1:0]       STATUS_MPP,
@@ -63,17 +63,16 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
   logic                  TLBAccess;
 
   // Grab the sv mode from SATP and determine whether translation should occur
-  assign SVMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
   assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
-  assign Translate = (SVMode != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation; 
+  assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation; 
   generate
       if (`XLEN==64) begin
-          assign SV39Mode = (SVMode == `SV39);
+          assign SV39Mode = (SATP_MODE == `SV39);
           // generate page fault if upper bits aren't all the same
           logic UpperEqual39, UpperEqual48;
           assign UpperEqual39 = &(Address[63:38]) | ~|(Address[63:38]);
           assign UpperEqual48 = &(Address[63:47]) | ~|(Address[63:47]); 
-          assign UpperBitsUnequalPageFault = SVMode ? ~UpperEqual39 : ~UpperEqual48;
+          assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
       end else begin
           assign SV39Mode = 0;
           assign UpperBitsUnequalPageFault = 0;

wally-pipelined/src/mmu/tlbphysicalpagemask.sv

@@ -1,79 +0,0 @@
-///////////////////////////////////////////
-// tlbphysicalpagemask.sv
-//
-// Written: David Harris and kmacsaigoren@hmc.edu 7 June 2021
-// Modified:
-// 
-//
-// Purpose: Takes two page numbers and replaces segments of the first page
-//          number with segments from the second, based on the page type.
-//          NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type.
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module tlbphysicalpagemask (
-    input  logic [`VPN_BITS-1:0]   VirtualPageNumber,
-    input  logic [`PPN_BITS-1:0]   PhysicalPageNumber,
-    input  logic [1:0]             HitPageType,
-    output logic [`PPN_BITS-1:0]   PhysicalPageNumberMixed 
-);
-
-  localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS;
-  logic [`PPN_BITS-1:0] ZeroExtendedVPN;
-  logic [`PPN_BITS-1:0] PageNumberMask;
-
-  generate
-    if (`XLEN == 32)
-      // kilopage: 22 bits of PPN, 0 bits of VPN
-      // megapage: 12 bits of PPN, 10 bits of VPN
-      mux2 #(22) pnm(22'h3FFFFF, 22'h3FFC00, HitPageType[0], PageNumberMask);
-    else
-      // kilopage: 44 bits of PPN, 0 bits of VPN
-      // megapage: 35 bits of PPN, 9 bits of VPN
-      // gigapage: 26 bits of PPN, 18 bits of VPN
-      // terapage: 17 bits of PPN, 27 bits of VPN
-      mux4 #(44) pnm(44'hFFFFFFFFFFF, 44'hFFFFFFFFE00, 44'hFFFFFFC0000, 44'hFFFF8000000, HitPageType, PageNumberMask);
-  endgenerate
- /*     always_comb 
-
-        case (PageType[0])
-          // the widths of these constansts are hardocded here to match `PPN_BITS in the wally-constants file.
-          0: PageNumberMask = 22'h3FFFFF; // kilopage: 22 bits of PPN, 0 bits of VPN
-          1: PageNumberMask = 22'h3FFC00; // megapage: 12 bits of PPN, 10 bits of VPN
-        endcase
-    end else begin
-      always_comb 
-        case (PageType[1:0])
-          0: PageNumberMask = 44'hFFFFFFFFFFF; // kilopage: 44 bits of PPN, 0 bits of VPN
-          1: PageNumberMask = 44'hFFFFFFFFE00; // megapage: 35 bits of PPN, 9 bits of VPN
-          2: PageNumberMask = 44'hFFFFFFC0000; // gigapage: 26 bits of PPN, 18 bits of VPN
-          3: PageNumberMask = 44'hFFFF8000000; // terapage: 17 bits of PPN, 27 bits of VPN
-          //     Bus widths accomodate SV48. In SV39, all of these
-          //     busses are the widths for sv48, but extra bits should be zeroed out by the mux
-          //     in the tlb when it generates VPN from the full virtualadress.
-        endcase
-    end
-  endgenerate */
-
-  // merge low segments of VPN with high segments of PPN decided by the pagetype.
-  assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VirtualPageNumber}; // forces the VPN to be the same width as PPN.
-  assign PhysicalPageNumberMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PhysicalPageNumber & PageNumberMask);
-
-endmodule

wally-pipelined/src/mmu/tlbram.sv

@@ -28,19 +28,19 @@
 `include "wally-config.vh"
 
 module tlbram #(parameter TLB_ENTRIES = 8) (
-  input logic                       clk, reset,
+  input  logic                      clk, reset,
-  input logic [`XLEN-1:0]           PTE,
+  input  logic [`XLEN-1:0]          PTE,
-  input logic [TLB_ENTRIES-1:0]     Matches, WriteEnables,
+  input  logic [TLB_ENTRIES-1:0]    Matches, WriteEnables,
   output logic [`PPN_BITS-1:0]      PhysicalPageNumber,
   output logic [7:0]                PTEAccessBits,
-  output logic [TLB_ENTRIES-1:0]    PTE_G
+  output logic [TLB_ENTRIES-1:0]    PTE_Gs
 );
 
   logic [`XLEN-1:0] RamRead[TLB_ENTRIES-1:0];
   logic [`XLEN-1:0] PageTableEntry;
 
   // Generate a flop for every entry in the RAM
-  tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, Matches, WriteEnables, PTE, RamRead, PTE_G);
+  tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, Matches, WriteEnables, PTE, RamRead, PTE_Gs);
   
   assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
   assign PTEAccessBits = PageTableEntry[7:0];