From 117ff8163bca7639f31f3bb5e8d9c7a2f23fcc9a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 19 Jan 2023 17:41:15 -0600 Subject: [PATCH] ram uses always rather than always_ff due to modelsim issue. --- pipelined/src/generic/mem/ram1p1rwbe.sv | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 55f7197bf..6ad27d013 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -64,19 +64,21 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( end else begin: ram integer i; + // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. + // Therefore these always blocks use the older always @(posedge clk) // Read - always_ff @(posedge clk) + always @(posedge clk) if(ce) dout <= #1 RAM[addr]; // Write divided into part for bytes and part for extra msbs if(WIDTH >= 8) - always_ff @(posedge clk) + always @(posedge clk) if (ce & we) for(i = 0; i < WIDTH/8; i++) if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8]; if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 - always_ff @(posedge clk) + always @(posedge clk) if (ce & we & bwe[WIDTH/8]) RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8]; end