From 117713be89d7d092af3e49b686964b2c5002167a Mon Sep 17 00:00:00 2001
From: Noah Boorstin <nboorstin@hmc.edu>
Date: Sat, 23 Jan 2021 16:42:17 -0500
Subject: [PATCH] Linux test now gets through first 8 instructions!

fixes the python parser:
  get the value, not function name, of PC
  only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
---
 wally-pipelined/src/testbench-busybear.sv |  6 +++---
 wally-pipelined/wally-busybear.do         | 10 +++++-----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/wally-pipelined/src/testbench-busybear.sv b/wally-pipelined/src/testbench-busybear.sv
index 2ff003a8f..0537fb23d 100644
--- a/wally-pipelined/src/testbench-busybear.sv
+++ b/wally-pipelined/src/testbench-busybear.sv
@@ -81,8 +81,8 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
       scan_file_rf = $fscanf(data_file_rf, "%x\n", rfExpected[j]);
       // check things!
       if (rf[j*64+63 -: 64] != rfExpected[j]) begin
-        $display("%t ps: rf[%i] does not equal rf expected: %x, %x", $time, j, rf[j*64+63 -: 64], rfExpected[j]);
-        $stop;
+        $display("%t ps: rf[%0d] does not equal rf expected: %x, %x", $time, j, rf[j*64+63 -: 64], rfExpected[j]);
+    //    $stop;
       end
     end
   end
@@ -103,7 +103,7 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
     //check things!
     if (PCF != pcExpected) begin
       $display("%t ps: PC does not equal PC expected: %x, %x", $time, PCF, pcExpected);
-      $stop;
+    //  $stop;
     end
   end
 
diff --git a/wally-pipelined/wally-busybear.do b/wally-pipelined/wally-busybear.do
index 259bf02d1..078127aa9 100644
--- a/wally-pipelined/wally-busybear.do
+++ b/wally-pipelined/wally-busybear.do
@@ -77,14 +77,14 @@ add wave -hex /testbench_busybear/dut/dp/regf/rf[28]
 add wave -hex /testbench_busybear/dut/dp/regf/rf[29]
 add wave -hex /testbench_busybear/dut/dp/regf/rf[30]
 add wave -hex /testbench_busybear/dut/dp/regf/rf[31]
-#add wave /testbench_busybear/InstrFName
+add wave /testbench_busybear/InstrFName
 ##add wave -hex /testbench_busybear/dut/dp/PCD
 #add wave -hex /testbench_busybear/dut/dp/InstrD
-#add wave /testbench_busybear/InstrDName
+add wave /testbench_busybear/InstrDName
 #add wave -divider
 ##add wave -hex /testbench_busybear/dut/dp/PCE
 ##add wave -hex /testbench_busybear/dut/dp/InstrE
-#add wave /testbench_busybear/InstrEName
+add wave /testbench_busybear/InstrEName
 #add wave -hex /testbench_busybear/dut/dp/SrcAE
 #add wave -hex /testbench_busybear/dut/dp/SrcBE
 #add wave -hex /testbench_busybear/dut/dp/ALUResultE
@@ -92,14 +92,14 @@ add wave -hex /testbench_busybear/dut/dp/regf/rf[31]
 #add wave -divider
 ##add wave -hex /testbench_busybear/dut/dp/PCM
 ##add wave -hex /testbench_busybear/dut/dp/InstrM
-#add wave /testbench_busybear/InstrMName
+add wave /testbench_busybear/InstrMName
 #add wave /testbench_busybear/dut/dmem/dtim/memwrite
 #add wave -hex /testbench_busybear/dut/dmem/AdrM
 #add wave -hex /testbench_busybear/dut/dmem/WriteDataM
 #add wave -divider
 #add wave -hex /testbench_busybear/dut/dp/PCW
 ##add wave -hex /testbench_busybear/dut/dp/InstrW
-#add wave /testbench_busybear/InstrWName
+add wave /testbench_busybear/InstrWName
 #add wave /testbench_busybear/dut/dp/RegWriteW
 #add wave -hex /testbench_busybear/dut/dp/ResultW
 #add wave -hex /testbench_busybear/dut/dp/RdW