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https://github.com/openhwgroup/cvw
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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commit
1173a937fd
@ -962,15 +962,19 @@ module testbenchfp;
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// http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says
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// http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says
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// for an unsigned integer result 0 is also okay
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// for an unsigned integer result 0 is also okay
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// Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but
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// TestFloat outputs 800... for both the largest integer values for both positive and negitive numbers but
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// the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
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// the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
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else if ((UnitVal === `CVTINTUNIT) &
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else if ( ((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & ~FlagMatch ) begin
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~((ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
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// ResMatch & FlagMatch checks the result again. It is checked within the
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// test again to avoid issues related when the values change tests (e.g., f16_eq_rne -> f16_eq_rz)
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if (~(ResMatch & FlagMatch)) begin
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errors += 1;
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errors += 1;
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$display("There is an error in %s", Tests[TestNum]);
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$display("\nError in %s", Tests[TestNum]);
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$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$stop;
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$stop;
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end
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end
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end
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if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
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if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
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// increment the test
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// increment the test
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@ -1,8 +1,8 @@
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hart_ids: [0]
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hart_ids: [0]
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hart0:
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hart0:
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# ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb
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# ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
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# ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zbb_Zbc_Zbs # Zkbs_Zcb
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# ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
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ISA: RV64IMAFDCSUZicsr_Zifencei_Zbb_Zbc_Zbs # Zkbs_Zcb
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ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
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physical_addr_sz: 56
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physical_addr_sz: 56
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User_Spec_Version: '2.3'
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User_Spec_Version: '2.3'
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supported_xlen: [64]
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supported_xlen: [64]
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