From 111f5926134a17fc5f248da2a9d1ef335687cdfb Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 14:52:15 -0800 Subject: [PATCH] factor divsqrt out of floating-point test cases to run on more derived configs --- config/derivlist.txt | 2 +- sim/regression-wally | 18 +++- testbench/testbench.sv | 8 ++ testbench/tests.vh | 238 +++++++++++++++++++---------------------- 4 files changed, 133 insertions(+), 133 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index de10f7d52..581922b9c 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -432,7 +432,7 @@ deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc DCACHE_NUMWAYS 32'd4 ICACHE_NUMWAYS 32'd4 -deriv way_8_4096_512_rv64gc rv32gc way_1_4096_512_rv64gc +deriv way_8_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc DCACHE_NUMWAYS 32'd8 ICACHE_NUMWAYS 32'd8 diff --git a/sim/regression-wally b/sim/regression-wally index 7b0175841..ef495df50 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -133,20 +133,26 @@ for test in ahbTests: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad", - "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] +tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad", + "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working #tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", # "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"] if (coverage): # delete all but 64gc tests when running coverage configs = [] tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", - "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad"] # add when working: "arch64zcb", "arch64zicboz" + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zcb", "arch64zicboz" if (fp): tests64gc.append("arch64f") tests64gc.append("arch64d") + tests64gc.append("arch64zfh") tests64gc.append("arch64f_fma") - tests64gc.append("arch64d_fma") + tests64gc.append("arch64d_fma") # *** add arch64zfh_fma when available(see riscv-arch-test pr 367) + tests64gc.append("arch64f_divsqrt") + tests64gc.append("arch64d_divsqrt") + tests64gc.append("arch64zfh_divsqrt") + tests64gc.append("arch64zfaf") + tests64gc.append("arch64zfad") coverStr = '-coverage' else: coverStr = '' @@ -167,7 +173,9 @@ if (nightly): ["tlb16_rv64gc", ["wally64priv"]], ["way_1_4096_512_rv64gc", ["arch64i", "arch64a"]], ["way_2_4096_512_rv64gc", ["arch64i"]], - ["way_8_4096_512_rv64gc", ["arch64i"]] + ["way_8_4096_512_rv64gc", ["arch64i"]], + ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ] for test in derivconfigtests: config = test[0]; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b20c6a993..893eb678b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -104,6 +104,8 @@ module testbench; "arch64d": if (P.D_SUPPORTED) tests = arch64d; "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; "arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma; + "arch64f_divsqrt": if (P.F_SUPPORTED) tests = arch64f_divsqrt; + "arch64d_divsqrt": if (P.D_SUPPORTED) tests = arch64d_divsqrt; "arch64zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei; "arch64zicond": if (P.ZICOND_SUPPORTED) tests = arch64zicond; "imperas64i": tests = imperas64i; @@ -128,6 +130,8 @@ module testbench; "arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz; "arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb; "arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh; +// "arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma; *** not yet in riscv-arch-tst PR367 + "arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; "arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad; endcase @@ -145,6 +149,8 @@ module testbench; "arch32d": if (P.D_SUPPORTED) tests = arch32d; "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; "arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma; + "arch32f_divsqrt": if (P.F_SUPPORTED) tests = arch32f_divsqrt; + "arch32d_divsqrt": if (P.D_SUPPORTED) tests = arch32d_divsqrt; "arch32zifencei": if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei; "arch32zicond": if (P.ZICOND_SUPPORTED) tests = arch32zicond; "imperas32i": tests = imperas32i; @@ -165,6 +171,8 @@ module testbench; "arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz; "arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb; "arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh; + // "arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma; *** not yet in riscv-arch-tst PR367 + "arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; "arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad; endcase diff --git a/testbench/tests.vh b/testbench/tests.vh index efb0e6788..f5c9cc0ac 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1126,10 +1126,10 @@ string imperas32f[] = '{ // "rv64i_m/F/src/fnmsub_b15-01.S" }; - string arch64f[] = '{ + string arch64f_divsqrt[] = '{ `RISCVARCHTEST, - "rv64i_m/F/src/fdiv_b1-01.S", "rv64i_m/F/src/fdiv_b20-01.S", + "rv64i_m/F/src/fdiv_b1-01.S", "rv64i_m/F/src/fdiv_b2-01.S", "rv64i_m/F/src/fdiv_b21-01.S", "rv64i_m/F/src/fdiv_b3-01.S", @@ -1147,7 +1147,11 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsqrt_b5-01.S", "rv64i_m/F/src/fsqrt_b7-01.S", "rv64i_m/F/src/fsqrt_b8-01.S", - "rv64i_m/F/src/fsqrt_b9-01.S", + "rv64i_m/F/src/fsqrt_b9-01.S" + }; + + string arch64f[] = '{ + `RISCVARCHTEST, "rv64i_m/F/src/fadd_b10-01.S", "rv64i_m/F/src/fadd_b1-01.S", "rv64i_m/F/src/fadd_b11-01.S", @@ -1178,17 +1182,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fcvt.wu.s_b27-01.S", "rv64i_m/F/src/fcvt.wu.s_b28-01.S", "rv64i_m/F/src/fcvt.wu.s_b29-01.S", - "rv64i_m/F/src/fdiv_b1-01.S", - "rv64i_m/F/src/fdiv_b20-01.S", - "rv64i_m/F/src/fdiv_b2-01.S", - "rv64i_m/F/src/fdiv_b21-01.S", - "rv64i_m/F/src/fdiv_b3-01.S", - "rv64i_m/F/src/fdiv_b4-01.S", - "rv64i_m/F/src/fdiv_b5-01.S", - "rv64i_m/F/src/fdiv_b6-01.S", - "rv64i_m/F/src/fdiv_b7-01.S", - "rv64i_m/F/src/fdiv_b8-01.S", - "rv64i_m/F/src/fdiv_b9-01.S", "rv64i_m/F/src/feq_b1-01.S", "rv64i_m/F/src/feq_b19-01.S", "rv64i_m/F/src/fle_b1-01.S", @@ -1269,15 +1262,6 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsgnj_b1-01.S", "rv64i_m/F/src/fsgnjn_b1-01.S", "rv64i_m/F/src/fsgnjx_b1-01.S", - "rv64i_m/F/src/fsqrt_b1-01.S", - "rv64i_m/F/src/fsqrt_b20-01.S", - "rv64i_m/F/src/fsqrt_b2-01.S", - "rv64i_m/F/src/fsqrt_b3-01.S", - "rv64i_m/F/src/fsqrt_b4-01.S", - "rv64i_m/F/src/fsqrt_b5-01.S", - "rv64i_m/F/src/fsqrt_b7-01.S", - "rv64i_m/F/src/fsqrt_b8-01.S", - "rv64i_m/F/src/fsqrt_b9-01.S", "rv64i_m/F/src/fsub_b10-01.S", "rv64i_m/F/src/fsub_b1-01.S", "rv64i_m/F/src/fsub_b11-01.S", @@ -1292,6 +1276,30 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsw-align-01.S" }; + string arch64zfh_divsqrt[] = '{ + `RISCVARCHTEST, + "rv64i_m/Zfh/src/fdiv_b20-01.S", + "rv64i_m/Zfh/src/fdiv_b1-01.S", + "rv64i_m/Zfh/src/fdiv_b2-01.S", + "rv64i_m/Zfh/src/fdiv_b21-01.S", + "rv64i_m/Zfh/src/fdiv_b3-01.S", + "rv64i_m/Zfh/src/fdiv_b4-01.S", + "rv64i_m/Zfh/src/fdiv_b5-01.S", + "rv64i_m/Zfh/src/fdiv_b6-01.S", + "rv64i_m/Zfh/src/fdiv_b7-01.S", + "rv64i_m/Zfh/src/fdiv_b8-01.S", + "rv64i_m/Zfh/src/fdiv_b9-01.S", + "rv64i_m/Zfh/src/fsqrt_b1-01.S", + "rv64i_m/Zfh/src/fsqrt_b20-01.S", + "rv64i_m/Zfh/src/fsqrt_b2-01.S", + "rv64i_m/Zfh/src/fsqrt_b3-01.S", + "rv64i_m/Zfh/src/fsqrt_b4-01.S", + "rv64i_m/Zfh/src/fsqrt_b5-01.S", + "rv64i_m/Zfh/src/fsqrt_b7-01.S", + "rv64i_m/Zfh/src/fsqrt_b8-01.S", + "rv64i_m/Zfh/src/fsqrt_b9-01.S" + }; + string arch64zfh[] = '{ `RISCVARCHTEST, "rv64i_m/Zfh/src/fadd_b10-01.S", @@ -1342,17 +1350,6 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S", "rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S", "rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S", - "rv64i_m/Zfh/src/fdiv_b20-01.S", - "rv64i_m/Zfh/src/fdiv_b1-01.S", - "rv64i_m/Zfh/src/fdiv_b2-01.S", - "rv64i_m/Zfh/src/fdiv_b21-01.S", - "rv64i_m/Zfh/src/fdiv_b3-01.S", - "rv64i_m/Zfh/src/fdiv_b4-01.S", - "rv64i_m/Zfh/src/fdiv_b5-01.S", - "rv64i_m/Zfh/src/fdiv_b6-01.S", - "rv64i_m/Zfh/src/fdiv_b7-01.S", - "rv64i_m/Zfh/src/fdiv_b8-01.S", - "rv64i_m/Zfh/src/fdiv_b9-01.S", "rv64i_m/Zfh/src/feq_b1-01.S", "rv64i_m/Zfh/src/feq_b19-01.S", "rv64i_m/Zfh/src/fle_b1-01.S", @@ -1385,15 +1382,6 @@ string imperas32f[] = '{ "rv64i_m/Zfh/src/fsgnj_b1-01.S", "rv64i_m/Zfh/src/fsgnjn_b1-01.S", "rv64i_m/Zfh/src/fsgnjx_b1-01.S", - "rv64i_m/Zfh/src/fsqrt_b1-01.S", - "rv64i_m/Zfh/src/fsqrt_b20-01.S", - "rv64i_m/Zfh/src/fsqrt_b2-01.S", - "rv64i_m/Zfh/src/fsqrt_b3-01.S", - "rv64i_m/Zfh/src/fsqrt_b4-01.S", - "rv64i_m/Zfh/src/fsqrt_b5-01.S", - "rv64i_m/Zfh/src/fsqrt_b7-01.S", - "rv64i_m/Zfh/src/fsqrt_b8-01.S", - "rv64i_m/Zfh/src/fsqrt_b9-01.S", "rv64i_m/Zfh/src/fsub_b10-01.S", "rv64i_m/Zfh/src/fsub_b1-01.S", "rv64i_m/Zfh/src/fsub_b11-01.S", @@ -1417,9 +1405,8 @@ string imperas32f[] = '{ // "rv64i_m/D/src/fnmsub.d_b15-01.S" }; - string arch64d[] = '{ + string arch64d_divsqrt[] = '{ `RISCVARCHTEST, - // for speed "rv64i_m/D/src/fdiv.d_b1-01.S", "rv64i_m/D/src/fdiv.d_b20-01.S", "rv64i_m/D/src/fdiv.d_b2-01.S", @@ -1439,8 +1426,13 @@ string imperas32f[] = '{ "rv64i_m/D/src/fsqrt.d_b5-01.S", "rv64i_m/D/src/fsqrt.d_b7-01.S", "rv64i_m/D/src/fsqrt.d_b8-01.S", - "rv64i_m/D/src/fsqrt.d_b9-01.S", - "rv64i_m/D/src/fadd.d_b10-01.S", + "rv64i_m/D/src/fsqrt.d_b9-01.S" + }; + + string arch64d[] = '{ + `RISCVARCHTEST, + // for speed + "rv64i_m/D/src/fadd.d_b10-01.S", "rv64i_m/D/src/fadd.d_b1-01.S", "rv64i_m/D/src/fadd.d_b11-01.S", "rv64i_m/D/src/fadd.d_b12-01.S", @@ -1502,17 +1494,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fcvt.wu.d_b27-01.S", "rv64i_m/D/src/fcvt.wu.d_b28-01.S", "rv64i_m/D/src/fcvt.wu.d_b29-01.S", - "rv64i_m/D/src/fdiv.d_b1-01.S", - "rv64i_m/D/src/fdiv.d_b20-01.S", - "rv64i_m/D/src/fdiv.d_b2-01.S", - "rv64i_m/D/src/fdiv.d_b21-01.S", - "rv64i_m/D/src/fdiv.d_b3-01.S", - "rv64i_m/D/src/fdiv.d_b4-01.S", - "rv64i_m/D/src/fdiv.d_b5-01.S", - "rv64i_m/D/src/fdiv.d_b6-01.S", - "rv64i_m/D/src/fdiv.d_b7-01.S", - "rv64i_m/D/src/fdiv.d_b8-01.S", - "rv64i_m/D/src/fdiv.d_b9-01.S", "rv64i_m/D/src/feq.d_b1-01.S", "rv64i_m/D/src/feq.d_b19-01.S", "rv64i_m/D/src/fle.d_b1-01.S", @@ -1590,15 +1571,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fsgnj.d_b1-01.S", "rv64i_m/D/src/fsgnjn.d_b1-01.S", "rv64i_m/D/src/fsgnjx.d_b1-01.S", - "rv64i_m/D/src/fsqrt.d_b1-01.S", - "rv64i_m/D/src/fsqrt.d_b20-01.S", - "rv64i_m/D/src/fsqrt.d_b2-01.S", - "rv64i_m/D/src/fsqrt.d_b3-01.S", - "rv64i_m/D/src/fsqrt.d_b4-01.S", - "rv64i_m/D/src/fsqrt.d_b5-01.S", - "rv64i_m/D/src/fsqrt.d_b7-01.S", - "rv64i_m/D/src/fsqrt.d_b8-01.S", - "rv64i_m/D/src/fsqrt.d_b9-01.S", "rv64i_m/D/src/fssub.d_b10-01.S", "rv64i_m/D/src/fssub.d_b1-01.S", "rv64i_m/D/src/fssub.d_b11-01.S", @@ -1754,6 +1726,30 @@ string arch64zbs[] = '{ // "rv32i_m/F/src/fnmsub_b15-01.S" }; + string arch32f_divsqrt[] = '{ + `RISCVARCHTEST, + "rv32i_m/F/src/fdiv_b20-01.S", + "rv32i_m/F/src/fdiv_b1-01.S", + "rv32i_m/F/src/fdiv_b2-01.S", + "rv32i_m/F/src/fdiv_b21-01.S", + "rv32i_m/F/src/fdiv_b3-01.S", + "rv32i_m/F/src/fdiv_b4-01.S", + "rv32i_m/F/src/fdiv_b5-01.S", + "rv32i_m/F/src/fdiv_b6-01.S", + "rv32i_m/F/src/fdiv_b7-01.S", + "rv32i_m/F/src/fdiv_b8-01.S", + "rv32i_m/F/src/fdiv_b9-01.S", + "rv32i_m/F/src/fsqrt_b1-01.S", + "rv32i_m/F/src/fsqrt_b20-01.S", + "rv32i_m/F/src/fsqrt_b2-01.S", + "rv32i_m/F/src/fsqrt_b3-01.S", + "rv32i_m/F/src/fsqrt_b4-01.S", + "rv32i_m/F/src/fsqrt_b5-01.S", + "rv32i_m/F/src/fsqrt_b7-01.S", + "rv32i_m/F/src/fsqrt_b8-01.S", + "rv32i_m/F/src/fsqrt_b9-01.S" + }; + string arch32f[] = '{ `RISCVARCHTEST, "rv32i_m/F/src/fadd_b10-01.S", @@ -1786,17 +1782,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fcvt.wu.s_b27-01.S", "rv32i_m/F/src/fcvt.wu.s_b28-01.S", "rv32i_m/F/src/fcvt.wu.s_b29-01.S", - "rv32i_m/F/src/fdiv_b20-01.S", - "rv32i_m/F/src/fdiv_b1-01.S", - "rv32i_m/F/src/fdiv_b2-01.S", - "rv32i_m/F/src/fdiv_b21-01.S", - "rv32i_m/F/src/fdiv_b3-01.S", - "rv32i_m/F/src/fdiv_b4-01.S", - "rv32i_m/F/src/fdiv_b5-01.S", - "rv32i_m/F/src/fdiv_b6-01.S", - "rv32i_m/F/src/fdiv_b7-01.S", - "rv32i_m/F/src/fdiv_b8-01.S", - "rv32i_m/F/src/fdiv_b9-01.S", "rv32i_m/F/src/feq_b1-01.S", "rv32i_m/F/src/feq_b19-01.S", "rv32i_m/F/src/fle_b1-01.S", @@ -1877,15 +1862,6 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fsgnj_b1-01.S", "rv32i_m/F/src/fsgnjn_b1-01.S", "rv32i_m/F/src/fsgnjx_b1-01.S", - "rv32i_m/F/src/fsqrt_b1-01.S", - "rv32i_m/F/src/fsqrt_b20-01.S", - "rv32i_m/F/src/fsqrt_b2-01.S", - "rv32i_m/F/src/fsqrt_b3-01.S", - "rv32i_m/F/src/fsqrt_b4-01.S", - "rv32i_m/F/src/fsqrt_b5-01.S", - "rv32i_m/F/src/fsqrt_b7-01.S", - "rv32i_m/F/src/fsqrt_b8-01.S", - "rv32i_m/F/src/fsqrt_b9-01.S", "rv32i_m/F/src/fsub_b10-01.S", "rv32i_m/F/src/fsub_b1-01.S", "rv32i_m/F/src/fsub_b11-01.S", @@ -1900,6 +1876,30 @@ string arch64zbs[] = '{ "rv32i_m/F/src/fsw-align-01.S" }; + string arch32zfh_divsqrt[] = '{ + `RISCVARCHTEST, + "rv32i_m/Zfh/src/fdiv_b20-01.S", + "rv32i_m/Zfh/src/fdiv_b1-01.S", + "rv32i_m/Zfh/src/fdiv_b2-01.S", + "rv32i_m/Zfh/src/fdiv_b21-01.S", + "rv32i_m/Zfh/src/fdiv_b3-01.S", + "rv32i_m/Zfh/src/fdiv_b4-01.S", + "rv32i_m/Zfh/src/fdiv_b5-01.S", + "rv32i_m/Zfh/src/fdiv_b6-01.S", + "rv32i_m/Zfh/src/fdiv_b7-01.S", + "rv32i_m/Zfh/src/fdiv_b8-01.S", + "rv32i_m/Zfh/src/fdiv_b9-01.S", + "rv32i_m/Zfh/src/fsqrt_b1-01.S", + "rv32i_m/Zfh/src/fsqrt_b20-01.S", + "rv32i_m/Zfh/src/fsqrt_b2-01.S", + "rv32i_m/Zfh/src/fsqrt_b3-01.S", + "rv32i_m/Zfh/src/fsqrt_b4-01.S", + "rv32i_m/Zfh/src/fsqrt_b5-01.S", + "rv32i_m/Zfh/src/fsqrt_b7-01.S", + "rv32i_m/Zfh/src/fsqrt_b8-01.S", + "rv32i_m/Zfh/src/fsqrt_b9-01.S" + }; + string arch32zfh[] = '{ `RISCVARCHTEST, "rv32i_m/Zfh/src/fadd_b10-01.S", @@ -1932,17 +1932,6 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S", "rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S", "rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S", - "rv32i_m/Zfh/src/fdiv_b20-01.S", - "rv32i_m/Zfh/src/fdiv_b1-01.S", - "rv32i_m/Zfh/src/fdiv_b2-01.S", - "rv32i_m/Zfh/src/fdiv_b21-01.S", - "rv32i_m/Zfh/src/fdiv_b3-01.S", - "rv32i_m/Zfh/src/fdiv_b4-01.S", - "rv32i_m/Zfh/src/fdiv_b5-01.S", - "rv32i_m/Zfh/src/fdiv_b6-01.S", - "rv32i_m/Zfh/src/fdiv_b7-01.S", - "rv32i_m/Zfh/src/fdiv_b8-01.S", - "rv32i_m/Zfh/src/fdiv_b9-01.S", "rv32i_m/Zfh/src/feq_b1-01.S", "rv32i_m/Zfh/src/feq_b19-01.S", "rv32i_m/Zfh/src/fle_b1-01.S", @@ -1975,15 +1964,6 @@ string arch64zbs[] = '{ "rv32i_m/Zfh/src/fsgnj_b1-01.S", "rv32i_m/Zfh/src/fsgnjn_b1-01.S", "rv32i_m/Zfh/src/fsgnjx_b1-01.S", - "rv32i_m/Zfh/src/fsqrt_b1-01.S", - "rv32i_m/Zfh/src/fsqrt_b20-01.S", - "rv32i_m/Zfh/src/fsqrt_b2-01.S", - "rv32i_m/Zfh/src/fsqrt_b3-01.S", - "rv32i_m/Zfh/src/fsqrt_b4-01.S", - "rv32i_m/Zfh/src/fsqrt_b5-01.S", - "rv32i_m/Zfh/src/fsqrt_b7-01.S", - "rv32i_m/Zfh/src/fsqrt_b8-01.S", - "rv32i_m/Zfh/src/fsqrt_b9-01.S", "rv32i_m/Zfh/src/fsub_b10-01.S", "rv32i_m/Zfh/src/fsub_b1-01.S", "rv32i_m/Zfh/src/fsub_b11-01.S", @@ -2086,6 +2066,30 @@ string arch64zbs[] = '{ "rv32i_m/D/src/fnmsub.d_b15-01.S" }; + string arch32d_divsqrt[] = '{ + `RISCVARCHTEST, + "rv32i_m/D/src/fdiv.d_b1-01.S", + "rv32i_m/D/src/fdiv.d_b20-01.S", + "rv32i_m/D/src/fdiv.d_b2-01.S", + "rv32i_m/D/src/fdiv.d_b21-01.S", + "rv32i_m/D/src/fdiv.d_b3-01.S", + "rv32i_m/D/src/fdiv.d_b4-01.S", + "rv32i_m/D/src/fdiv.d_b5-01.S", + "rv32i_m/D/src/fdiv.d_b6-01.S", + "rv32i_m/D/src/fdiv.d_b7-01.S", + "rv32i_m/D/src/fdiv.d_b8-01.S", + "rv32i_m/D/src/fdiv.d_b9-01.S", + "rv32i_m/D/src/fsqrt.d_b1-01.S", + "rv32i_m/D/src/fsqrt.d_b20-01.S", + "rv32i_m/D/src/fsqrt.d_b2-01.S", + "rv32i_m/D/src/fsqrt.d_b3-01.S", + "rv32i_m/D/src/fsqrt.d_b4-01.S", + "rv32i_m/D/src/fsqrt.d_b5-01.S", + "rv32i_m/D/src/fsqrt.d_b7-01.S", + "rv32i_m/D/src/fsqrt.d_b8-01.S", + "rv32i_m/D/src/fsqrt.d_b9-01.S" + }; + string arch32d[] = '{ `RISCVARCHTEST, "rv32i_m/D/src/fadd.d_b10-01.S", @@ -2132,17 +2136,6 @@ string arch64zbs[] = '{ "rv32i_m/D/src/fcvt.wu.d_b27-01.S", "rv32i_m/D/src/fcvt.wu.d_b28-01.S", "rv32i_m/D/src/fcvt.wu.d_b29-01.S", - "rv32i_m/D/src/fdiv.d_b1-01.S", - "rv32i_m/D/src/fdiv.d_b20-01.S", - "rv32i_m/D/src/fdiv.d_b2-01.S", - "rv32i_m/D/src/fdiv.d_b21-01.S", - "rv32i_m/D/src/fdiv.d_b3-01.S", - "rv32i_m/D/src/fdiv.d_b4-01.S", - "rv32i_m/D/src/fdiv.d_b5-01.S", - "rv32i_m/D/src/fdiv.d_b6-01.S", - "rv32i_m/D/src/fdiv.d_b7-01.S", - "rv32i_m/D/src/fdiv.d_b8-01.S", - "rv32i_m/D/src/fdiv.d_b9-01.S", "rv32i_m/D/src/feq.d_b1-01.S", "rv32i_m/D/src/feq.d_b19-01.S", "rv32i_m/D/src/fle.d_b1-01.S", @@ -2211,15 +2204,6 @@ string arch64zbs[] = '{ "rv32i_m/D/src/fsgnj.d_b1-01.S", "rv32i_m/D/src/fsgnjn.d_b1-01.S", "rv32i_m/D/src/fsgnjx.d_b1-01.S", - "rv32i_m/D/src/fsqrt.d_b1-01.S", - "rv32i_m/D/src/fsqrt.d_b20-01.S", - "rv32i_m/D/src/fsqrt.d_b2-01.S", - "rv32i_m/D/src/fsqrt.d_b3-01.S", - "rv32i_m/D/src/fsqrt.d_b4-01.S", - "rv32i_m/D/src/fsqrt.d_b5-01.S", - "rv32i_m/D/src/fsqrt.d_b7-01.S", - "rv32i_m/D/src/fsqrt.d_b8-01.S", - "rv32i_m/D/src/fsqrt.d_b9-01.S", "rv32i_m/D/src/fssub.d_b10-01.S", "rv32i_m/D/src/fssub.d_b1-01.S", "rv32i_m/D/src/fssub.d_b11-01.S",