From 1117b90f407c610d5e07e67db131b9086ee522e2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 29 Nov 2021 18:32:51 -0600
Subject: [PATCH] Created Makefile to manage IP generation.

---
 .gitignore                                           |  1 +
 fpga/generator/Makefile                              | 12 ++++++++++++
 ...te_axi_bridge.tcl => xlnx_ahblite_axi_bridge.tcl} |  0
 ...ck_converter.tcl => xlnx_axi_clock_converter.tcl} |  0
 fpga/generator/{ddr4_mig.tcl => xlnx_ddr4.tcl}       |  0
 .../{proc_sys_reset.tcl => xlnx_proc_sys_reset.tcl}  |  0
 6 files changed, 13 insertions(+)
 create mode 100644 fpga/generator/Makefile
 rename fpga/generator/{ahblite_axi_bridge.tcl => xlnx_ahblite_axi_bridge.tcl} (100%)
 rename fpga/generator/{axi_clock_converter.tcl => xlnx_axi_clock_converter.tcl} (100%)
 rename fpga/generator/{ddr4_mig.tcl => xlnx_ddr4.tcl} (100%)
 rename fpga/generator/{proc_sys_reset.tcl => xlnx_proc_sys_reset.tcl} (100%)

diff --git a/.gitignore b/.gitignore
index 2542dd881..e33205dd4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -35,3 +35,4 @@ tests/linux-testgen/buildroot-config-src/linux.config.old
 tests/linux-testgen/buildroot-config-src/busybox.config.old
 wally-pipelined/regression/slack-notifier/slack-webhook-url.txt
 wally-pipelined/regression/logs
+fpga/generator/IP
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
new file mode 100644
index 000000000..9cfb20b46
--- /dev/null
+++ b/fpga/generator/Makefile
@@ -0,0 +1,12 @@
+dst := IP
+
+
+all: $(dst)/xlnx_proc_sys_reset.log \
+	$(dst)/xlnx_ddr4.log \
+	$(dst)/xlnx_axi_clock_converter.log \
+	 $(dst)/xlnx_ahblite_axi_bridge.log
+
+$(dst)/%.log: %.tcl
+	mkdir -p IP
+	cd IP;\
+	vivado -mode batch -source ../$*.tcl | tee $*.log
diff --git a/fpga/generator/ahblite_axi_bridge.tcl b/fpga/generator/xlnx_ahblite_axi_bridge.tcl
similarity index 100%
rename from fpga/generator/ahblite_axi_bridge.tcl
rename to fpga/generator/xlnx_ahblite_axi_bridge.tcl
diff --git a/fpga/generator/axi_clock_converter.tcl b/fpga/generator/xlnx_axi_clock_converter.tcl
similarity index 100%
rename from fpga/generator/axi_clock_converter.tcl
rename to fpga/generator/xlnx_axi_clock_converter.tcl
diff --git a/fpga/generator/ddr4_mig.tcl b/fpga/generator/xlnx_ddr4.tcl
similarity index 100%
rename from fpga/generator/ddr4_mig.tcl
rename to fpga/generator/xlnx_ddr4.tcl
diff --git a/fpga/generator/proc_sys_reset.tcl b/fpga/generator/xlnx_proc_sys_reset.tcl
similarity index 100%
rename from fpga/generator/proc_sys_reset.tcl
rename to fpga/generator/xlnx_proc_sys_reset.tcl