From 10ff69efc10f729333cf0a6d15c969e06dc53b90 Mon Sep 17 00:00:00 2001 From: rachanaerra Date: Mon, 5 Dec 2022 15:05:21 -0600 Subject: [PATCH] updated constraints file --- fpga/constraints/debug2.xdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 00a53f4f6..6ec6200f5 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -316,12 +316,12 @@ connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IF create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe61] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] -connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]] +connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe62] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62] -connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]] +connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FCvtIntStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe63]