Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Divider cleanup

Browse Source
This commit is contained in:
David Harris 2021-10-03 11:16:48 -04:00
parent 78eba19a1f
commit 10ef563211
1 changed files with 6 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
wally-pipelined/src/muldiv/muldiv.sv
View File

@ -48,35 +48,23 @@ module muldiv (
logic [`XLEN-1:0] QuotM, RemM; logic [`XLEN-1:0] QuotM, RemM;
logic [`XLEN*2-1:0] ProdE, ProdM; logic [`XLEN*2-1:0] ProdE, ProdM;
logic enable_q;
//logic [2:0] Funct3E_Q;
logic div0error; // ***unused
logic [`XLEN-1:0] XE, DE;
//logic [`XLEN-1:0] Num0, Den0;
// logic gclk;
logic StartDivideE, BusyE, DivDoneM; logic StartDivideE, BusyE, DivDoneM;
logic SignedDivideE; logic SignedDivideE;
logic W64M; logic W64M;
// Multiplier // Multiplier
mul mul(.*); mul mul(.*);
flopenrc #(`XLEN*2) ProdMReg(clk, reset, FlushM, ~StallM, ProdE, ProdM); flopenrc #(`XLEN*2) ProdMReg(clk, reset, FlushM, ~StallM, ProdE, ProdM);
// Divide // Divide
assign XE = SrcAE;
assign DE = SrcBE;
assign SignedDivideE = ~Funct3E[0];
//intdiv #(`XLEN) div (QuotE, RemE, DivDoneE, DivBusyE, div0error, N, D, gclk, reset, StartDivideE, SignedDivideE);
intdivrestoring div(.clk, .reset, .StallM, .FlushM,
.SignedDivideE, .W64E, .StartDivideE, .XE(SrcAE), .DE(SrcBE), .BusyE, .DivDoneM, .QuotM, .RemM);
// Start a divide when a new division instruction is received and the divider isn't already busy or finishing // Start a divide when a new division instruction is received and the divider isn't already busy or finishing
assign StartDivideE = MulDivE & Funct3E[2] & ~BusyE & ~DivDoneM; assign StartDivideE = MulDivE & Funct3E[2] & ~BusyE & ~DivDoneM;
assign DivBusyE = StartDivideE | BusyE; assign DivBusyE = StartDivideE | BusyE;
assign SignedDivideE = ~Funct3E[0];
intdivrestoring div(.clk, .reset, .StallM, .FlushM,
.SignedDivideE, .W64E, .StartDivideE, .XE(SrcAE), .DE(SrcBE), .BusyE, .DivDoneM, .QuotM, .RemM);
// Select result // Result multiplexer
always_comb always_comb
case (Funct3M) case (Funct3M)
3'b000: PrelimResultM = ProdM[`XLEN-1:0]; 3'b000: PrelimResultM = ProdM[`XLEN-1:0];
@ -97,6 +85,8 @@ module muldiv (
assign MulDivResultM = PrelimResultM; assign MulDivResultM = PrelimResultM;
end end
// Writeback stage pipeline register
flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW); flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW);
end else begin // no M instructions supported end else begin // no M instructions supported