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Removed unnecessary Umfirst from early termination

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David Harris 2024-06-19 09:18:51 -07:00
parent 4b4980e42d
commit 10e6d5846b
3 changed files with 4 additions and 7 deletions
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5
src/fpu/fdivsqrt/fdivsqrt.sv
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@ -61,7 +61,6 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
logic [P.DIVb+3:0] D; // Iterator Divisor logic [P.DIVb+3:0] D; // Iterator Divisor
logic [P.DIVb:0] FirstU, FirstUM; // Intermediate result values logic [P.DIVb:0] FirstU, FirstUM; // Intermediate result values
logic [P.DIVb+1:0] FirstC; // Step tracker logic [P.DIVb+1:0] FirstC; // Step tracker
logic Firstun; // Quotient selection
logic WZeroE; // Early termination flag logic WZeroE; // Early termination flag
logic [P.DURLEN-1:0] CyclesE; // FSM cycles logic [P.DURLEN-1:0] CyclesE; // FSM cycles
logic SpecialCaseM; // Divide by zero, square root of negative, etc. logic SpecialCaseM; // Divide by zero, square root of negative, etc.
@ -89,11 +88,11 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
fdivsqrtiter #(P) fdivsqrtiter( // CSA Iterator fdivsqrtiter #(P) fdivsqrtiter( // CSA Iterator
.clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D, .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D,
.FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC)); .FirstU, .FirstUM, .FirstC, .FirstWS(WS), .FirstWC(WC));
fdivsqrtpostproc #(P) fdivsqrtpostproc( // Postprocessor fdivsqrtpostproc #(P) fdivsqrtpostproc( // Postprocessor
.clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC,
.SqrtE, .Firstun, .SqrtM, .SpecialCaseM, .SqrtE, .SqrtM, .SpecialCaseM,
.UmM, .WZeroE, .DivStickyM, .UmM, .WZeroE, .DivStickyM,
// Int-specific // Int-specific
.IntNormShiftM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM, .IntNormShiftM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM,

2
src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -35,7 +35,6 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
input logic [P.DIVb+3:0] X, D, // Q4.DIVb input logic [P.DIVb+3:0] X, D, // Q4.DIVb
output logic [P.DIVb:0] FirstU, FirstUM, // U1.DIVb output logic [P.DIVb:0] FirstU, FirstUM, // U1.DIVb
output logic [P.DIVb+1:0] FirstC, // Q2.DIVb output logic [P.DIVb+1:0] FirstC, // Q2.DIVb
output logic Firstun,
output logic [P.DIVb+3:0] FirstWS, FirstWC // Q4.DIVb output logic [P.DIVb+3:0] FirstWS, FirstWC // Q4.DIVb
); );
@ -119,6 +118,5 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
assign FirstU = U[0]; assign FirstU = U[0];
assign FirstUM = UM[0]; assign FirstUM = UM[0];
assign FirstC = C[0]; assign FirstC = C[0];
assign Firstun = un[0];
endmodule endmodule

4
src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -35,7 +35,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
input logic [P.DIVb:0] FirstU, FirstUM, // U1.DIVb input logic [P.DIVb:0] FirstU, FirstUM, // U1.DIVb
input logic [P.DIVb+1:0] FirstC, // Q2.DIVb input logic [P.DIVb+1:0] FirstC, // Q2.DIVb
input logic SqrtE, input logic SqrtE,
input logic Firstun, SqrtM, SpecialCaseM, input logic SqrtM, SpecialCaseM,
input logic [P.XLEN-1:0] AM, // U/Q(XLEN.0) input logic [P.XLEN-1:0] AM, // U/Q(XLEN.0)
input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M, input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
input logic [P.DIVBLEN-1:0] IntNormShiftM, input logic [P.DIVBLEN-1:0] IntNormShiftM,
@ -71,7 +71,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
mux2 #(P.DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE); mux2 #(P.DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
csa #(P.DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero}; csa #(P.DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
aplusbeq0 #(P.DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E); aplusbeq0 #(P.DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
assign WZeroE = weq0E|(wfeq0E & Firstun); assign WZeroE = weq0E | wfeq0E;
end else begin end else begin
assign WZeroE = weq0E; assign WZeroE = weq0E;
end end