From 10b08f80396193c6124035867f58f152b046a9ce Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 10 May 2024 08:51:12 -0500 Subject: [PATCH] Updated brach predictor names to more logical names and match textbook. --- src/ifu/bpred/bpred.sv | 1 - src/ifu/bpred/gshare.sv | 6 +++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 166fba3de..7dd8a8456 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -212,7 +212,6 @@ module bpred import cvw::*; #(parameter cvw_t P) ( // could be wrong or the fall through address selected for branch predict not taken. // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. - // **** use BPBTAWrongM from BTB. assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE; flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 7f5906084..9192a7cf5 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -47,7 +47,7 @@ module gshare import cvw::*; #(parameter cvw_t P, logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchX; - logic [1:0] TableBPDirPredF, BPDirPredD, BPDirPredE, FwdNewDirPredF; + logic [1:0] PHTBPDirPredF, BPDirPredD, BPDirPredE, FwdNewDirPredF; logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW; logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW; @@ -83,12 +83,12 @@ module gshare import cvw::*; #(parameter cvw_t P, MatchM ? {NewBPDirPredM} : NewBPDirPredW ; - assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF; + assign BPDirPredF = MatchX ? FwdNewDirPredF : PHTBPDirPredF; ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), - .rd1(TableBPDirPredF), + .rd1(PHTBPDirPredF), .wa2(IndexM), .wd2(NewBPDirPredM), .we2(BranchM),