diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh index c5ebb5de0..eb4ee4494 100755 --- a/bin/SeparateBranch.sh +++ b/bin/SeparateBranch.sh @@ -6,7 +6,10 @@ ## Modified: ## ## Purpose: Converts a single branch.log containing multiple benchmark branch outcomes into -## separate files, one for each program.x4 +## separate files, one for each program. +## Input: branch log file generated by modelsim +## output: outputs to directory branch a collection of files with the branch outcomes +## separated by benchmark application. Example names are aha-mot64bd_sizeopt_speed_branch.log ## ## A component of the CORE-V-WALLY configurable RISC-V project. ## diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 9e08f2c7a..8bf98ef5a 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -36,10 +36,15 @@ import re # [14.5859173702079, 12.3634674403619, 10.5806018170154, 8.38831266973592, 6.37097544620762, 3.52638362703015]) #} -RefData = [('twobitCModel6', 11.0501534891674), ('twobitCModel8', 8.51829052266352), ('twobitCModel10', 7.56775222626483), - ('twobitCModel12', 6.31366834586515), ('twobitCModel14', 5.72699936834177), ('twobitCModel16', 5.72699936834177), - ('gshareCModel6', 14.5731555979574), ('gshareCModel8', 12.3155658100497), ('gshareCModel10', 10.4589596630561), - ('gshareCModel12', 8.25796055444401), ('gshareCModel14', 6.23093702707613), ('gshareCModel16', 3.34001125650374)] +#RefData = [('twobitCModel6', 11.0501534891674), ('twobitCModel8', 8.51829052266352), ('twobitCModel10', 7.56775222626483), +# ('twobitCModel12', 6.31366834586515), ('twobitCModel14', 5.72699936834177), ('twobitCModel16', 5.72699936834177), +# ('gshareCModel6', 14.5731555979574), ('gshareCModel8', 12.3155658100497), ('gshareCModel10', 10.4589596630561), +# ('gshareCModel12', 8.25796055444401), ('gshareCModel14', 6.23093702707613), ('gshareCModel16', 3.34001125650374)] + +RefData = [('twobitCModel6', 9.65280765420711), ('twobitCModel8', 8.75120245829945), ('twobitCModel10', 8.1318382397263), + ('twobitCModel12', 7.53026646633342), ('twobitCModel14', 6.07679338544009), ('twobitCModel16', 6.07679338544009), + ('gshareCModel6', 10.6602835418646), ('gshareCModel8', 8.38384710559667), ('gshareCModel10', 6.36847432155534), + ('gshareCModel12', 3.91108491151983), ('gshareCModel14', 2.83926519215395), ('gshareCModel16', .60213659066941)] def ComputeCPI(benchmark): @@ -255,7 +260,7 @@ if(sys.argv[1] == '-b'): else: combined = benchmarkDict['All_'] # merge the reference data into rtl data - combined.extend(RefData) + # combined.extend(RefData) (name, value) = FormatToPlot(combined) lst = [] dct = {} diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 07f005f43..46d3ed22a 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -141,8 +141,14 @@ localparam PLIC_UART_ID = 32'd10; localparam PLIC_SDC_ID = 32'd9; localparam BPRED_SUPPORTED = 1; +// this is an annoying hack for the branch predictor parameterization override. +`ifdef BPRED_OVERRIDE +localparam BPRED_TYPE = `BPRED_TYPE; +localparam BPRED_SIZE = `BPRED_SIZE; +`else localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -localparam BPRED_SIZE = 32'd16; +localparam BPRED_SIZE = 32'd10; +`endif localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py index 4f1757cb8..4ec9324a3 100755 --- a/sim/bpred-sim.py +++ b/sim/bpred-sim.py @@ -46,33 +46,33 @@ configs = [ ) ] -# bpdSize = [6, 8, 10, 12, 14, 16] -# bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic'] -# for CurrBPType in bpdType: -# for CurrBPSize in bpdSize: -# name = CurrBPType+str(CurrBPSize) -# configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize) -# tc = TestCase( -# name=name, -# variant="rv32gc", -# cmd="vsim > {} -c < {} -c < {} -c < {} -c <