mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
simplify plic logic
This commit is contained in:
parent
69a0f6e00b
commit
0f7e995055
@ -176,11 +176,7 @@ module plic (
|
|||||||
end
|
end
|
||||||
|
|
||||||
// pending interrupt requests
|
// pending interrupt requests
|
||||||
assign nextIntPending =
|
assign nextIntPending = (intPending | requests) & ~intInProgress;
|
||||||
(intPending | // existing pending requests
|
|
||||||
(requests & ~intInProgress)) & // assert new requests (if they aren't already being serviced)
|
|
||||||
~({`N{((entry == 24'h200004) & memread)}} << (intClaim[0]-1)) & // deassert requests that just completed
|
|
||||||
~({`N{((entry == 24'h201004) & memread)}} << (intClaim[1]-1));
|
|
||||||
flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
|
flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
|
||||||
|
|
||||||
// context-dependent signals
|
// context-dependent signals
|
||||||
|
Loading…
Reference in New Issue
Block a user