diff --git a/wally-pipelined/src/sdc/SDC.sv b/wally-pipelined/src/sdc/SDC.sv new file mode 100644 index 000000000..6912c0ab7 --- /dev/null +++ b/wally-pipelined/src/sdc/SDC.sv @@ -0,0 +1,93 @@ +/////////////////////////////////////////// +// SDC.sv +// +// Written: Ross Thompson September 22, 2021 +// Modified: +// +// Purpose: SDC interface to AHBLite BUS. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +`define SDCCLKDIV 2 + +module SDC + (input logic HCLK, + input logic HRESETn, + input logic HSELSDC, + input logic [4:0] HADDR, + input logic HWRITE, + input logic HREADY, + input logic [1:0] HTRANS, + input logic [`XLEN-1:0] HWDATA, + output logic [`XLEN-1:0] HREADSDC, + output logic HRESPSDC, + output logic HREADYSDC, + + //sd card interface + // place the tristate drivers at the top. this level + // will use dedicated 1 direction ports. + output logic SDCmdOut, + input logic SDCmdIn, + output logic SDCmdOE, + input logic SDDatIn, + output logic SDCLK, + + // interrupt to PLIC + output logic SDCIntM); + + logic initTrans; + logic RegRead; + logic RegWrite; + + // *** reduce size later + logic [31:0] CLKDiv; + + + // registers + //| Offset | Name | Size | Purpose | + //|--------+---------+------+------------------------------------------------| + //| 0x0 | CLKDiv | 4 | Divide HCLK to produce SDCLK | + //| 0x4 | Status | 4 | Provide status to software | + //| 0x8 | Control | 4 | Send commands to SDC | + //| 0xC | Size | 4 | Size of data command (only 512 byte supported) | + //| 0x10 | address | 8 | address of operation | + //| 0x18 | data | 8 | Data Bus interface | + + // Currently using a mailbox style interface. Data is passed through the Data register (0x10) + // The card will support 3 operations + // 1. initialize + // 2. read + // 3. write + // all read and write operations will occur on 512 bytes (4096 bits) of data + // starting at the 512 byte aligned address in the address register This register + // is the byte address. + + // currently does not support writes + + assign InitTrans = HREADY & HSELTSDC & (HTRANS != 2'b00); + assign RegWrite = InitTrans & HWRITE; + assign RegRead = InitTrans & ~HWRITE; + + // *** need to delay + flopenl #(32) CLKDivReg(HCLK, ~HRESETn, , HADDR == '0 & RegWrite, HWRITE, `SDCCLKDIV, CLKDiv); + + +endmodule + diff --git a/wally-pipelined/src/sdc/regfile_p2r1w1_nibo.sv b/wally-pipelined/src/sdc/regfile_p2r1w1_nibo.sv index 3bb1329e4..b508ec367 100644 --- a/wally-pipelined/src/sdc/regfile_p2r1w1_nibo.sv +++ b/wally-pipelined/src/sdc/regfile_p2r1w1_nibo.sv @@ -29,11 +29,13 @@ module regfile_p2r1w1_nibo #(parameter integer DEPTH = 10, parameter integer WID input logic we1, input logic [DEPTH-1:0] ra1, output logic [WIDTH-1:0] rd1, + output logic [(2**DEPTH)*WIDTH-1:0] Rd1All, input logic [DEPTH-1:0] wa1, input logic [WIDTH-1:0] wd1); logic [WIDTH-1:0] regs [2**DEPTH-1:0]; - + genvar index; + always_ff @(posedge clk) begin if(we1) begin regs[wa1] <= wd1; @@ -41,5 +43,7 @@ module regfile_p2r1w1_nibo #(parameter integer DEPTH = 10, parameter integer WID end assign rd1 = regs[ra1]; - + for(index = 0; index < 2**DEPTH; index++) + assign Rd1All[index*WIDTH+WIDTH-1:index*WIDTH] = regs[index]; + endmodule diff --git a/wally-pipelined/src/sdc/sd_top.sv b/wally-pipelined/src/sdc/sd_top.sv index cfa3ced66..99191b501 100644 --- a/wally-pipelined/src/sdc/sd_top.sv +++ b/wally-pipelined/src/sdc/sd_top.sv @@ -46,6 +46,7 @@ module sd_top #(parameter g_COUNT_WIDTH = 8) input logic i_READ_REQUEST, // After Ready for read is sent to the core, the core will // pulse this bit high to indicate it wants the block at this address output logic [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is + output logic [4095:0] ReadData, // full 512 bytes to Bus // being published output logic o_DATA_VALID, // held high while data being read to core to indicate that it is valid output logic o_LAST_NIBBLE, // pulse when last nibble is sent @@ -408,6 +409,7 @@ module sd_top #(parameter g_COUNT_WIDTH = 8) .we1(w_NIBO_EN), .ra1(r_DAT_COUNTER_OUT[9:0]), // Nibble Read (to core) Address .rd1(r_DATA_TO_CORE), // output nibble to core + .Rd1All(ReadData), .wa1(r_DAT_COUNTER_OUT[9:0]), // Nibble Write (to host) Address .wd1(r_DAT_Q)); // input nibble from card diff --git a/wally-pipelined/src/sdc/tb/sd_top_tb.sv b/wally-pipelined/src/sdc/tb/sd_top_tb.sv index 53ec02961..11bb2cadb 100644 --- a/wally-pipelined/src/sdc/tb/sd_top_tb.sv +++ b/wally-pipelined/src/sdc/tb/sd_top_tb.sv @@ -43,7 +43,8 @@ module sd_top_tb(); logic [3:0] o_DATA_TO_CORE; logic o_DATA_VALID; logic o_LAST_NIBBLE; - + logic [4095:0] ReadData; + // Driver wire PAD; @@ -64,6 +65,7 @@ module sd_top_tb(); .o_READY_FOR_READ(o_READY_FOR_READ), .i_READ_REQUEST(i_READ_REQUEST), .o_DATA_TO_CORE(o_DATA_TO_CORE), + .ReadData(ReadData), .o_DATA_VALID(o_DATA_VALID), .o_LAST_NIBBLE(o_LAST_NIBBLE), .i_COUNT_IN_MAX(i_COUNT_IN_MAX), diff --git a/wally-pipelined/src/sdc/tb/wave.do b/wally-pipelined/src/sdc/tb/wave.do index d86158826..e41e298ae 100644 --- a/wally-pipelined/src/sdc/tb/wave.do +++ b/wally-pipelined/src/sdc/tb/wave.do @@ -107,6 +107,7 @@ add wave -noupdate /sd_top_tb/DUT/w_BLOCK_ADDR add wave -noupdate /sd_top_tb/DUT/i_BLOCK_ADDR add wave -noupdate /sd_top_tb/DUT/regfile_cmd17_data_block/regs add wave -noupdate /sd_top_tb/DUT/regfile_cmd17_data_block/ra1 +add wave -noupdate /sd_top_tb/ReadData TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {2028326 ns} 0} {{Cursor 2} {4831 ns} 0} quietly wave cursor active 1 @@ -124,4 +125,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2013966 ns} {2038576 ns} +WaveRestoreZoom {1979107 ns} {2077545 ns}