From 0f68fccf8249242a2e40d9561ec1dcade3617fe2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 20 Jan 2023 14:19:07 -0800 Subject: [PATCH] Started adding bit manipulation unit --- pipelined/config/shared/wally-constants.vh | 1 + pipelined/config/shared/wally-shared.vh | 6 +++ pipelined/src/bmu/bmu.sv | 45 ++++++++++++++++++++++ pipelined/src/ieu/datapath.sv | 11 +++++- pipelined/src/ieu/ieu.sv | 11 ++++-- pipelined/src/wally/wallypipelinedcore.sv | 19 ++++++++- 6 files changed, 85 insertions(+), 8 deletions(-) create mode 100644 pipelined/src/bmu/bmu.sv diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh index a865cfd5c..0acc12b86 100644 --- a/pipelined/config/shared/wally-constants.vh +++ b/pipelined/config/shared/wally-constants.vh @@ -52,6 +52,7 @@ // macros to define supported modes `define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA `define C_SUPPORTED ((`MISA >> 2) % 2 == 1) `define D_SUPPORTED ((`MISA >> 3) % 2 == 1) `define E_SUPPORTED ((`MISA >> 4) % 2 == 1) diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 1e961c64a..2fcb3af7a 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -26,6 +26,12 @@ `define RADIX 32'h4 `define DIVCOPIES 32'h4 +// eventually move to each config +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + // Memory synthesis configuration `define USE_SRAM 0 diff --git a/pipelined/src/bmu/bmu.sv b/pipelined/src/bmu/bmu.sv new file mode 100644 index 000000000..ba6ab0b08 --- /dev/null +++ b/pipelined/src/bmu/bmu.sv @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// bmu.sv +// +// Written: kekim@g.hmc.edu, David_Harris@hmc.edu 20 January 2023 +// Modified: +// +// Purpose: Bit manipulation extensions Zba, Zbb, Zbc, Zbs +// Single-cycle operation in Execute stage +// +// Documentation: n/a +// See RISC-V Bit-Manipulation ISA-extensions +// Version 1.0.0-38-g865e7a7, 2021-06-28: Release candidate +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module bmu( + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output + input logic [31:0] InstrD, // instruction + output logic BMUE, // bit manipulation instruction + output logic [`XLEN-1:0] BMUResultE // bit manipulation result +); + + + +endmodule // mdu + + diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 5c4ad5ef0..84e3dc9cb 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -48,6 +48,7 @@ module datapath ( output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B + input logic BMUE, // Bit manipulation instruction // Memory stage signals input logic StallM, FlushM, // Stall, flush Memory stage input logic FWriteIntM, FCvtIntW, // FPU writes integer register file, FPU converts float to int @@ -61,7 +62,9 @@ module datapath ( input logic [2:0] ResultSrcW, // Select source of result to write back to register file input logic [`XLEN-1:0] FCvtIntResW, // FPU convert fp to integer result input logic [`XLEN-1:0] ReadDataW, // Read data from LSU - input logic [`XLEN-1:0] CSRReadValW, MDUResultW, // CSR read result, MDU (Multiply/divide unit) result + input logic [`XLEN-1:0] CSRReadValW, // CSR read result + input logic [`XLEN-1:0] MDUResultW, // MDU (Multiply/divide unit) result + input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result input logic [`XLEN-1:0] FIntDivResultW, // FPU's integer divide result // Hazard Unit signals output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, // Register sources to read in Decode or Execute stage @@ -78,6 +81,7 @@ module datapath ( logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage logic [`XLEN-1:0] SrcAE, SrcBE; // ALU operands logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage + logic [`XLEN-1:0] IEUBResultE; // IEUResultE before optional bit manipulation mux // Memory stage signals logic [`XLEN-1:0] IEUResultM; // Result from execution stage logic [`XLEN-1:0] IFResultM; // Result from either IEU or single-cycle FPU op writing an integer register @@ -110,7 +114,10 @@ module datapath ( mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); - mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); + mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUBResultE); + if (`B_SUPPORTED) + mux2 #(`XLEN) bmuresultmux(IEUResultE, BMUResultE, BMUE, IEUResultE); + else assign IEUResultE = IEUBResultE; // Memory stage pipeline register flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index db0ddb2cc..fd8a74c2b 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -43,6 +43,7 @@ module ieu ( output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction output logic [2:0] Funct3E, // Funct3 instruction field output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B + input logic BMUE, // This is a bit manipulation instruction output logic [4:0] RdE, // Destination register // Memory stage signals input logic SquashSCW, // Squash store conditional, from LSU @@ -56,8 +57,10 @@ module ieu ( output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InstrValidM, // Instruction is valid // Writeback stage signals - input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt - input logic [`XLEN-1:0] CSRReadValW, MDUResultW, // CSR read value, MDU (multiply/divide unit) result + input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt) + input logic [`XLEN-1:0] CSRReadValW, // CSR read value, + input logic [`XLEN-1:0] MDUResultW, // multiply/divide unit result + input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result input logic [`XLEN-1:0] FCvtIntResW, // FPU's float to int conversion result input logic FCvtIntW, // FPU converts float to int output logic [4:0] RdW, // Destination register @@ -102,10 +105,10 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, - .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); + .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); forward fw( .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index daefca9af..2e6b63035 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -163,6 +163,10 @@ module wallypipelinedcore ( logic FCvtIntE; logic CommittedF; + // Bit manipulation unit + logic [`XLEN-1:0] BMUResultE; // Bit manipuation result BMU -> IEU + logic BMUE; // is this a BMU instruction + // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, @@ -190,7 +194,7 @@ module wallypipelinedcore ( .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE, // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU @@ -200,7 +204,7 @@ module wallypipelinedcore ( .SrcAM, // to privilege and fpu .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, // Writeback stage - .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), + .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, .FCvtIntResW, .FCvtIntW, // hazards .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, @@ -357,4 +361,15 @@ module wallypipelinedcore ( assign SetFflagsM = 0; assign FpLoadStoreM = 0; end + + // bit manipulation unit + if (`B_SUPPORTED) begin:bmu + bmu bmu(.ForwardedSrcAE, .ForwardedSrcBE, .InstrD, .BMUE, .BMUResultE); + end else begin // no B instructions supported + assign BMUResultE = 0; + assign BMUE = 0; + end + + + endmodule