From 0f36cbd830aaf9b4719c2d4ad3cad864b8f9feff Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Mon, 12 Jun 2023 12:21:25 -0700 Subject: [PATCH] Update regfile.sv Program clean up --- src/ieu/regfile.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index 5eff24022..2b76bca17 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -31,10 +31,10 @@ module regfile #(parameter XLEN, E_SUPPORTED) ( input logic clk, reset, input logic we3, // Write enable input logic [4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3) - input logic [XLEN-1:0] wd3, // Write data for port 3 - output logic [XLEN-1:0] rd1, rd2); // Read data for ports 1, 2 + input logic [XLEN-1:0] wd3, // Write data for port 3 + output logic [XLEN-1:0] rd1, rd2); // Read data for ports 1, 2 - localparam NUMREGS = E_SUPPORTED ? 16 : 32; // only 16 registers in E mode + localparam NUMREGS = E_SUPPORTED ? 16 : 32; // only 16 registers in E mode logic [XLEN-1:0] rf[NUMREGS-1:1]; integer i; @@ -50,7 +50,7 @@ module regfile #(parameter XLEN, E_SUPPORTED) ( always_ff @(negedge clk) if (reset) for(i=1; i