diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv
index 5eff24022..2b76bca17 100644
--- a/src/ieu/regfile.sv
+++ b/src/ieu/regfile.sv
@@ -31,10 +31,10 @@ module regfile #(parameter XLEN, E_SUPPORTED) (
   input  logic             clk, reset,
   input  logic             we3,                 // Write enable
   input  logic [4:0]       a1, a2, a3,          // Source registers to read (a1, a2), destination register to write (a3)
-  input  logic [XLEN-1:0] wd3,                 // Write data for port 3
-  output logic [XLEN-1:0] rd1, rd2);           // Read data for ports 1, 2
+  input  logic [XLEN-1:0]  wd3,                 // Write data for port 3
+  output logic [XLEN-1:0]  rd1, rd2);           // Read data for ports 1, 2
 
-  localparam NUMREGS = E_SUPPORTED ? 16 : 32;  // only 16 registers in E mode
+  localparam NUMREGS = E_SUPPORTED ? 16 : 32;   // only 16 registers in E mode
 
   logic [XLEN-1:0] rf[NUMREGS-1:1];
   integer i;
@@ -50,7 +50,7 @@ module regfile #(parameter XLEN, E_SUPPORTED) (
     
   always_ff @(negedge clk)
     if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= 0;
-    else       if (we3)            rf[a3] <= wd3;  
+    else       if (we3)                 rf[a3] <= wd3;  
 
   assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
   assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;