From 0f2315e8a1e2d54e2992eb12e79c82e58c24b060 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 31 Aug 2022 14:52:06 -0500 Subject: [PATCH] more renaming. --- pipelined/src/ifu/ifu.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index a6bb6a053..6f2948ec3 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -248,12 +248,12 @@ module ifu ( logic CaptureEn; logic [1:0] RW; assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}; - flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0])); + ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), + .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), + .HWSTRB(), .RW, .ByteMask(), .WriteData('0), + .CPUBusy, .BusStall, .BusCommitted(), .ReadDataWordM(AllInstrRawF[31:0])); - busfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, .CaptureEn, - .BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE)); - assign IFUHBURST = 3'b0; assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0; assign {ICacheMiss, ICacheAccess} = '0;