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https://github.com/openhwgroup/cvw
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Fixed tlbmisc testing with PBMTE = 0
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parent
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commit
0e1c53f9f6
@ -104,14 +104,17 @@ main:
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# jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0
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# jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0
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li t0, 0x80805000
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li t0, 0x80805000
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jalr ra, t0
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jalr ra, t0
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li t0, 0x80807000 # again, triggering setting access bit
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jalr ra, t0
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# Good PBMT with menvcfg.PBMTE = 0
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# Good PBMT with menvcfg.PBMTE = 0
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li t0, 3
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li a0, 3
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ecall # switch to machine mode
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ecall # switch to machine mode
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li t5, 0x1
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li t5, 0x1
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slli t5, t5, 62
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slli t5, t5, 62
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csrc menvcfg, t5 # menvcfg.PBMTE = 0
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csrc menvcfg, t5 # menvcfg.PBMTE = 0
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li t0, 1
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li a0, 1
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ecall # switch back to supervisor mode
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ecall # switch back to supervisor mode
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li t0, 0x80806000
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li t0, 0x80806000
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jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0
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jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0
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@ -365,6 +368,7 @@ pagetable:
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.8byte 0x00000000200000C3 # valid r for VA 80802000
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.8byte 0x00000000200000C3 # valid r for VA 80802000
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.8byte 0x00000000200000C9 # valid x for VA 80803000
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.8byte 0x00000000200000C9 # valid x for VA 80803000
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.8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
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.8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
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.8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA
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.8byte 0x00000000200000CF # valid rwx for VA 80805000 for covering ITLB translate
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.8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT
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.8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT
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.8byte 0x000000002000000F # valid rwx for VA 80807000 for covering UpdateDA
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