From 0e183be3e54dac19846d6c8b9edc829fae7030fe Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 14 Apr 2022 09:23:21 -0700 Subject: [PATCH] fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM --- pipelined/testbench/testbench-linux.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index b71cc4d0f..f00ca8257 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -729,8 +729,11 @@ module testbench; // New IP spoofing logic globalIntsBecomeEnabled; assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22)); + logic checkInterruptM; + assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM; + always @(negedge clk) begin - if(checkInstrM) begin + if(checkInterruptM) begin if((interruptInstrCount+1) == AttemptedInstructionCount) begin if(!NO_IE_MTIME_CHECKPOINT) begin case (interruptCauseVal)