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Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.

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This commit is contained in:
David Harris 2022-05-03 03:45:41 -07:00
parent 9e47fca2b7
commit 0df73d203b
1 changed files with 12 additions and 3 deletions
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15
pipelined/src/cache/sram1p1rw.sv vendored
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@ -45,6 +45,9 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
logic [$clog2(DEPTH)-1:0] AdrD; logic [$clog2(DEPTH)-1:0] AdrD;
logic WriteEnableD; logic WriteEnableD;
localparam WM8 = WIDTH%8;
always_ff @(posedge clk) AdrD <= Adr; always_ff @(posedge clk) AdrD <= Adr;
integer index; integer index;
@ -62,20 +65,26 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
if (WriteEnable) begin if (WriteEnable) begin
for(index = 0; index < WIDTH/8; index++) begin for(index = 0; index < WIDTH/8; index++) begin
if(ByteMask[index]) begin if(ByteMask[index]) begin
StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8]; StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
end end
end end
if (WM8 > 0) begin
if (ByteMask[WIDTH/8]) begin
StoredData[Adr][WIDTH-1:WIDTH-WM8] <= #1
CacheWriteData[WIDTH-1:WIDTH-WM8];
end
end
end end
end end
// if not a multiple of 8, MSByte is not 8 bits long. /* // if not a multiple of 8, MSByte is not 8 bits long.
if(WIDTH%8 != 0) begin if(WIDTH%8 != 0) begin
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (WriteEnable & ByteMask[WIDTH/8]) begin if (WriteEnable & ByteMask[WIDTH/8]) begin
StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8]; StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
end end
end end
end end */
assign ReadData = StoredData[AdrD]; assign ReadData = StoredData[AdrD];
endmodule endmodule