From 0dc50536ef17abdedffd6b606442c13db4967668 Mon Sep 17 00:00:00 2001 From: Sydeny Date: Sat, 15 Apr 2023 00:48:32 -0700 Subject: [PATCH] trimming comments on fctrl bug fixes --- src/fpu/fctrl.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index f0d8ca85a..c43c6e0eb 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -242,13 +242,13 @@ module fctrl ( // X - all except int->fp, store, load, mv int->fp assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store - ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float - There was an issue here, this condition was not refering to mv int -> fp // ((FResSelD==2'b11)&FRegWriteD)| + ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float ((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float // Y - all except cvt, mv, load, class, sqrt assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class - ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float as above // previously mv both ways - Another issue here, previously (FResSelD==2'b11)| does not cover mv both way int-> fp and fp-> int - ((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int // mv both ways + ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float as above + ((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt // Removed (FResSelD==2'b11)| removed to avoid redundancy