Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

update Boolean logic for all testing for divide

Browse Source
This commit is contained in:
James E. Stine 2024-01-29 17:37:35 -06:00
parent 95a97faf3f
commit 0d9e2fdf60
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
testbench/testbench-fp.sv
View File

@ -848,7 +848,7 @@ module testbenchfp;
end
S2: begin
DivStart = 1'b0;
if ((FDivBusyE)|(~DivDone))
if ((FDivBusyE|~DivDone)&(UnitVal == `DIVUNIT))
nextstate = S2;
else
nextstate = Done;
@ -960,8 +960,8 @@ module testbenchfp;
assign FMAop = (OpCtrlVal == `FMAUNIT);
assign DivDone = OldFDivBusyE & ~FDivBusyE;
assign CheckNow = ((DivDone | ~divsqrtop) |
(TEST == "all" | TEST == "add" | TEST == "fma" | TEST == "sub"))
& (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
(TEST == "add" | TEST == "fma" | TEST == "sub") |
((TEST == "all") & (DivDone | ~divsqrtop)));
if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin
errors += 1;