From 893e03d55b859ffb7ac0f1e0387c6e10d5f3afce Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 29 Apr 2021 17:36:46 -0500 Subject: [PATCH 1/3] Fixed memory size in configs for rv32ic and rv64ic. Removed warning on call to $fscanf. --- wally-pipelined/config/rv32ic/wally-config.vh | 4 ++-- wally-pipelined/config/rv64ic/wally-config.vh | 4 ++-- wally-pipelined/testbench/function_radix.sv | 6 ++++-- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index fa16fdb86..41285cfa1 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -68,8 +68,8 @@ `define BOOTTIMBASE 32'h00000000 `define BOOTTIMRANGE 32'h00003FFF -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0007FFFF +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h07FFFFFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 3ef92055a..2e0d92fb8 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -72,8 +72,8 @@ `define BOOTTIMBASE 32'h00000000 `define BOOTTIMRANGE 32'h00003FFF -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0007FFFF +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h07FFFFFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/testbench/function_radix.sv b/wally-pipelined/testbench/function_radix.sv index 20e2ff13e..5e3dff986 100644 --- a/wally-pipelined/testbench/function_radix.sv +++ b/wally-pipelined/testbench/function_radix.sv @@ -110,6 +110,8 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile); integer ProgramAddrMapLineCount, ProgramLabelMapLineCount; longint ProgramAddrMapLine; string ProgramLabelMapLine; + integer status; + // preload // initial begin @@ -123,7 +125,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile); // read line by line to count lines if (ProgramAddrMapFP) begin while (! $feof(ProgramAddrMapFP)) begin - $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine); + status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine); ProgramAddrMapLineCount = ProgramAddrMapLineCount + 1; end @@ -141,7 +143,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile); if (ProgramLabelMapFP) begin while (! $feof(ProgramLabelMapFP)) begin - $fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine); + status = $fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine); ProgramLabelMapMemory[ProgramLabelMapLineCount] = ProgramLabelMapLine; ProgramLabelMapLineCount = ProgramLabelMapLineCount + 1; end From 830787e3e1fb0281b586ea984a03377c9bce70a1 Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Thu, 29 Apr 2021 20:42:14 -0400 Subject: [PATCH 2/3] Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts --- wally-pipelined/src/privileged/csrm.sv | 2 +- wally-pipelined/src/privileged/trap.sv | 14 +++++++++++--- wally-pipelined/testbench/testbench-imperas.sv | 2 ++ 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index 5ab8fa38d..4cfc533d0 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -97,7 +97,7 @@ module csrm #(parameter ); logic [`XLEN-1:0] MISA_REGW; - logic [`XLEN-1:0] MSCRATCH_REGW,MCAUSE_REGW, MTVAL_REGW; + logic [`XLEN-1:0] MSCRATCH_REGW, MCAUSE_REGW, MTVAL_REGW; logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // 64-bit registers in RV64, or two 32-bit registers in RV32 logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15]; // *** Might have to make 16 individual registers //logic [`XLEN-1:0] PMPADDR0_REGW; diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 552ce9a4e..36cde4dad 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -27,7 +27,7 @@ `include "wally-config.vh" module trap ( - input logic reset, + input logic clk, reset, input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM, input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM, @@ -40,6 +40,7 @@ module trap ( input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [31:0] InstrM, + input logic StallW, output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic InterruptM, output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM @@ -74,11 +75,18 @@ module trap ( // Handle vectored traps (when mtvec/stvec/utvec csr value has bits [1:0] == 01) // For vectored traps, set program counter to _tvec value + 4 times the cause code + // + // POSSIBLE OPTIMIZATION: + // From 20190608 privielegd spec page 27 (3.1.7) + // > Allowing coarser alignments in Vectored mode enables vectoring to be + // > implemented without a hardware adder circuit. + // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with + // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000} generate if(`VECTORED_INTERRUPTS_SUPPORTED) begin always_comb if (PrivilegedTrapVector[1:0] == 2'b01 && CauseM[`XLEN-1] == 1) - PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00}; + PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {CauseM[`XLEN-5:0], 2'b00}, 2'b00}; else PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; end @@ -91,7 +99,7 @@ module trap ( if (mretM) PrivilegedNextPCM = MEPC_REGW; else if (sretM) PrivilegedNextPCM = SEPC_REGW; else if (uretM) PrivilegedNextPCM = UEPC_REGW; - else PrivilegedNextPCM = PrivilegedTrapVector; + else PrivilegedNextPCM = PrivilegedVectoredTrapVector; // Cause priority defined in table 3.7 of 20190608 privileged spec // Exceptions are of lower priority than all interrupts (3.1.9) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index f99ee1aff..607c921f7 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -351,6 +351,7 @@ module testbench(); "rv64p/WALLY-SEPC", "4000", "rv64p/WALLY-MTVAL", "6000", "rv64p/WALLY-STVAL", "4000", + "rv64p/WALLY-MTVEC", "2000", "rv64p/WALLY-MARCHID", "4000", "rv64p/WALLY-MIMPID", "4000", "rv64p/WALLY-MHARTID", "4000", @@ -371,6 +372,7 @@ module testbench(); "rv32p/WALLY-MHARTID", "4000", "rv32p/WALLY-MVENDORID", "4000" //"rv32p/WALLY-MEDELEG", "4000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though. + //"rv32p/WALLY-MTVEC", "2000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though. }; string tests64periph[] = '{ From c9fcd3405d60ec364b01aec7b1005d2657cbda0b Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 29 Apr 2021 20:59:30 -0400 Subject: [PATCH 3/3] rollback regression to 400k instrs for busybear --- wally-pipelined/regression/regression-wally.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index d249d7ff0..2b272e3b4 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -19,7 +19,7 @@ configs = [ Config( name="busybear", cmd="vsim -do wally-busybear-batch.do -c > {}", - grepstr="# loaded 800000 instructions" + grepstr="# loaded 40000 instructions" ), Config( name="buildroot",