mirror of
https://github.com/openhwgroup/cvw
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Merge pull request #415 from ross144/main
added new branch predictor post processing script and updated buildroot config script to support c++
This commit is contained in:
David Harris
GitHub
commit
0d0d5d8af0
620
bin/parseHPMC.py
620
bin/parseHPMC.py
@ -1,8 +1,8 @@
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#!/usr/bin/python3
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###########################################
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## Written: Ross Thompson ross1728@gmail.com
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## Created: 4 Jan 2022
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## Written: Rose Thompson ross1728@gmail.com
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## Created: 20 September 2023
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## Modified:
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##
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## Purpose: Parses the performance counters from a modelsim trace.
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@ -28,110 +28,29 @@
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import os
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import sys
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import matplotlib.pyplot as plt
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import re
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import math
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import numpy as np
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import argparse
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#RefData={'twobitCModel' :(['6', '8', '10', '12', '14', '16'],
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# [11.0680836450622, 8.53864970807778, 7.59565430177984, 6.38741598498948, 5.83662961500838, 5.83662961500838]),
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# 'gshareCModel' : (['6', '8', '10', '12', '14', '16'],
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# [14.5859173702079, 12.3634674403619, 10.5806018170154, 8.38831266973592, 6.37097544620762, 3.52638362703015])
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#}
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RefData = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
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('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009),
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('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534),
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('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)]
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#RefData = [('twobitCModel6', 11.0501534891674), ('twobitCModel8', 8.51829052266352), ('twobitCModel10', 7.56775222626483),
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# ('twobitCModel12', 6.31366834586515), ('twobitCModel14', 5.72699936834177), ('twobitCModel16', 5.72699936834177),
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# ('gshareCModel6', 14.5731555979574), ('gshareCModel8', 12.3155658100497), ('gshareCModel10', 10.4589596630561),
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# ('gshareCModel12', 8.25796055444401), ('gshareCModel14', 6.23093702707613), ('gshareCModel16', 3.34001125650374)]
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RefData = [('twobitCModel6', 9.65280765420711), ('twobitCModel8', 8.75120245829945), ('twobitCModel10', 8.1318382397263),
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('twobitCModel12', 7.53026646633342), ('twobitCModel14', 6.07679338544009), ('twobitCModel16', 6.07679338544009),
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('gshareCModel6', 10.6602835418646), ('gshareCModel8', 8.38384710559667), ('gshareCModel10', 6.36847432155534),
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('gshareCModel12', 3.91108491151983), ('gshareCModel14', 2.83926519215395), ('gshareCModel16', .60213659066941)]
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def ComputeCPI(benchmark):
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'Computes and inserts CPI into benchmark stats.'
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(nameString, opt, dataDict) = benchmark
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CPI = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
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dataDict['CPI'] = CPI
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def ComputeBranchDirMissRate(benchmark):
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'Computes and inserts branch direction miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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branchDirMissRate = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
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dataDict['BDMR'] = branchDirMissRate
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def ComputeBranchTargetMissRate(benchmark):
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'Computes and inserts branch target miss prediction rate.'
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# *** this is wrong in the verilog test bench
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(nameString, opt, dataDict) = benchmark
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branchTargetMissRate = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
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dataDict['BTMR'] = branchTargetMissRate
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def ComputeRASMissRate(benchmark):
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'Computes and inserts return address stack miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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RASMPR = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
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dataDict['RASMPR'] = RASMPR
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def ComputeInstrClassMissRate(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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ClassMPR = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
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dataDict['ClassMPR'] = ClassMPR
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def ComputeICacheMissRate(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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ICacheMR = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
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dataDict['ICacheMR'] = ICacheMR
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def ComputeICacheMissTime(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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cycles = int(dataDict['I Cache Miss'])
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if(cycles == 0): ICacheMR = 0
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else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
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dataDict['ICacheMT'] = ICacheMR
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def ComputeDCacheMissRate(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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DCacheMR = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
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dataDict['DCacheMR'] = DCacheMR
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def ComputeDCacheMissTime(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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cycles = int(dataDict['D Cache Miss'])
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if(cycles == 0): DCacheMR = 0
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else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
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dataDict['DCacheMT'] = DCacheMR
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def ComputeAll(benchmarks):
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for benchmark in benchmarks:
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ComputeCPI(benchmark)
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ComputeBranchDirMissRate(benchmark)
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ComputeBranchTargetMissRate(benchmark)
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ComputeRASMissRate(benchmark)
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ComputeInstrClassMissRate(benchmark)
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ComputeICacheMissRate(benchmark)
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ComputeICacheMissTime(benchmark)
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ComputeDCacheMissRate(benchmark)
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ComputeDCacheMissTime(benchmark)
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def printStats(benchmark):
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(nameString, opt, dataDict) = benchmark
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print('Test', nameString)
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print('Compile configuration', opt)
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print('CPI \t\t\t %1.2f' % dataDict['CPI'])
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print('Branch Dir Pred Miss Rate %2.2f' % dataDict['BDMR'])
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print('Branch Target Pred Miss Rate %2.2f' % dataDict['BTMR'])
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print('RAS Miss Rate \t\t %1.2f' % dataDict['RASMPR'])
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print('Instr Class Miss Rate %1.2f' % dataDict['ClassMPR'])
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print('I Cache Miss Rate %1.4f' % dataDict['ICacheMR'])
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print('I Cache Miss Ave Cycles %1.4f' % dataDict['ICacheMT'])
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print('D Cache Miss Rate %1.4f' % dataDict['DCacheMR'])
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print('D Cache Miss Ave Cycles %1.4f' % dataDict['DCacheMT'])
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print()
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def ParseBranchListFile(path):
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'''Take the path to the list of Questa Sim log files containing the performance counters outputs. File
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is formated in row columns. Each row is a trace with the file, branch predictor type, and the parameters.
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parameters can be any number and depend on the predictor type. Returns a list of lists.'''
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lst = []
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BranchList = open(path, 'r')
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for line in BranchList:
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tokens = line.split()
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predictorLog = os.path.dirname(path) + '/' + tokens[0]
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predictorType = tokens[1]
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predictorParams = tokens[2::]
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lst.append([predictorLog, predictorType, predictorParams])
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#print(predictorLog, predictorType, predictorParams)
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return lst
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def ProcessFile(fileName):
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'''Extract preformance counters from a modelsim log. Outputs a list of tuples for each test/benchmark.
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@ -150,43 +69,37 @@ def ProcessFile(fileName):
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HPMClist = { }
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elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
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countToken = line.split('=')[1].split()
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value = int(countToken[0])
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value = int(countToken[0]) if countToken[0] != 'x' else 0
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name = ' '.join(countToken[1:])
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HPMClist[name] = value
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elif ('is done' in line):
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benchmarks.append((testName, opt, HPMClist))
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return benchmarks
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def ComputeArithmeticAverage(benchmarks):
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average = {}
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index = 0
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for (testName, opt, HPMClist) in benchmarks:
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for field in HPMClist:
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value = HPMClist[field]
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if field not in average:
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average[field] = value
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else:
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average[field] += value
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index += 1
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benchmarks.append(('All', '', average))
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def FormatToPlot(currBenchmark):
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names = []
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values = []
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for config in currBenchmark:
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#print ('config' , config)
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names.append(config[0])
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values.append(config[1])
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return (names, values)
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def ComputeStats(benchmarks):
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for benchmark in benchmarks:
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(nameString, opt, dataDict) = benchmark
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dataDict['CPI'] = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
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dataDict['BDMR'] = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
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dataDict['BTMR'] = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
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dataDict['RASMPR'] = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
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dataDict['ClassMPR'] = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
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dataDict['ICacheMR'] = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
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cycles = int(dataDict['I Cache Miss'])
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if(cycles == 0): ICacheMR = 0
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else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
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dataDict['ICacheMT'] = ICacheMR
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dataDict['DCacheMR'] = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
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(nameString, opt, dataDict) = benchmark
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cycles = int(dataDict['D Cache Miss'])
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if(cycles == 0): DCacheMR = 0
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else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
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dataDict['DCacheMT'] = DCacheMR
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def GeometricAverage(benchmarks, field):
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Product = 1
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index = 0
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for (testName, opt, HPMCList) in benchmarks:
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#print(HPMCList)
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Product *= HPMCList[field]
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index += 1
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return Product ** (1.0/index)
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def ComputeGeometricAverage(benchmarks):
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fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR', 'CPI', 'ICacheMT', 'DCacheMT']
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@ -196,129 +109,362 @@ def ComputeGeometricAverage(benchmarks):
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index = 0
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for (testName, opt, HPMCList) in benchmarks:
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#print(HPMCList)
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Product *= HPMCList[field]
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value = HPMCList[field]
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if(value != 0): Product *= value # if that value is 0 exclude from mean because it destories the geo mean
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index += 1
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AllAve[field] = Product ** (1.0/index)
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benchmarks.append(('All', '', AllAve))
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benchmarks.append(('Mean', '', AllAve))
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if(sys.argv[1] == '-b'):
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configList = []
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summery = 0
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if(sys.argv[2] == '-s'):
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summery = 1
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sys.argv = sys.argv[1::]
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for config in sys.argv[2::]:
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benchmarks = ProcessFile(config)
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#ComputeArithmeticAverage(benchmarks)
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ComputeAll(benchmarks)
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ComputeGeometricAverage(benchmarks)
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#print('CONFIG: %s GEO MEAN: %f' % (config, GeometricAverage(benchmarks, 'BDMR')))
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configList.append((config.split('.')[0], benchmarks))
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def GenerateName(predictorType, predictorParams):
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if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras'):
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return predictorType + predictorParams[0]
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elif(predictorParams == 'local'):
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return predictorType + predictorParams[0] + '_' + predictorParams[1]
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else:
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print(f'Error unsupported predictor type {predictorType}')
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sys.exit(-1)
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# Merge all configruations into a single list
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benchmarkAll = []
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for (config, benchmarks) in configList:
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#print(config)
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def ComputePredNumEntries(predictorType, predictorParams):
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if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
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return 2**int(predictorParams[0])
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elif(predictorType == 'ras'):
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return int(predictorParams[0])
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elif(predictorParams == 'local'):
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return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
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else:
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print(f'Error unsupported predictor type {predictorType}')
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sys.exit(-1)
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def BuildDataBase(predictorLogs):
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# Once done with the following loop, performanceCounterList will contain the predictor type and size along with the
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# raw performance counter data and the processed data on a per benchmark basis. It also includes the geometric mean.
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# list
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# branch predictor configuration 0 (tuple)
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# benchmark name
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# compiler optimization
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# data (dictionary)
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# dictionary of performance counters
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# branch predictor configuration 1 (tuple)
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# benchmark name (dictionary)
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# compiler optimization
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# data
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# dictionary of performance counters
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# ...
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performanceCounterList = []
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for trace in predictorLogs:
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predictorLog = trace[0]
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predictorType = trace[1]
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predictorParams = trace[2]
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# Extract the performance counter data
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performanceCounters = ProcessFile(predictorLog)
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ComputeStats(performanceCounters)
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ComputeGeometricAverage(performanceCounters)
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#print(performanceCounters)
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performanceCounterList.append([GenerateName(predictorType, predictorParams), predictorType, performanceCounters, ComputePredNumEntries(predictorType, predictorParams)])
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return performanceCounterList
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def ReorderDataBase(performanceCounterList):
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# Reorder the data so the benchmark name comes first, then the branch predictor configuration
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benchmarkFirstList = []
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for (predictorName, predictorPrefixName, benchmarks, entries) in performanceCounterList:
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for benchmark in benchmarks:
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(nameString, opt, dataDict) = benchmark
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#print("BENCHMARK")
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#print(nameString)
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#print(opt)
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#print(dataDict)
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benchmarkAll.append((nameString, opt, config, dataDict))
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#print('ALL!!!!!!!!!!')
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#for bench in benchmarkAll:
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# print('BENCHMARK')
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# print(bench)
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#print('ALL!!!!!!!!!!')
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benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, dataDict))
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return benchmarkFirstList
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def ExtractSelectedData(benchmarkFirstList):
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# now extract all branch prediction direction miss rates for each
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# namestring + opt, config
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benchmarkDict = { }
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for benchmark in benchmarkAll:
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(name, opt, config, dataDict) = benchmark
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if name+'_'+opt in benchmarkDict:
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benchmarkDict[name+'_'+opt].append((config, dataDict['BDMR']))
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for benchmark in benchmarkFirstList:
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(name, opt, config, prefixName, entries, dataDict) = benchmark
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if opt == 'bd_speedopt_speed': NewName = name+'Sp'
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elif opt == 'bd_sizeopt_speed': NewName = name+'Sz'
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else: NewName = name
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#print(NewName)
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#NewName = name+'_'+opt
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if NewName in benchmarkDict:
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benchmarkDict[NewName].append((config, prefixName, entries, dataDict[ReportPredictorType]))
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else:
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benchmarkDict[name+'_'+opt] = [(config, dataDict['BDMR'])]
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benchmarkDict[NewName] = [(config, prefixName, entries, dataDict[ReportPredictorType])]
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return benchmarkDict
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size = len(benchmarkDict)
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index = 1
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if(summery == 0):
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#print('Number of plots', size)
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def ReportAsTable(benchmarkDict):
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refLine = benchmarkDict['Mean']
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FirstLine = []
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SecondLine = []
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for (name, typ, size, val) in refLine:
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FirstLine.append(name)
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SecondLine.append(size)
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for benchmarkName in benchmarkDict:
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currBenchmark = benchmarkDict[benchmarkName]
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(names, values) = FormatToPlot(currBenchmark)
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print(names, values)
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plt.subplot(6, 7, index)
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plt.bar(names, values)
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plt.title(benchmarkName)
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plt.ylabel('BR Dir Miss Rate (%)')
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#plt.xlabel('Predictor')
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index += 1
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else:
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combined = benchmarkDict['All_']
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# merge the reference data into rtl data
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# combined.extend(RefData)
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(name, value) = FormatToPlot(combined)
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lst = []
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dct = {}
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category = []
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length = []
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accuracy = []
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for index in range(0, len(name)):
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match = re.match(r"([a-z]+)([0-9]+)", name[index], re.I)
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percent = 100 -value[index]
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if match:
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(PredType, size) = match.groups()
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category.append(PredType)
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length.append(size)
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accuracy.append(percent)
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if(PredType not in dct):
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dct[PredType] = ([size], [percent])
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else:
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(currSize, currPercent) = dct[PredType]
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currSize.append(size)
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currPercent.append(percent)
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dct[PredType] = (currSize, currPercent)
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print(dct)
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sys.stdout.write('benchmark\t\t')
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for name in FirstLine:
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if(len(name) < 8): sys.stdout.write('%s\t\t' % name)
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else: sys.stdout.write('%s\t' % name)
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sys.stdout.write('\n')
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sys.stdout.write('size\t\t\t')
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for size in SecondLine:
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if(len(str(size)) < 8): sys.stdout.write('%d\t\t' % size)
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else: sys.stdout.write('%d\t' % size)
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sys.stdout.write('\n')
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||||
if(args.summary):
|
||||
sys.stdout.write('Mean\t\t\t')
|
||||
for (name, typ, size, val) in refLine:
|
||||
sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 - val))
|
||||
sys.stdout.write('\n')
|
||||
|
||||
if(not args.summary):
|
||||
for benchmark in benchmarkDict:
|
||||
length = len(benchmark)
|
||||
if(length < 8): sys.stdout.write('%s\t\t\t' % benchmark)
|
||||
elif(length < 16): sys.stdout.write('%s\t\t' % benchmark)
|
||||
else: sys.stdout.write('%s\t' % benchmark)
|
||||
for (name, typ, size, val) in benchmarkDict[benchmark]:
|
||||
sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 -val))
|
||||
sys.stdout.write('\n')
|
||||
|
||||
def ReportAsText(benchmarkDict):
|
||||
if(args.summary):
|
||||
mean = benchmarkDict['Mean']
|
||||
print('Mean')
|
||||
for (name, typ, size, val) in mean:
|
||||
sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
|
||||
|
||||
if(not args.summary):
|
||||
for benchmark in benchmarkDict:
|
||||
print(benchmark)
|
||||
for (name, type, size, val) in benchmarkDict[benchmark]:
|
||||
sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
|
||||
|
||||
def Inversion(lst):
|
||||
return [x if not args.invert else 100 - x for x in lst]
|
||||
|
||||
def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName):
|
||||
index = 0
|
||||
NumberInGroup = len(seriesDict)
|
||||
# Figure out width of bars. NumberInGroup bars + want 2 bar space
|
||||
# the space between groups is 1
|
||||
EffectiveNumInGroup = NumberInGroup + 2
|
||||
barWidth = 1 / EffectiveNumInGroup
|
||||
fig = plt.subplots(figsize = (EffectiveNumInGroup*BenchPerRow/8, 4))
|
||||
colors = ['blue', 'blue', 'blue', 'blue', 'blue', 'blue', 'black', 'black', 'black', 'black', 'black', 'black']
|
||||
for name in seriesDict:
|
||||
xpos = np.arange(BenchPerRow)
|
||||
xpos = [x + index*barWidth for x in xpos]
|
||||
values = seriesDict[name]
|
||||
plt.bar(xpos, Inversion(values), width=barWidth, edgecolor='grey', label=name, color=colors[index%len(colors)])
|
||||
index += 1
|
||||
plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, BenchPerRow)], xlabelList)
|
||||
plt.xlabel('Benchmark')
|
||||
if(not args.invert): plt.ylabel('Misprediction Rate (%)')
|
||||
else: plt.ylabel('Prediction Accuracy (%)')
|
||||
plt.legend(loc='upper left', ncol=2)
|
||||
plt.savefig(FileName)
|
||||
|
||||
def SelectPartition(xlabelListBig, seriesDictBig, group, BenchPerRow):
|
||||
seriesDictTrunk = {}
|
||||
for benchmarkName in seriesDictBig:
|
||||
lst = seriesDictBig[benchmarkName]
|
||||
seriesDictTrunk[benchmarkName] = lst[group*BenchPerRow:(group+1)*BenchPerRow]
|
||||
xlabelListTrunk = xlabelListBig[group*BenchPerRow:(group+1)*BenchPerRow]
|
||||
return(xlabelListTrunk, seriesDictTrunk)
|
||||
|
||||
|
||||
def ReportAsGraph(benchmarkDict, bar):
|
||||
def FormatToPlot(currBenchmark):
|
||||
names = []
|
||||
sizes = []
|
||||
values = []
|
||||
typs = []
|
||||
for config in currBenchmark:
|
||||
names.append(config[0])
|
||||
sizes.append(config[1])
|
||||
values.append(config[2])
|
||||
typs.append(config[3])
|
||||
return (names, sizes, values, typs)
|
||||
titlesInvert = {'BDMR' : 'Branch Direction Accuracy',
|
||||
'BTMR' : 'Branch Target Accuracy',
|
||||
'RASMPR': 'RAS Accuracy',
|
||||
'ClassMPR': 'Class Prediction Accuracy'}
|
||||
titles = {'BDMR' : 'Branch Direction Misprediction',
|
||||
'BTMR' : 'Branch Target Misprediction',
|
||||
'RASMPR': 'RAS Misprediction',
|
||||
'ClassMPR': 'Class Misprediction'}
|
||||
if(args.summary):
|
||||
markers = ['x', '.', '+', '*', '^', 'o', ',', 's']
|
||||
colors = ['blue', 'black', 'gray', 'dodgerblue', 'lightsteelblue', 'turquoise', 'black', 'blue']
|
||||
temp = benchmarkDict['Mean']
|
||||
|
||||
# the benchmarkDict['Mean'] contains sequencies of results for multiple
|
||||
# branch predictors with various parameterizations
|
||||
# group the parameterizations by the common typ.
|
||||
sequencies = {}
|
||||
for (name, typ, size, value) in benchmarkDict['Mean']:
|
||||
if not typ in sequencies:
|
||||
sequencies[typ] = [(size, value)]
|
||||
else:
|
||||
sequencies[typ].append((size,value))
|
||||
# then graph the common typ as a single line+scatter plot
|
||||
# finally repeat for all typs of branch predictors and overlay
|
||||
fig, axes = plt.subplots()
|
||||
marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*', 'tenlocal' : '.', 'eightlocal' : ',', 'fourlocal' : 'x', 'tenlocalahead' : '.', 'eightlocalahead' : ',', 'fourlocalahead' : 'x', 'tenlocalrepair' : 'x'}
|
||||
colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue', 'tenlocal' : 'lightblue', 'eightlocal' : 'lightblue', 'fourlocal' : 'lightblue', 'tenlocalahead' : 'lightblue', 'eightlocalahead' : 'lightblue', 'fourlocalahead' : 'lightblue', 'tenlocalrepair' : 'lightblue'}
|
||||
for cat in dct:
|
||||
(x, y) = dct[cat]
|
||||
x=[int(2**int(v)) for v in x]
|
||||
#print(x, y)
|
||||
print(cat)
|
||||
axes.plot(x,y, color=colors[cat])
|
||||
axes.scatter(x,y, label=cat, marker=marker[cat], color=colors[cat])
|
||||
#plt.scatter(x, y, label=cat)
|
||||
#plt.plot(x, y)
|
||||
#axes.set_xticks([4, 6, 8, 10, 12, 14])
|
||||
index = 0
|
||||
if(args.invert): plt.title(titlesInvert[ReportPredictorType])
|
||||
else: plt.title(titles[ReportPredictorType])
|
||||
for branchPredName in sequencies:
|
||||
data = sequencies[branchPredName]
|
||||
(xdata, ydata) = zip(*data)
|
||||
if args.invert: ydata = [100 - x for x in ydata]
|
||||
axes.plot(xdata, ydata, color=colors[index])
|
||||
axes.scatter(xdata, ydata, label=branchPredName, color=colors[index], marker=markers[index])
|
||||
index = (index + 1) % len(markers)
|
||||
axes.legend(loc='upper left')
|
||||
axes.set_xscale("log")
|
||||
axes.set_ylabel('Prediction Accuracy')
|
||||
axes.set_xlabel('Entries')
|
||||
axes.set_xticks([64, 256, 1024, 4096, 16384, 65536])
|
||||
axes.set_xticklabels([64, 256, 1024, 4096, 16384, 65536])
|
||||
axes.set_xticks(xdata)
|
||||
axes.set_xticklabels(xdata)
|
||||
axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
|
||||
plt.show()
|
||||
plt.show()
|
||||
|
||||
|
||||
else:
|
||||
# steps 1 and 2
|
||||
benchmarks = ProcessFile(sys.argv[1])
|
||||
print(benchmarks[0])
|
||||
ComputeAll(benchmarks)
|
||||
ComputeGeometricAverage(benchmarks)
|
||||
# 3 process into useful data
|
||||
# cache hit rates
|
||||
# cache fill time
|
||||
# branch predictor status
|
||||
# hazard counts
|
||||
# CPI
|
||||
# instruction distribution
|
||||
for benchmark in benchmarks:
|
||||
printStats(benchmark)
|
||||
# if(not args.summary):
|
||||
# size = len(benchmarkDict)
|
||||
# sizeSqrt = math.sqrt(size)
|
||||
# isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
|
||||
# numCol = math.floor(sizeSqrt)
|
||||
# numRow = numCol + (0 if isSquare else 1)
|
||||
# index = 1
|
||||
# fig = plt.figure()
|
||||
# for benchmarkName in benchmarkDict:
|
||||
# currBenchmark = benchmarkDict[benchmarkName]
|
||||
# (names, typs, sizes, values) = FormatToPlot(currBenchmark)
|
||||
# #axes.plot(numRow, numCol, index)
|
||||
# ax = fig.add_subplot(numRow, numCol, index)
|
||||
# ax.bar(names, values)
|
||||
# ax.title.set_text(benchmarkName)
|
||||
# #plt.ylabel('BR Dir Miss Rate (%)')
|
||||
# #plt.xlabel('Predictor')
|
||||
# index += 1
|
||||
|
||||
if(not args.summary):
|
||||
size = len(benchmarkDict)
|
||||
sizeSqrt = math.sqrt(size)
|
||||
isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
|
||||
numCol = math.floor(sizeSqrt)
|
||||
numRow = numCol + (0 if isSquare else 1)
|
||||
index = 1
|
||||
BenchPerRow = 7
|
||||
|
||||
xlabelList = []
|
||||
seriesDict = {}
|
||||
|
||||
for benchmarkName in benchmarkDict:
|
||||
currBenchmark = benchmarkDict[benchmarkName]
|
||||
xlabelList.append(benchmarkName)
|
||||
for (name, typ, size, value) in currBenchmark:
|
||||
if(name not in seriesDict):
|
||||
seriesDict[name] = [value]
|
||||
else:
|
||||
seriesDict[name].append(value)
|
||||
if(index >= BenchPerRow): break
|
||||
index += 1
|
||||
|
||||
xlabelListBig = []
|
||||
seriesDictBig = {}
|
||||
for benchmarkName in benchmarkDict:
|
||||
currBenchmark = benchmarkDict[benchmarkName]
|
||||
xlabelListBig.append(benchmarkName)
|
||||
for (name, typ, size, value) in currBenchmark:
|
||||
if(name not in seriesDictBig):
|
||||
seriesDictBig[name] = [value]
|
||||
else:
|
||||
seriesDictBig[name].append(value)
|
||||
|
||||
#The next step will be to split the benchmarkDict into length BenchPerRow pieces then repeat the following code
|
||||
# on each piece.
|
||||
for row in range(0, math.ceil(39 / BenchPerRow)):
|
||||
(xlabelListTrunk, seriesDictTrunk) = SelectPartition(xlabelListBig, seriesDictBig, row, BenchPerRow)
|
||||
FileName = 'barSegment%d.png' % row
|
||||
groupLen = len(xlabelListTrunk)
|
||||
BarGraph(seriesDictTrunk, xlabelListTrunk, groupLen, FileName)
|
||||
|
||||
|
||||
# main
|
||||
parser = argparse.ArgumentParser(description='Parses performance counters from a Questa Sim trace to produce a graph or graphs.')
|
||||
|
||||
# parse program arguments
|
||||
metric = parser.add_mutually_exclusive_group()
|
||||
metric.add_argument('-r', '--ras', action='store_const', help='Plot return address stack (RAS) performance.', default=False, const=True)
|
||||
metric.add_argument('-d', '--direction', action='store_const', help='Plot direction prediction (2-bit, Gshare, local, etc) performance.', default=False, const=True)
|
||||
metric.add_argument('-t', '--target', action='store_const', help='Plot branch target buffer (BTB) performance.', default=False, const=True)
|
||||
metric.add_argument('-c', '--iclass', action='store_const', help='Plot instruction classification performance.', default=False, const=True)
|
||||
|
||||
parser.add_argument('-s', '--summary', action='store_const', help='Show only the geometric average for all benchmarks.', default=False, const=True)
|
||||
parser.add_argument('-b', '--bar', action='store_const', help='Plot graphs.', default=False, const=True)
|
||||
parser.add_argument('-g', '--reference', action='store_const', help='Include the golden reference model from branch-predictor-simulator. Data stored statically at the top of %(prog)s. If you need to regenreate use CModelBranchAcurracy.sh', default=False, const=True)
|
||||
parser.add_argument('-i', '--invert', action='store_const', help='Invert metric. Example Branch miss prediction becomes prediction accuracy. 100 - miss rate', default=False, const=True)
|
||||
|
||||
displayMode = parser.add_mutually_exclusive_group()
|
||||
displayMode.add_argument('--text', action='store_const', help='Display in text format only.', default=False, const=True)
|
||||
displayMode.add_argument('--table', action='store_const', help='Display in text format only.', default=False, const=True)
|
||||
displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True)
|
||||
displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True)
|
||||
parser.add_argument('sources', nargs=1)
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
# Figure what we are reporting
|
||||
ReportPredictorType = 'BDMR' # default
|
||||
if(args.ras): ReportPredictorType = 'RASMPR'
|
||||
if(args.target): ReportPredictorType = 'BTMR'
|
||||
if(args.iclass): ReportPredictorType = 'ClassMPR'
|
||||
|
||||
# Figure how we are displaying the data
|
||||
ReportMode = 'gui' # default
|
||||
if(args.text): ReportMode = 'text'
|
||||
if(args.table): ReportMode = 'table'
|
||||
if(args.debug): ReportMode = 'debug'
|
||||
|
||||
# read the questa sim list file.
|
||||
# row, col format. each row is a questa sim run with performance counters and a particular
|
||||
# branch predictor type and size. size can be multiple parameters for more complex predictors like
|
||||
# local history and tage.
|
||||
# <file> <type> <size>
|
||||
predictorLogs = ParseBranchListFile(args.sources[0]) # digests the traces
|
||||
performanceCounterList = BuildDataBase(predictorLogs) # builds a database of performance counters by trace and then by benchmark
|
||||
benchmarkFirstList = ReorderDataBase(performanceCounterList) # reorder first by benchmark then trace
|
||||
benchmarkDict = ExtractSelectedData(benchmarkFirstList) # filters to just the desired performance counter metric
|
||||
|
||||
if(args.reference): benchmarkDict['Mean'].extend(RefData)
|
||||
#print(benchmarkDict['Mean'])
|
||||
#print(benchmarkDict['aha-mont64Speed'])
|
||||
#print(benchmarkDict)
|
||||
|
||||
# table format
|
||||
if(ReportMode == 'table'):
|
||||
ReportAsTable(benchmarkDict)
|
||||
|
||||
if(ReportMode == 'text'):
|
||||
ReportAsText(benchmarkDict)
|
||||
|
||||
if(ReportMode == 'gui'):
|
||||
ReportAsGraph(benchmarkDict, args.bar)
|
||||
|
||||
# *** this is only needed of -b (no -s)
|
||||
|
||||
# debug
|
||||
#config0 = performanceCounterList[0][0]
|
||||
#data0 = performanceCounterList[0][1]
|
||||
#bench0 = data0[0]
|
||||
#bench0name = bench0[0]
|
||||
#bench0data = bench0[2]
|
||||
#bench0BrCount = bench0data['Br Count']
|
||||
#bench1 = data0[1]
|
||||
|
||||
#print(data0)
|
||||
#print(bench0)
|
||||
#print(bench1)
|
||||
|
||||
#print(bench0name)
|
||||
#print(bench0BrCount)
|
||||
|
||||
@ -142,6 +142,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
|
||||
@ -156,6 +156,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BPRED_SIZE = 32'd12;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -144,6 +144,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -150,7 +150,13 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
`endif
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
`ifdef BTB_OVERRIDE
|
||||
localparam BTB_SIZE = `BTB_SIZE;
|
||||
localparam RAS_SIZE = `RAS_SIZE;
|
||||
`else
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
`endif
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -144,6 +144,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -143,6 +143,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -146,6 +146,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -147,8 +147,9 @@ localparam PLIC_SDC_ID = 32'd9;
|
||||
localparam BPRED_SUPPORTED = 1;
|
||||
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_SIZE = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -146,6 +146,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
@ -89,6 +89,7 @@ localparam cvw_t P = '{
|
||||
BPRED_SIZE : BPRED_SIZE,
|
||||
BPRED_NUM_LHR : BPRED_NUM_LHR,
|
||||
BTB_SIZE : BTB_SIZE,
|
||||
RAS_SIZE : RAS_SIZE,
|
||||
RADIX : RADIX,
|
||||
DIVCOPIES : DIVCOPIES,
|
||||
ZBA_SUPPORTED : ZBA_SUPPORTED,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -9,7 +9,7 @@
|
||||
chosen {
|
||||
linux,initrd-end = <0x85c43a00>;
|
||||
linux,initrd-start = <0x84200000>;
|
||||
bootargs = "root=/dev/vda ro";
|
||||
bootargs = "root=/dev/vda ro console=ttyS0,115200";
|
||||
stdout-path = "/soc/uart@10000000";
|
||||
};
|
||||
|
||||
|
||||
12
sim/bp-results/branch-list.txt
Normal file
12
sim/bp-results/branch-list.txt
Normal file
@ -0,0 +1,12 @@
|
||||
gshare6.log gshare 6
|
||||
gshare8.log gshare 8
|
||||
gshare10.log gshare 10
|
||||
gshare12.log gshare 12
|
||||
gshare14.log gshare 14
|
||||
gshare16.log gshare 16
|
||||
twobit6.log twobit 6
|
||||
twobit8.log twobit 8
|
||||
twobit10.log twobit 10
|
||||
twobit12.log twobit 12
|
||||
twobit14.log twobit 14
|
||||
twobit16.log twobit 16
|
||||
6
sim/bp-results/btb-list.txt
Normal file
6
sim/bp-results/btb-list.txt
Normal file
@ -0,0 +1,6 @@
|
||||
btb6.log btb 6
|
||||
btb8.log btb 8
|
||||
btb10.log btb 10
|
||||
btb12.log btb 12
|
||||
btb14.log btb 14
|
||||
btb16.log btb 16
|
||||
6
sim/bp-results/class-list.txt
Normal file
6
sim/bp-results/class-list.txt
Normal file
@ -0,0 +1,6 @@
|
||||
class6.log class 6
|
||||
class8.log class 8
|
||||
class10.log class 10
|
||||
class12.log class 12
|
||||
class14.log class 14
|
||||
class16.log class 16
|
||||
5
sim/bp-results/ras-list.txt
Normal file
5
sim/bp-results/ras-list.txt
Normal file
@ -0,0 +1,5 @@
|
||||
ras3.log ras 3
|
||||
ras4.log ras 4
|
||||
ras6.log ras 6
|
||||
ras10.log ras 10
|
||||
ras16.log ras 16
|
||||
@ -46,18 +46,40 @@ configs = [
|
||||
)
|
||||
]
|
||||
|
||||
bpdSize = [6, 8, 10, 12, 14, 16]
|
||||
bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
|
||||
for CurrBPType in bpdType:
|
||||
for CurrBPSize in bpdSize:
|
||||
name = CurrBPType+str(CurrBPSize)
|
||||
configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=" + str(bpdType.index(CurrBPType)) + "+define+BPRED_SIZE=" + str(CurrBPSize)
|
||||
tc = TestCase(
|
||||
name=name,
|
||||
variant="rv32gc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
grepstr="")
|
||||
configs.append(tc)
|
||||
# bpdSize = [6, 8, 10, 12, 14, 16]
|
||||
# bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
|
||||
# for CurrBPType in bpdType:
|
||||
# for CurrBPSize in bpdSize:
|
||||
# name = CurrBPType+str(CurrBPSize)
|
||||
# configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=" + str(bpdType.index(CurrBPType)) + "+define+BPRED_SIZE=" + str(CurrBPSize)
|
||||
# tc = TestCase(
|
||||
# name=name,
|
||||
# variant="rv32gc",
|
||||
# cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
# grepstr="")
|
||||
# configs.append(tc)
|
||||
|
||||
# bpdSize = [6, 8, 10, 12, 14, 16]
|
||||
# for CurrBPSize in bpdSize:
|
||||
# name = 'BTB'+str(CurrBPSize)
|
||||
# configOptions = "+define+INSTR_CLASS_PRED=1 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+BTB_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE"
|
||||
# tc = TestCase(
|
||||
# name=name,
|
||||
# variant="rv32gc",
|
||||
# cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
# grepstr="")
|
||||
# configs.append(tc)
|
||||
|
||||
bpdSize = [2, 3, 4, 6, 10, 16]
|
||||
for CurrBPSize in bpdSize:
|
||||
name = 'RAS'+str(CurrBPSize)
|
||||
configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+BTB_SIZE=16" + "+define+RAS_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE+define+RAS_OVERRIDE"
|
||||
tc = TestCase(
|
||||
name=name,
|
||||
variant="rv32gc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
grepstr="")
|
||||
configs.append(tc)
|
||||
|
||||
# bpdSize = [6, 8, 10, 12, 14, 16]
|
||||
# LHRSize = [4, 8, 10]
|
||||
|
||||
64
sim/wave.do
64
sim/wave.do
@ -299,7 +299,15 @@ add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -label PHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -divider {class check}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory
|
||||
add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr
|
||||
add wave -noupdate -expand -group Bpred -divider {class check}
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
@ -578,31 +586,31 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
|
||||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
|
||||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
|
||||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
|
||||
add wave -noupdate -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
|
||||
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
|
||||
add wave -noupdate -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
|
||||
add wave -noupdate -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
|
||||
add wave -noupdate -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||
add wave -noupdate -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||
add wave -noupdate -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||
add wave -noupdate -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
|
||||
add wave -noupdate -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
|
||||
add wave -noupdate -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
|
||||
add wave -noupdate -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
|
||||
add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
|
||||
@ -677,7 +685,7 @@ add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/IllegalFPUInstrD
|
||||
add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/STATUS_FS
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/csrsr/STATUS_FS_INT
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {5101 ns} 0} {{Cursor 3} {152766 ns} 1}
|
||||
WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {111958 ns} 0} {{Cursor 3} {152766 ns} 1}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 194
|
||||
@ -693,4 +701,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {4326 ns} {6929 ns}
|
||||
WaveRestoreZoom {37879604 ns} {38203328 ns}
|
||||
|
||||
@ -149,6 +149,7 @@ typedef struct packed {
|
||||
int BPRED_NUM_LHR;
|
||||
int BPRED_SIZE;
|
||||
int BTB_SIZE;
|
||||
int RAS_SIZE;
|
||||
|
||||
// FPU division architecture
|
||||
int RADIX;
|
||||
|
||||
@ -27,8 +27,7 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module RASPredictor import cvw::*; #(parameter cvw_t P,
|
||||
parameter StackSize = 16 )(
|
||||
module RASPredictor import cvw::*; #(parameter cvw_t P)(
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
|
||||
@ -41,10 +40,10 @@ module RASPredictor import cvw::*; #(parameter cvw_t P,
|
||||
);
|
||||
|
||||
logic CounterEn;
|
||||
localparam Depth = $clog2(StackSize);
|
||||
localparam Depth = $clog2(P.RAS_SIZE);
|
||||
|
||||
logic [Depth-1:0] NextPtr, Ptr, P1, M1, IncDecPtr;
|
||||
logic [StackSize-1:0] [P.XLEN-1:0] memory;
|
||||
logic [P.RAS_SIZE-1:0] [P.XLEN-1:0] memory;
|
||||
integer index;
|
||||
|
||||
logic PopF;
|
||||
@ -76,14 +75,20 @@ module RASPredictor import cvw::*; #(parameter cvw_t P,
|
||||
assign P1 = 1;
|
||||
assign M1 = '1; // -1
|
||||
mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
|
||||
assign NextPtr = Ptr + IncDecPtr;
|
||||
logic [Depth-1:0] Sum;
|
||||
assign Sum = Ptr + IncDecPtr;
|
||||
if(|P.RAS_SIZE[Depth-1:0])
|
||||
assign NextPtr = Sum >= P.RAS_SIZE[Depth-1:0] ? 0 : Sum; // wrap back around if our stack is not a power of 2
|
||||
else
|
||||
assign NextPtr = Sum;
|
||||
//assign NextPtr = Ptr + IncDecPtr;
|
||||
|
||||
flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);
|
||||
|
||||
// RAS must be reset.
|
||||
always_ff @ (posedge clk) begin
|
||||
if(reset) begin
|
||||
for(index=0; index<StackSize; index++)
|
||||
for(index=0; index<P.RAS_SIZE; index++)
|
||||
memory[index] <= {P.XLEN{1'b0}};
|
||||
end else if(PushE) begin
|
||||
memory[NextPtr] <= #1 PCLinkE;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user