diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index ae37c0ccc..ec47c9576 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -93,6 +93,9 @@ module csr #(parameter logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM; logic IllegalCSRMWriteReadonlyM; + logic InstrValidNotFlushedM; + assign InstrValidNotFlushedM = ~StallW & ~FlushW; + // modify CSRs always_comb begin // Choose either rs1 or uimm[4:0] as source @@ -119,7 +122,7 @@ module csr #(parameter assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); assign CSRUWriteM = CSRWriteM; - csri csri(.clk, .reset, .FlushW, .StallW, .CSRMWriteM, .CSRSWriteM, + csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM, .CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM, .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM); csrsr csrsr(.clk, .reset, .StallW, @@ -137,7 +140,7 @@ module csr #(parameter .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, .MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM); - csrm csrm(.clk, .reset, .FlushW, .StallW, + csrm csrm(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .MTrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW, @@ -145,7 +148,7 @@ module csr #(parameter .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM); - csrs csrs(.clk, .reset, .FlushW, .StallW, + csrs csrs(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRSWriteM, .STrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, @@ -153,12 +156,12 @@ module csr #(parameter .SCOUNTEREN_REGW, .SEDELEG_REGW, .SIDELEG_REGW, .SATP_REGW, .SIP_REGW, .SIE_REGW, .WriteSSTATUSM, .IllegalCSRSAccessM); - csrn csrn(.clk, .reset, .FlushW, .StallW, + csrn csrn(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW, .CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW, .UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM); - csru csru(.clk, .reset, .FlushW, .StallW, + csru csru(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM, .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM, .IllegalCSRUAccessM); diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 7247de025..9520ffb7b 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -38,7 +38,7 @@ module csri #(parameter SIE = 12'h104, SIP = 12'h144) ( input logic clk, reset, - input logic FlushW, StallW, + input logic InstrValidNotFlushedM, StallW, input logic CSRMWriteM, CSRSWriteM, input logic [11:0] CSRAdrM, input logic ExtIntM, TimerIntM, SwIntM, @@ -52,9 +52,6 @@ module csri #(parameter logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK; logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; - logic InstrValidNotFlushedM; - assign InstrValidNotFlushedM = ~StallW & ~FlushW; - // Determine which interrupts need to be set // assumes no N-mode user interrupts diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index 35fddbee7..06c6c018a 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -70,7 +70,7 @@ module csrm #(parameter MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222} ) ( input logic clk, reset, - input logic FlushW, StallW, + input logic InstrValidNotFlushedM, StallW, input logic CSRMWriteM, MTrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, @@ -95,9 +95,6 @@ module csrm #(parameter logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; - logic InstrValidNotFlushedM; - assign InstrValidNotFlushedM = ~StallW & ~FlushW; - // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop genvar i; if (`PMP_ENTRIES > 0) begin:pmp diff --git a/pipelined/src/privileged/csrn.sv b/pipelined/src/privileged/csrn.sv index 458f15333..d524313e0 100644 --- a/pipelined/src/privileged/csrn.sv +++ b/pipelined/src/privileged/csrn.sv @@ -42,7 +42,7 @@ module csrn #(parameter UTVAL = 12'h043, UIP = 12'h044) ( input logic clk, reset, - input logic FlushW, StallW, + input logic InstrValidNotFlushedM, StallW, input logic CSRNWriteM, UTrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW, @@ -60,9 +60,6 @@ module csrn #(parameter logic WriteUCAUSEM, WriteUTVALM; logic [`XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW; logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW; - - logic InstrValidNotFlushedM; - assign InstrValidNotFlushedM = ~StallW & ~FlushW; // Write enables assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & InstrValidNotFlushedM; diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index a4c1438d3..0947facef 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -52,7 +52,7 @@ module csrs #(parameter ) ( input logic clk, reset, - input logic FlushW, StallW, + input logic InstrValidNotFlushedM, StallW, input logic CSRSWriteM, STrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, @@ -81,9 +81,6 @@ module csrs #(parameter (* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW; - logic InstrValidNotFlushedM; - assign InstrValidNotFlushedM = ~StallW & ~FlushW; - assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM; assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM; assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM; diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index 088abe85f..818b96ad4 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -37,7 +37,7 @@ module csru #(parameter FRM = 12'h002, FCSR = 12'h003) ( input logic clk, reset, - input logic FlushW, StallW, + input logic InstrValidNotFlushedM, StallW, input logic CSRUWriteM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] CSRWriteValM, @@ -54,9 +54,6 @@ module csru #(parameter logic [2:0] NextFRMM; logic [4:0] NextFFLAGSM; - logic InstrValidNotFlushedM; - assign InstrValidNotFlushedM = ~StallW & ~FlushW; - // Write enables //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & InstrValidNotFlushedM; assign WriteFRMM = (CSRUWriteM & (CSRAdrM == FRM | CSRAdrM == FCSR)) & InstrValidNotFlushedM;