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Made abhlite instation on wallypipehart more clear, updated spacing for consistency

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This commit is contained in:
Noah Limpert 2021-11-24 22:48:01 -08:00
parent 8a64510ee4
commit 0cd31bfc1f
1 changed files with 36 additions and 37 deletions
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73
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -276,50 +276,49 @@ module wallypipelinedhart (
ahblite ebu(// IFU connections ahblite ebu(// IFU connections
.InstrPAdrF(InstrPAdrF), .clk, .reset,
.InstrReadF(InstrReadF), .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
.InstrRData(InstrRData), .InstrPAdrF, // *** rename these to match block diagram
.InstrAckF(InstrAckF), .InstrReadF, .InstrRData, .InstrAckF,
// LSU connections // Signals from Data Cache
.DCtoAHBPAdrM(DCtoAHBPAdrM), // rename to DCtoAHBPAdrM .DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCtoAHBWriteData,
.DCtoAHBReadM(DCtoAHBReadM), // rename to DCtoAHBReadM .DCfromAHBReadData,
.DCtoAHBWriteM(DCtoAHBWriteM), // rename to DCtoAHBWriteM .MemSizeM(DCtoAHBSizeM[1:0]), // *** remove
.DCtoAHBWriteData(DCtoAHBWriteData), .DCfromAHBAck,
.DCfromAHBReadData(DCfromAHBReadData),
.DCfromAHBAck(DCfromAHBAck), .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
// remove these .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST,
.MemSizeM(DCtoAHBSizeM[1:0]), // *** depends on XLEN should be removed .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED,
.UnsignedLoadM(1'b0), .HWRITED);
.AtomicMaskedM(2'b00),
.*);
muldiv mdu( muldiv mdu(
.clk, .reset, .clk, .reset,
// Execute Stage interface // Execute Stage interface
// .SrcAE, .SrcBE, // .SrcAE, .SrcBE,
.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
.Funct3E, .Funct3M, .Funct3E, .Funct3M,
.MulDivE, .W64E, .MulDivE, .W64E,
// Writeback stage // Writeback stage
.MulDivResultW, .MulDivResultW,
// Divide Done // Divide Done
.DivBusyE, .DivBusyE,
// hazards // hazards
.StallM, .StallW, .FlushM, .FlushW .StallM, .StallW, .FlushM, .FlushW
); // multiply and divide unit ); // multiply and divide unit
hazard hzu( hazard hzu(
.BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM, .BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
.LoadStallD, .StoreStallD, .MulDivStallD, .CSRRdStallD, .LoadStallD, .StoreStallD, .MulDivStallD, .CSRRdStallD,
.LSUStall, .ICacheStallF, .LSUStall, .ICacheStallF,
.FPUStallD, .FStallD, .FPUStallD, .FStallD,
.DivBusyE, .FDivBusyE, .DivBusyE, .FDivBusyE,
.EcallFaultM, .BreakpointFaultM, .EcallFaultM, .BreakpointFaultM,
.InvalidateICacheM, .InvalidateICacheM,
// Stall & flush outputs // Stall & flush outputs
.StallF, .StallD, .StallE, .StallM, .StallW, .StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW); // global stall and flush control .FlushF, .FlushD, .FlushE, .FlushM, .FlushW
); // global stall and flush control
// Priveleged block operates in M and W stages, handling CSRs and exceptions // Priveleged block operates in M and W stages, handling CSRs and exceptions
privileged priv(.*); privileged priv(.*);