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initial seed of AES engine

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James E. Stine 2024-02-20 18:31:17 -06:00
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src/ieu/aes_common/aes_inv_mixcolumns.sv Normal file
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///////////////////////////////////////////
// aes_inv_mixcolumns.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V AES Mix Columns
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module inv_mixword (input logic [31:0] word, output logic [31:0] mixed_word);
// Instantiate Internal Logic
logic [7:0] b0, b1, b2, b3;
logic [7:0] mb0, mb1, mb2, mb3;
logic [7:0] gm9_mb0, gm11_mb0, gm13_mb0, gm14_mb0;
logic [7:0] gm9_mb1, gm11_mb1, gm13_mb1, gm14_mb1;
logic [7:0] gm9_mb2, gm11_mb2, gm13_mb2, gm14_mb2;
logic [7:0] gm9_mb3, gm11_mb3, gm13_mb3, gm14_mb3;
// Break up word into 1 byte slices
assign b0 = word[31:24];
assign b1 = word[23:16];
assign b2 = word[15:8];
assign b3 = word[7:0];
// mb0 Galois components
gm9 gm9_0(.gm9_in(b1), .gm9_out(gm9_mb0));
gm11 gm11_0(.gm11_in(b3), .gm11_out(gm11_mb0));
gm13 gm13_0(.gm13_in(b2), .gm13_out(gm13_mb0));
gm14 gm14_0(.gm14_in(b0), .gm14_out(gm14_mb0));
// mb1 Galois components
gm9 gm9_1(.gm9_in(b2), .gm9_out(gm9_mb1));
gm11 gm11_1(.gm11_in(b0), .gm11_out(gm11_mb1));
gm13 gm13_1(.gm13_in(b3), .gm13_out(gm13_mb1));
gm14 gm14_1(.gm14_in(b1), .gm14_out(gm14_mb1));
// mb2 Galois components
gm9 gm9_2(.gm9_in(b3), .gm9_out(gm9_mb2));
gm11 gm11_2(.gm11_in(b1), .gm11_out(gm11_mb2));
gm13 gm13_2(.gm13_in(b0), .gm13_out(gm13_mb2));
gm14 gm14_2(.gm14_in(b2), .gm14_out(gm14_mb2));
// mb3 Galois components
gm9 gm9_3(.gm9_in(b0), .gm9_out(gm9_mb3));
gm11 gm11_3(.gm11_in(b2), .gm11_out(gm11_mb3));
gm13 gm13_3(.gm13_in(b1), .gm13_out(gm13_mb3));
gm14 gm14_3(.gm14_in(b3), .gm14_out(gm14_mb3));
// XOR Galois components and assign output
assign mb0 = gm9_mb0 ^ gm11_mb0 ^ gm13_mb0 ^ gm14_mb0;
assign mb1 = gm9_mb1 ^ gm11_mb1 ^ gm13_mb1 ^ gm14_mb1;
assign mb2 = gm9_mb2 ^ gm11_mb2 ^ gm13_mb2 ^ gm14_mb2;
assign mb3 = gm9_mb3 ^ gm11_mb3 ^ gm13_mb3 ^ gm14_mb3;
assign mixed_word = {mb0, mb1, mb2, mb3};
endmodule // inv_mixword
module aes_inv_mixcols (input logic [127:0] data, output logic [127:0] mixed_col);
// Declare Internal logic
logic [31:0] w0, w1, w2, w3;
logic [31:0] ws0, ws1, ws2, ws3;
// Break up input data into word components
assign w0 = data[127:96];
assign w1 = data[95:64];
assign w2 = data[63:32];
assign w3 = data[31:0];
// Declare mixword components
inv_mixword mw_0(.word(w0), .mixed_word(ws0));
inv_mixword mw_1(.word(w1), .mixed_word(ws1));
inv_mixword mw_2(.word(w2), .mixed_word(ws2));
inv_mixword mw_3(.word(w3), .mixed_word(ws3));
// Assign output to mixed word
assign mixed_col = {ws0, ws1, ws2, ws3};
endmodule // inv_mixcols

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///////////////////////////////////////////
// aes_inv_sbox.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V Rinjdael Inverted S-BOX
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_inv_sbox(input logic [7:0] in,
output logic [7:0] out);
always_comb
begin
case(in)
8'h00 : out = 8'h52;
8'h01 : out = 8'h09;
8'h02 : out = 8'h6A;
8'h03 : out = 8'hD5;
8'h04 : out = 8'h30;
8'h05 : out = 8'h36;
8'h06 : out = 8'hA5;
8'h07 : out = 8'h38;
8'h08 : out = 8'hBF;
8'h09 : out = 8'h40;
8'h0A : out = 8'hA3;
8'h0B : out = 8'h9E;
8'h0C : out = 8'h81;
8'h0D : out = 8'hF3;
8'h0E : out = 8'hD7;
8'h0F : out = 8'hFB;
8'h10 : out = 8'h7C;
8'h11 : out = 8'hE3;
8'h12 : out = 8'h39;
8'h13 : out = 8'h82;
8'h14 : out = 8'h9B;
8'h15 : out = 8'h2F;
8'h16 : out = 8'hFF;
8'h17 : out = 8'h87;
8'h18 : out = 8'h34;
8'h19 : out = 8'h8E;
8'h1A : out = 8'h43;
8'h1B : out = 8'h44;
8'h1C : out = 8'hC4;
8'h1D : out = 8'hDE;
8'h1E : out = 8'hE9;
8'h1F : out = 8'hCB;
8'h20 : out = 8'h54;
8'h21 : out = 8'h7B;
8'h22 : out = 8'h94;
8'h23 : out = 8'h32;
8'h24 : out = 8'hA6;
8'h25 : out = 8'hC2;
8'h26 : out = 8'h23;
8'h27 : out = 8'h3D;
8'h28 : out = 8'hEE;
8'h29 : out = 8'h4C;
8'h2A : out = 8'h95;
8'h2B : out = 8'h0B;
8'h2C : out = 8'h42;
8'h2D : out = 8'hFA;
8'h2E : out = 8'hC3;
8'h2F : out = 8'h4E;
8'h30 : out = 8'h08;
8'h31 : out = 8'h2E;
8'h32 : out = 8'hA1;
8'h33 : out = 8'h66;
8'h34 : out = 8'h28;
8'h35 : out = 8'hD9;
8'h36 : out = 8'h24;
8'h37 : out = 8'hB2;
8'h38 : out = 8'h76;
8'h39 : out = 8'h5B;
8'h3A : out = 8'hA2;
8'h3B : out = 8'h49;
8'h3C : out = 8'h6D;
8'h3D : out = 8'h8B;
8'h3E : out = 8'hD1;
8'h3F : out = 8'h25;
8'h40 : out = 8'h72;
8'h41 : out = 8'hF8;
8'h42 : out = 8'hF6;
8'h43 : out = 8'h64;
8'h44 : out = 8'h86;
8'h45 : out = 8'h68;
8'h46 : out = 8'h98;
8'h47 : out = 8'h16;
8'h48 : out = 8'hD4;
8'h49 : out = 8'hA4;
8'h4A : out = 8'h5C;
8'h4B : out = 8'hCC;
8'h4C : out = 8'h5D;
8'h4D : out = 8'h65;
8'h4E : out = 8'hB6;
8'h4F : out = 8'h92;
8'h50 : out = 8'h6C;
8'h51 : out = 8'h70;
8'h52 : out = 8'h48;
8'h53 : out = 8'h50;
8'h54 : out = 8'hFD;
8'h55 : out = 8'hED;
8'h56 : out = 8'hB9;
8'h57 : out = 8'hDA;
8'h58 : out = 8'h5E;
8'h59 : out = 8'h15;
8'h5A : out = 8'h46;
8'h5B : out = 8'h57;
8'h5C : out = 8'hA7;
8'h5D : out = 8'h8D;
8'h5E : out = 8'h9D;
8'h5F : out = 8'h84;
8'h60 : out = 8'h90;
8'h61 : out = 8'hD8;
8'h62 : out = 8'hAB;
8'h63 : out = 8'h00;
8'h64 : out = 8'h8C;
8'h65 : out = 8'hBC;
8'h66 : out = 8'hD3;
8'h67 : out = 8'h0A;
8'h68 : out = 8'hF7;
8'h69 : out = 8'hE4;
8'h6A : out = 8'h58;
8'h6B : out = 8'h05;
8'h6C : out = 8'hB8;
8'h6D : out = 8'hB3;
8'h6E : out = 8'h45;
8'h6F : out = 8'h06;
8'h70 : out = 8'hD0;
8'h71 : out = 8'h2C;
8'h72 : out = 8'h1E;
8'h73 : out = 8'h8F;
8'h74 : out = 8'hCA;
8'h75 : out = 8'h3F;
8'h76 : out = 8'h0F;
8'h77 : out = 8'h02;
8'h78 : out = 8'hC1;
8'h79 : out = 8'hAF;
8'h7A : out = 8'hBD;
8'h7B : out = 8'h03;
8'h7C : out = 8'h01;
8'h7D : out = 8'h13;
8'h7E : out = 8'h8A;
8'h7F : out = 8'h6B;
8'h80 : out = 8'h3A;
8'h81 : out = 8'h91;
8'h82 : out = 8'h11;
8'h83 : out = 8'h41;
8'h84 : out = 8'h4F;
8'h85 : out = 8'h67;
8'h86 : out = 8'hDC;
8'h87 : out = 8'hEA;
8'h88 : out = 8'h97;
8'h89 : out = 8'hF2;
8'h8A : out = 8'hCF;
8'h8B : out = 8'hCE;
8'h8C : out = 8'hF0;
8'h8D : out = 8'hB4;
8'h8E : out = 8'hE6;
8'h8F : out = 8'h73;
8'h90 : out = 8'h96;
8'h91 : out = 8'hAC;
8'h92 : out = 8'h74;
8'h93 : out = 8'h22;
8'h94 : out = 8'hE7;
8'h95 : out = 8'hAD;
8'h96 : out = 8'h35;
8'h97 : out = 8'h85;
8'h98 : out = 8'hE2;
8'h99 : out = 8'hF9;
8'h9A : out = 8'h37;
8'h9B : out = 8'hE8;
8'h9C : out = 8'h1C;
8'h9D : out = 8'h75;
8'h9E : out = 8'hDF;
8'h9F : out = 8'h6E;
8'hA0 : out = 8'h47;
8'hA1 : out = 8'hF1;
8'hA2 : out = 8'h1A;
8'hA3 : out = 8'h71;
8'hA4 : out = 8'h1D;
8'hA5 : out = 8'h29;
8'hA6 : out = 8'hC5;
8'hA7 : out = 8'h89;
8'hA8 : out = 8'h6F;
8'hA9 : out = 8'hB7;
8'hAA : out = 8'h62;
8'hAB : out = 8'h0E;
8'hAC : out = 8'hAA;
8'hAD : out = 8'h18;
8'hAE : out = 8'hBE;
8'hAF : out = 8'h1B;
8'hB0 : out = 8'hFC;
8'hB1 : out = 8'h56;
8'hB2 : out = 8'h3E;
8'hB3 : out = 8'h4B;
8'hB4 : out = 8'hC6;
8'hB5 : out = 8'hD2;
8'hB6 : out = 8'h79;
8'hB7 : out = 8'h20;
8'hB8 : out = 8'h9A;
8'hB9 : out = 8'hDB;
8'hBA : out = 8'hC0;
8'hBB : out = 8'hFE;
8'hBC : out = 8'h78;
8'hBD : out = 8'hCD;
8'hBE : out = 8'h5A;
8'hBF : out = 8'hF4;
8'hC0 : out = 8'h1F;
8'hC1 : out = 8'hDD;
8'hC2 : out = 8'hA8;
8'hC3 : out = 8'h33;
8'hC4 : out = 8'h88;
8'hC5 : out = 8'h07;
8'hC6 : out = 8'hC7;
8'hC7 : out = 8'h31;
8'hC8 : out = 8'hB1;
8'hC9 : out = 8'h12;
8'hCA : out = 8'h10;
8'hCB : out = 8'h59;
8'hCC : out = 8'h27;
8'hCD : out = 8'h80;
8'hCE : out = 8'hEC;
8'hCF : out = 8'h5F;
8'hD0 : out = 8'h60;
8'hD1 : out = 8'h51;
8'hD2 : out = 8'h7F;
8'hD3 : out = 8'hA9;
8'hD4 : out = 8'h19;
8'hD5 : out = 8'hB5;
8'hD6 : out = 8'h4A;
8'hD7 : out = 8'h0D;
8'hD8 : out = 8'h2D;
8'hD9 : out = 8'hE5;
8'hDA : out = 8'h7A;
8'hDB : out = 8'h9F;
8'hDC : out = 8'h93;
8'hDD : out = 8'hC9;
8'hDE : out = 8'h9C;
8'hDF : out = 8'hEF;
8'hE0 : out = 8'hA0;
8'hE1 : out = 8'hE0;
8'hE2 : out = 8'h3B;
8'hE3 : out = 8'h4D;
8'hE4 : out = 8'hAE;
8'hE5 : out = 8'h2A;
8'hE6 : out = 8'hF5;
8'hE7 : out = 8'hB0;
8'hE8 : out = 8'hC8;
8'hE9 : out = 8'hEB;
8'hEA : out = 8'hBB;
8'hEB : out = 8'h3C;
8'hEC : out = 8'h83;
8'hED : out = 8'h53;
8'hEE : out = 8'h99;
8'hEF : out = 8'h61;
8'hF0 : out = 8'h17;
8'hF1 : out = 8'h2B;
8'hF2 : out = 8'h04;
8'hF3 : out = 8'h7E;
8'hF4 : out = 8'hBA;
8'hF5 : out = 8'h77;
8'hF6 : out = 8'hD6;
8'hF7 : out = 8'h26;
8'hF8 : out = 8'hE1;
8'hF9 : out = 8'h69;
8'hFA : out = 8'h14;
8'hFB : out = 8'h63;
8'hFC : out = 8'h55;
8'hFD : out = 8'h21;
8'hFE : out = 8'h0C;
8'hFF : out = 8'h7D;
endcase
end
endmodule

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///////////////////////////////////////////
// aes_inv_sbox_128.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V 128-bit Inverse Substitution box
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_inv_sbox_128(input logic [127:0] in,
output logic [127:0] out);
//Declare the SBOX for (least significant) word 0 of the input
aes_inv_sbox_word sbox_w0(.in(in[31:0]), .out(out[31:0]));
//Declare the SBOX for word 1 of the input
aes_inv_sbox_word sbox_w1(.in(in[63:32]), .out(out[63:32]));
//Declare the SBOX for word 2 of the input
aes_inv_sbox_word sbox_w2(.in(in[95:64]), .out(out[95:64]));
//Declare the SBOX for word 3 of the input
aes_inv_sbox_word sbox_w3(.in(in[127:96]), .out(out[127:96]));
endmodule

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///////////////////////////////////////////
// aes_inv_sbox.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V Rinjdael Inverted S-BOX
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_inv_sbox_word(input logic [31:0] in,
output logic [31:0] out);
//Declare the SBOX for (least significant) byte 0 of the input
aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
//Declare the SBOX for byte 1 of the input
aes_inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8]));
//Declare the SBOX for byte 2 of the input
aes_inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16]));
//Declare the SBOX for byte 3 of the input
aes_inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24]));
endmodule

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///////////////////////////////////////////
// aes_inv_shiftrow.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V AES Shiftrow
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_inv_shiftrow(input logic [127:0] dataIn,
output logic [127:0] dataOut);
//Seperate the first (Least Significant) word into bytes
logic [7:0] w0_b0 = dataIn[7:0];
logic [7:0] w0_b1 = dataIn[15:8];
logic [7:0] w0_b2 = dataIn[23:16];
logic [7:0] w0_b3 = dataIn[31:24];
//Seperate the second word into bytes
logic [7:0] w1_b0 = dataIn[39:32];
logic [7:0] w1_b1 = dataIn[47:40];
logic [7:0] w1_b2 = dataIn[55:48];
logic [7:0] w1_b3 = dataIn[63:56];
//Seperate the third word into bytes
logic [7:0] w2_b0 = dataIn[71:64];
logic [7:0] w2_b1 = dataIn[79:72];
logic [7:0] w2_b2 = dataIn[87:80];
logic [7:0] w2_b3 = dataIn[95:88];
//Seperate the fourth (Most significant) word into bytes
logic [7:0] w3_b0 = dataIn[103:96];
logic [7:0] w3_b1 = dataIn[111:104];
logic [7:0] w3_b2 = dataIn[119:112];
logic [7:0] w3_b3 = dataIn[127:120];
//The output words are composed of sets of the input bytes.
logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};
assign dataOut = {out_w0, out_w1, out_w2, out_w3};
endmodule
/*
Purpose : This next module provides an alternative way to shift the values.
in which it takes the shift number (essentially row number) as
an input and shifts cyclically to the left by that number of bits.
the complexity here is removed from the module and is more complex in
input selection.
*/
module aes_shiftword(input logic[1:0] shiftAmt,
input logic [31:0] dataIn,
output logic [31:0] dataOut);
logic [7:0] b0 = dataIn[7:0];
logic [7:0] b1 = dataIn[15:8];
logic [7:0] b2 = dataIn[23:16];
logic [7:0] b3 = dataIn[31:24];
always_comb
begin
case(shiftAmt)
//00 : Barrel Shift no bytes
2'b00 : dataOut = {b3, b2, b1, b0};
//01 : Barrel Shift one byte
2'b01 : dataOut = {b0, b3, b2, b1};
//10 : Barrel Shift two bytes
2'b10 : dataOut = {b1, b0, b3, b2};
//11 : Barrel Shift three bytes
default : dataOut = {b2, b1, b0, b3};
endcase
end // always_comb
endmodule

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///////////////////////////////////////////
// aes_mixcolumns.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V "Mix Columns"
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
/*
* Purpose : The "mix columns" operation is essentially composed of a
* nice little Galois field multiplication (of 1, 2 or 3) in the field
* x^8 + x^4 + x^3 + x + 1.
* The actual matrix you multiply by is
* [2 3 1 1][a_0,j]
* [1 2 3 1][a_1,j]
* [1 1 2 3][a_2,j]
* [3 1 1 2][a_3,j]
*
* Reference: secworks repo
*/
module aes_mixcolumns(data, mixedcols);
// Declare Inputs/Outputs
input logic [127:0] data;
output logic [127:0] mixedcols;
// Declare internal Logic
logic [31:0] w0, w1, w2, w3;
logic [31:0] ws0, ws1, ws2, ws3;
// Break up data into individual words
assign w0 = data[127:96];
assign w1 = data[95:64];
assign w2 = data[63:32];
assign w3 = data[31:0];
// Instantiate The mix words components for the words
mixword mw0(.word(w0), .mixed_word(ws0));
mixword mw1(.word(w1), .mixed_word(ws1));
mixword mw2(.word(w2), .mixed_word(ws2));
mixword mw3(.word(w3), .mixed_word(ws3));
// Assign Output
assign mixedcols = {ws0, ws1, ws2, ws3};
endmodule // mixcolumns
//This applies the Galois field operations to an individual 32 bit word.
module mixword (word, mixed_word);
// Declare Inputs/Outputs
input logic [31:0] word;
output logic [31:0] mixed_word;
// Declare Internal Signals
logic [7:0] b0, b1, b2, b3;
logic [7:0] mb0, mb1, mb2, mb3;
logic [7:0] gm2_0_out;
logic [7:0] gm3_0_out;
logic [7:0] gm2_1_out;
logic [7:0] gm3_1_out;
logic [7:0] gm2_2_out;
logic [7:0] gm3_2_out;
logic [7:0] gm2_3_out;
logic [7:0] gm3_3_out;
// Break word into bytes
assign b0 = word[31:24];
assign b1 = word[23:16];
assign b2 = word[15:8];
assign b3 = word[7:0];
// mb0 Galois components
gm2 gm2_0(.gm2_in(b0),
.gm2_out(gm2_0_out));
gm3 gm3_0(.gm3_in(b3),
.gm3_out(gm3_0_out));
// mb1 Galois components
gm2 gm2_1(.gm2_in(b1),
.gm2_out(gm2_1_out));
gm3 gm3_1(.gm3_in(b0),
.gm3_out(gm3_1_out));
// mb2 Galois components
gm2 gm2_2(.gm2_in(b2),
.gm2_out(gm2_2_out));
gm3 gm3_2(.gm3_in(b1),
.gm3_out(gm3_2_out));
// mb3 Galois components
gm2 gm2_3(.gm2_in(b3),
.gm2_out(gm2_3_out));
gm3 gm3_3(.gm3_in(b2),
.gm3_out(gm3_3_out));
// Combine Componenets into mixed word
assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2;
assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3;
assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3;
assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1;
assign mixed_word = {mb0, mb1, mb2, mb3};
endmodule

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///////////////////////////////////////////
// aes_mixcolumns.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V Rinjdael forward S-BOX in the form of a LUT
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_sbox(input logic [7:0] in,
output logic [7:0] out);
// case statement to lookup the value in the rijndael table
always_comb
begin
case(in)
8'h00 : out = 8'h63;
8'h01 : out = 8'h7C;
8'h02 : out = 8'h77;
8'h03 : out = 8'h7B;
8'h04 : out = 8'hF2;
8'h05 : out = 8'h6B;
8'h06 : out = 8'h6F;
8'h07 : out = 8'hC5;
8'h08 : out = 8'h30;
8'h09 : out = 8'h01;
8'h0A : out = 8'h67;
8'h0B : out = 8'h2B;
8'h0C : out = 8'hFE;
8'h0D : out = 8'hD7;
8'h0E : out = 8'hAB;
8'h0F : out = 8'h76;
8'h10 : out = 8'hCA;
8'h11 : out = 8'h82;
8'h12 : out = 8'hC9;
8'h13 : out = 8'h7D;
8'h14 : out = 8'hFA;
8'h15 : out = 8'h59;
8'h16 : out = 8'h47;
8'h17 : out = 8'hF0;
8'h18 : out = 8'hAD;
8'h19 : out = 8'hD4;
8'h1A : out = 8'hA2;
8'h1B : out = 8'hAF;
8'h1C : out = 8'h9C;
8'h1D : out = 8'hA4;
8'h1E : out = 8'h72;
8'h1F : out = 8'hC0;
8'h20 : out = 8'hB7;
8'h21 : out = 8'hFD;
8'h22 : out = 8'h93;
8'h23 : out = 8'h26;
8'h24 : out = 8'h36;
8'h25 : out = 8'h3F;
8'h26 : out = 8'hF7;
8'h27 : out = 8'hCC;
8'h28 : out = 8'h34;
8'h29 : out = 8'hA5;
8'h2A : out = 8'hE5;
8'h2B : out = 8'hF1;
8'h2C : out = 8'h71;
8'h2D : out = 8'hD8;
8'h2E : out = 8'h31;
8'h2F : out = 8'h15;
8'h30 : out = 8'h04;
8'h31 : out = 8'hC7;
8'h32 : out = 8'h23;
8'h33 : out = 8'hC3;
8'h34 : out = 8'h18;
8'h35 : out = 8'h96;
8'h36 : out = 8'h05;
8'h37 : out = 8'h9A;
8'h38 : out = 8'h07;
8'h39 : out = 8'h12;
8'h3A : out = 8'h80;
8'h3B : out = 8'hE2;
8'h3C : out = 8'hEB;
8'h3D : out = 8'h27;
8'h3E : out = 8'hB2;
8'h3F : out = 8'h75;
8'h40 : out = 8'h09;
8'h41 : out = 8'h83;
8'h42 : out = 8'h2C;
8'h43 : out = 8'h1A;
8'h44 : out = 8'h1B;
8'h45 : out = 8'h6E;
8'h46 : out = 8'h5A;
8'h47 : out = 8'hA0;
8'h48 : out = 8'h52;
8'h49 : out = 8'h3B;
8'h4A : out = 8'hD6;
8'h4B : out = 8'hB3;
8'h4C : out = 8'h29;
8'h4D : out = 8'hE3;
8'h4E : out = 8'h2F;
8'h4F : out = 8'h84;
8'h50 : out = 8'h53;
8'h51 : out = 8'hD1;
8'h52 : out = 8'h00;
8'h53 : out = 8'hED;
8'h54 : out = 8'h20;
8'h55 : out = 8'hFC;
8'h56 : out = 8'hB1;
8'h57 : out = 8'h5B;
8'h58 : out = 8'h6A;
8'h59 : out = 8'hCB;
8'h5A : out = 8'hBE;
8'h5B : out = 8'h39;
8'h5C : out = 8'h4A;
8'h5D : out = 8'h4C;
8'h5E : out = 8'h58;
8'h5F : out = 8'hCF;
8'h60 : out = 8'hD0;
8'h61 : out = 8'hEF;
8'h62 : out = 8'hAA;
8'h63 : out = 8'hFB;
8'h64 : out = 8'h43;
8'h65 : out = 8'h4D;
8'h66 : out = 8'h33;
8'h67 : out = 8'h85;
8'h68 : out = 8'h45;
8'h69 : out = 8'hF9;
8'h6A : out = 8'h02;
8'h6B : out = 8'h7F;
8'h6C : out = 8'h50;
8'h6D : out = 8'h3C;
8'h6E : out = 8'h9F;
8'h6F : out = 8'hA8;
8'h70 : out = 8'h51;
8'h71 : out = 8'hA3;
8'h72 : out = 8'h40;
8'h73 : out = 8'h8F;
8'h74 : out = 8'h92;
8'h75 : out = 8'h9D;
8'h76 : out = 8'h38;
8'h77 : out = 8'hF5;
8'h78 : out = 8'hBC;
8'h79 : out = 8'hB6;
8'h7A : out = 8'hDA;
8'h7B : out = 8'h21;
8'h7C : out = 8'h10;
8'h7D : out = 8'hFF;
8'h7E : out = 8'hF3;
8'h7F : out = 8'hD2;
8'h80 : out = 8'hCD;
8'h81 : out = 8'h0C;
8'h82 : out = 8'h13;
8'h83 : out = 8'hEC;
8'h84 : out = 8'h5F;
8'h85 : out = 8'h97;
8'h86 : out = 8'h44;
8'h87 : out = 8'h17;
8'h88 : out = 8'hC4;
8'h89 : out = 8'hA7;
8'h8A : out = 8'h7E;
8'h8B : out = 8'h3D;
8'h8C : out = 8'h64;
8'h8D : out = 8'h5D;
8'h8E : out = 8'h19;
8'h8F : out = 8'h73;
8'h90 : out = 8'h60;
8'h91 : out = 8'h81;
8'h92 : out = 8'h4F;
8'h93 : out = 8'hDC;
8'h94 : out = 8'h22;
8'h95 : out = 8'h2A;
8'h96 : out = 8'h90;
8'h97 : out = 8'h88;
8'h98 : out = 8'h46;
8'h99 : out = 8'hEE;
8'h9A : out = 8'hB8;
8'h9B : out = 8'h14;
8'h9C : out = 8'hDE;
8'h9D : out = 8'h5E;
8'h9E : out = 8'h0B;
8'h9F : out = 8'hDB;
8'hA0 : out = 8'hE0;
8'hA1 : out = 8'h32;
8'hA2 : out = 8'h3A;
8'hA3 : out = 8'h0A;
8'hA4 : out = 8'h49;
8'hA5 : out = 8'h06;
8'hA6 : out = 8'h24;
8'hA7 : out = 8'h5C;
8'hA8 : out = 8'hC2;
8'hA9 : out = 8'hD3;
8'hAA : out = 8'hAC;
8'hAB : out = 8'h62;
8'hAC : out = 8'h91;
8'hAD : out = 8'h95;
8'hAE : out = 8'hE4;
8'hAF : out = 8'h79;
8'hB0 : out = 8'hE7;
8'hB1 : out = 8'hC8;
8'hB2 : out = 8'h37;
8'hB3 : out = 8'h6D;
8'hB4 : out = 8'h8D;
8'hB5 : out = 8'hD5;
8'hB6 : out = 8'h4E;
8'hB7 : out = 8'hA9;
8'hB8 : out = 8'h6C;
8'hB9 : out = 8'h56;
8'hBA : out = 8'hF4;
8'hBB : out = 8'hEA;
8'hBC : out = 8'h65;
8'hBD : out = 8'h7A;
8'hBE : out = 8'hAE;
8'hBF : out = 8'h08;
8'hC0 : out = 8'hBA;
8'hC1 : out = 8'h78;
8'hC2 : out = 8'h25;
8'hC3 : out = 8'h2E;
8'hC4 : out = 8'h1C;
8'hC5 : out = 8'hA6;
8'hC6 : out = 8'hB4;
8'hC7 : out = 8'hC6;
8'hC8 : out = 8'hE8;
8'hC9 : out = 8'hDD;
8'hCA : out = 8'h74;
8'hCB : out = 8'h1F;
8'hCC : out = 8'h4B;
8'hCD : out = 8'hBD;
8'hCE : out = 8'h8B;
8'hCF : out = 8'h8A;
8'hD0 : out = 8'h70;
8'hD1 : out = 8'h3E;
8'hD2 : out = 8'hB5;
8'hD3 : out = 8'h66;
8'hD4 : out = 8'h48;
8'hD5 : out = 8'h03;
8'hD6 : out = 8'hF6;
8'hD7 : out = 8'h0E;
8'hD8 : out = 8'h61;
8'hD9 : out = 8'h35;
8'hDA : out = 8'h57;
8'hDB : out = 8'hB9;
8'hDC : out = 8'h86;
8'hDD : out = 8'hC1;
8'hDE : out = 8'h1D;
8'hDF : out = 8'h9E;
8'hE0 : out = 8'hE1;
8'hE1 : out = 8'hF8;
8'hE2 : out = 8'h98;
8'hE3 : out = 8'h11;
8'hE4 : out = 8'h69;
8'hE5 : out = 8'hD9;
8'hE6 : out = 8'h8E;
8'hE7 : out = 8'h94;
8'hE8 : out = 8'h9B;
8'hE9 : out = 8'h1E;
8'hEA : out = 8'h87;
8'hEB : out = 8'hE9;
8'hEC : out = 8'hCE;
8'hED : out = 8'h55;
8'hEE : out = 8'h28;
8'hEF : out = 8'hDF;
8'hF0 : out = 8'h8C;
8'hF1 : out = 8'hA1;
8'hF2 : out = 8'h89;
8'hF3 : out = 8'h0D;
8'hF4 : out = 8'hBF;
8'hF5 : out = 8'hE6;
8'hF6 : out = 8'h42;
8'hF7 : out = 8'h68;
8'hF8 : out = 8'h41;
8'hF9 : out = 8'h99;
8'hFA : out = 8'h2D;
8'hFB : out = 8'h0F;
8'hFC : out = 8'hB0;
8'hFD : out = 8'h54;
8'hFE : out = 8'hBB;
8'hFF : out = 8'h16;
endcase
end
endmodule

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///////////////////////////////////////////
// aes_sbox_word.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V 4 sets of Rijndael S-BOX so whole word can be looked up simultaneously.
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_sbox_word(input logic [31:0] in,
output logic [31:0] out);
// Declare the SBOX for (least significant) byte 0 of the input
aes_sbox sbox_b0(.in(in[7:0]),
.out(out[7:0]));
// Declare the SBOX for byte 1 of the input
aes_sbox sbox_b1(.in(in[15:8]),
.out(out[15:8]));
// Declare the SBOX for byte 2 of the input
aes_sbox sbox_b2(.in(in[23:16]),
.out(out[23:16]));
// Declare the SBOX for byte 3 of the input
aes_sbox sbox_b3(.in(in[31:24]),
.out(out[31:24]));
endmodule

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///////////////////////////////////////////
// aes_shiftrow.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V aes_shiftrow for taking in first data line
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_shiftrow(input logic [127:0] dataIn,
output logic [127:0] dataOut);
// (This form of writing it may seem like more effort but I feel
// like it is more self-explanatory this way without losing efficiency)
//Seperate the first (Least Significant) word into bytes
logic [7:0] w0_b0 = dataIn[7:0];
logic [7:0] w0_b1 = dataIn[79:72];
logic [7:0] w0_b2 = dataIn[23:16];
logic [7:0] w0_b3 = dataIn[95:88];
//Seperate the second word into bytes
logic [7:0] w1_b0 = dataIn[39:32];
logic [7:0] w1_b1 = dataIn[111:104];
logic [7:0] w1_b2 = dataIn[55:48];
logic [7:0] w1_b3 = dataIn[127:120];
//Seperate the third word into bytes
logic [7:0] w2_b0 = dataIn[71:64];
logic [7:0] w2_b1 = dataIn[15:8];
logic [7:0] w2_b2 = dataIn[87:80];
logic [7:0] w2_b3 = dataIn[31:24];
//Seperate the fourth (Most significant) word into bytes
logic [7:0] w3_b0 = dataIn[103:96];
logic [7:0] w3_b1 = dataIn[47:40];
logic [7:0] w3_b2 = dataIn[119:112];
logic [7:0] w3_b3 = dataIn[63:56];
//The output words are composed of sets of the input bytes.
logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};
assign dataOut = {out_w0, out_w1, out_w2, out_w3};
endmodule
/*
* Purpose : This next module provides an alternative way to shift the values.
in which it takes the shift number (essentially row number) as
an input and shifts cyclically to the left by that number of bits.
the complexity here is removed from the module and is more complex in
input selection (eww more thinking bad return to monkeh)
*/
module aes_shiftwordbrutherr(input logic[1:0] shiftAmt,
input logic [31:0] dataIn,
output logic [31:0] dataOut);
logic [7:0] b0 = dataIn[7:0];
logic [7:0] b1 = dataIn[15:8];
logic [7:0] b2 = dataIn[23:16];
logic [7:0] b3 = dataIn[31:24];
always_comb
begin
case(shiftAmt)
//00 : Barrel Shift no bytes
2'b00 : dataOut = {b3, b2, b1, b0};
//01 : Barrel Shift one byte
2'b01 : dataOut = {b2, b1, b0, b3};
//10 : Barrel Shift two bytes
2'b10 : dataOut = {b1, b0, b2, b3};
//11 : Barrel Shift three bytes
default : dataOut = {b0, b1, b2, b3};
endcase
end
endmodule

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///////////////////////////////////////////
// galois_func.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V Galois field operations for mix columns operation
//
// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module gm2 (gm2_in, gm2_out);
input logic [7:0] gm2_in;
output logic [7:0] gm2_out;
// Set output to Galois Mult 2
assign gm2_out = {gm2_in[6:0], 1'b0} ^ (8'h1b & {8{gm2_in[7]}});
endmodule // gm2
module gm3 (gm3_in, gm3_out);
input logic [7:0] gm3_in;
output logic [7:0] gm3_out;
// Internal Logic
logic [7:0] gm2_0_out;
// Sub-Modules for gm2 multiplication
gm2 gm2_0 (.gm2_in(gm3_in), .gm2_out(gm2_0_out));
// Assign Output
assign gm3_out = gm2_0_out ^ gm3_in;
endmodule
module gm4 (gm4_in, gm4_out);
input logic [7:0] gm4_in;
output logic [7:0] gm4_out;
// Internal Logic
logic [7:0] gm2_0_out;
logic [7:0] gm2_1_out;
// Sub-Modules for multiple gm2 multiplications
gm2 gm2_0 (.gm2_in(gm4_in),
.gm2_out(gm2_0_out));
gm2 gm2_1 (.gm2_in(gm2_0_out),
.gm2_out(gm2_1_out));
// Assign output to second gm2 output
assign gm4_out = gm2_1_out;
endmodule
module gm8 (gm8_in, gm8_out);
input logic [7:0] gm8_in;
output logic [7:0] gm8_out;
// Internal Logic
logic [7:0] gm2_0_out;
logic [7:0] gm4_0_out;
// Sub-Modules for sub-galois operations
gm4 gm4_0 (.gm4_in(gm8_in),
.gm4_out(gm4_0_out));
gm2 gm2_0 (.gm2_in(gm4_0_out),
.gm2_out(gm2_0_out));
// Assign output to gm2 output
assign gm8_out = gm2_0_out;
endmodule // gm8
module gm9 (gm9_in, gm9_out);
input logic [7:0] gm9_in;
output logic [7:0] gm9_out;
// Internal Logic
logic [7:0] gm8_0_out;
// Sub-Modules for sub-galois operations
gm8 gm8_0 (.gm8_in(gm9_in), .gm8_out(gm8_0_out));
// Set output to gm8(in) ^ in
assign gm9_out = gm8_0_out ^ gm9_in;
endmodule
module gm11 (gm11_in, gm11_out);
input logic [7:0] gm11_in;
output logic [7:0] gm11_out;
// Internal Logic
logic [7:0] gm8_0_out;
logic [7:0] gm2_0_out;
// Sub-Modules for sub-galois operations
gm8 gm8_0 (.gm8_in(gm11_in), .gm8_out(gm8_0_out));
gm2 gm2_0 (.gm2_in(gm11_in), .gm2_out(gm2_0_out));
// Set output to gm8(in) ^ gm2(in) ^ in
assign gm11_out = gm8_0_out ^ gm2_0_out ^ gm11_in;
endmodule // gm11
module gm13 (gm13_in, gm13_out);
input logic [7:0] gm13_in;
output logic [7:0] gm13_out;
// Internal Logic
logic [7:0] gm8_0_out;
logic [7:0] gm4_0_out;
// Sub-Modules for sub-galois operations
gm8 gm8_0 (.gm8_in(gm13_in), .gm8_out(gm8_0_out));
gm4 gm4_0 (.gm4_in(gm13_in), .gm4_out(gm4_0_out));
// Set output to gm8(in) ^ gm4(in) ^ in
assign gm13_out = gm8_0_out ^ gm4_0_out ^ gm13_in;
endmodule // gm13
module gm14 (gm14_in, gm14_out);
input logic [7:0] gm14_in;
output logic [7:0] gm14_out;
// Internal Logic
logic [7:0] gm8_0_out;
logic [7:0] gm4_0_out;
logic [7:0] gm2_0_out;
// Sub-Modules for sub-galois operations
gm8 gm8_0 (.gm8_in(gm14_in), .gm8_out(gm8_0_out));
gm4 gm4_0 (.gm4_in(gm14_in), .gm4_out(gm4_0_out));
gm2 gm2_0 (.gm2_in(gm14_in), .gm2_out(gm2_0_out));
//Assign output to gm8(in) ^ gm4(in) ^ gm2(in)
assign gm14_out = gm8_0_out ^ gm4_0_out ^ gm2_0_out;
endmodule // gm14

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///////////////////////////////////////////
// rotateleft.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: RISC-V 32-bit left rotate
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module rotate_left(input logic [31:0] input_data,
input logic [4:0] shamt,
output logic [31:0] rot_data);
assign rot_data = (input_data << shamt) | (input_data >> (32 - shamt));
endmodule