From ac1f9ac4582063fce3d97b310db5ce0fe1fee9d9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 28 Jan 2025 09:14:58 -0800 Subject: [PATCH 1/8] Use imperas manifest files --- sim/questa/wally.do | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 945cb6ef4..bd2d81754 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -124,8 +124,8 @@ if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} { set lockstep 1 set lockstepvlog "+incdir+${IMPERAS_HOME}/ImpPublic/include/host \ +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ - ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \ - ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv" + -f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f \ + -f ${IMPERAS_HOME}/ImpProprietary/source/host/idv/idv.f" set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " } From ef8435ce88600ecea306c4f7bdbeef3c8be90d51 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 28 Jan 2025 09:18:07 -0800 Subject: [PATCH 2/8] Separate fcov and lockstep --- bin/wsim | 9 ++++----- sim/questa/wally.do | 13 ++++++++++--- testbench/testbench.sv | 19 +++++++++++++------ 3 files changed, 27 insertions(+), 14 deletions(-) diff --git a/bin/wsim b/bin/wsim index 96b857363..c8ec316fe 100755 --- a/bin/wsim +++ b/bin/wsim @@ -27,7 +27,7 @@ def parseArgs(): parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") - parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") + parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="") @@ -101,15 +101,15 @@ def prepSim(args, ElfFile): flagsList.append("--ccov") if args.fcov: flagsList.append("--fcov") - defineList.extend(["+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I"]) # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests + defineList.extend(["+define+ENABLE_RVVI_TRACE", "+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I"]) # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests argsList.extend(["+TRACE2COV_ENABLE=1", "+IDV_TRACE2COV=1"]) if args.gui: flagsList.append("--gui") if args.lockstep or args.lockstepverbose: flagsList.append("--lockstep") - if args.lockstep or args.lockstepverbose or args.fcov: + if args.lockstep or args.lockstepverbose: prefix = lockstepSetup(args) - defineList.append("+define+USE_IMPERAS_DV") + defineList.extend(["+define+USE_IMPERAS_DV", "+define+ENABLE_RVVI_TRACE"]) if args.config == "breker": # Requires a license for the breker tool. See tests/breker/README.md for details ElfFileNoExtension = os.path.splitext(ElfFile)[0] flagsList.append("--breker") @@ -154,7 +154,6 @@ def runQuesta(args, flags, prefix): args.params = fr'--params \"{args.params}\"' if args.define: args.define = fr'--define \"{args.define}\"' - # fcov implies lockstep cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {args.define} {flags}" cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"' print(f"Running Questa with command: {cmd}") diff --git a/sim/questa/wally.do b/sim/questa/wally.do index bd2d81754..6b921b9d5 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -111,15 +111,22 @@ if {[lcheck lst "--ccov"]} { # if --fcov found set flag and remove from list if {[lcheck lst "--fcov"]} { + set IMPERAS_HOME $::env(IMPERAS_HOME) set FunctCoverage 1 + # ImpProprietary is needed for trace2cov for now set FCvlog "+incdir+${FCRVVI}/unpriv \ +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \ +incdir+${FCRVVI}/common +incdir+${FCRVVI} \ - +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source" + +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ + +incdir+${IMPERAS_HOME}/ImpPublic/include/host \ + +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ + -f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f \ + -f ${IMPERAS_HOME}/ImpProprietary/source/host/idv/idv.f" + set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " } -# if --lockstep or --fcov found set flag and remove from list -if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} { +# if --lockstep found set flag and remove from list +if {[lcheck lst "--lockstep"]} { set IMPERAS_HOME $::env(IMPERAS_HOME) set lockstep 1 set lockstepvlog "+incdir+${IMPERAS_HOME}/ImpPublic/include/host \ diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 696a288f1..1366b9378 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -731,17 +731,22 @@ module testbench; end end +// RVVI trace for functional coverage and lockstep +`ifdef ENABLE_RVVI_TRACE + rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi(); + wallyTracer #(P) wallyTracer(rvvi); +`endif + +// Functional coverage +`ifdef INCLUDE_TRACE2COV + trace2cov idv_trace2cov(rvvi); // needed for fcov as of now +`endif + //////////////////////////////////////////////////////////////////////////////// // ImperasDV Co-simulator hooks //////////////////////////////////////////////////////////////////////////////// `ifdef USE_IMPERAS_DV - rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi(); - wallyTracer #(P) wallyTracer(rvvi); - - trace2log idv_trace2log(rvvi); - trace2cov idv_trace2cov(rvvi); - // enabling of comparison types trace2api #(.CMP_PC (1), .CMP_INS (1), @@ -751,6 +756,8 @@ end .CMP_CSR (1) ) idv_trace2api(rvvi); + // trace2log idv_trace2log(rvvi); // currently not used + string filename; initial begin // imperasDV requires the elffile be defined at the begining of the simulation. From 98ef85128c32b3431246baf9271f23ab36b6070c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 30 Jan 2025 01:08:33 -0800 Subject: [PATCH 3/8] Revert use imperas manifest --- sim/questa/wally.do | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 6b921b9d5..22c0c8e68 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -120,8 +120,8 @@ if {[lcheck lst "--fcov"]} { +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ +incdir+${IMPERAS_HOME}/ImpPublic/include/host \ +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ - -f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f \ - -f ${IMPERAS_HOME}/ImpProprietary/source/host/idv/idv.f" + ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \ + ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv" set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " } @@ -131,8 +131,8 @@ if {[lcheck lst "--lockstep"]} { set lockstep 1 set lockstepvlog "+incdir+${IMPERAS_HOME}/ImpPublic/include/host \ +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ - -f ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvvi.f \ - -f ${IMPERAS_HOME}/ImpProprietary/source/host/idv/idv.f" + ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \ + ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv" set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " } From 2fe3686a24aaf7a054541f7d96b9fe28dd7b1929 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 6 Feb 2025 02:47:03 -0800 Subject: [PATCH 4/8] More functional coverage refactoring --- bin/regression-wally | 2 +- bin/wsim | 4 +--- sim/imperas-verbose.ic | 3 +-- sim/questa/wally.do | 7 +------ testbench/common/trace2riscvISACOV.sv | 25 +++++++++++++++++++++++++ testbench/common/wallyTracer.sv | 1 + testbench/testbench.sv | 6 ++---- 7 files changed, 32 insertions(+), 16 deletions(-) create mode 100644 testbench/common/trace2riscvISACOV.sv diff --git a/bin/regression-wally b/bin/regression-wally index 9291faabc..1d0a79c39 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -320,7 +320,7 @@ def addTestsByDir(testDir, config, sim, coverStr, configs, lockstepMode=0, breke # fcov/ccov only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files fileEnd = "ALL.elf" if "cvw-arch-verif/tests" in testDir and "priv" not in testDir and (coverStr == "--fcov" or coverStr == "--ccov") else ".elf" if lockstepMode or coverStr == "--fcov": - gs = "Mismatches : 0" + gs = "** Note: $finish" elif brekerMode: gs="# trek: info: summary: Test PASSED" else: diff --git a/bin/wsim b/bin/wsim index c8ec316fe..c8592d993 100755 --- a/bin/wsim +++ b/bin/wsim @@ -101,13 +101,11 @@ def prepSim(args, ElfFile): flagsList.append("--ccov") if args.fcov: flagsList.append("--fcov") - defineList.extend(["+define+ENABLE_RVVI_TRACE", "+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I"]) # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests - argsList.extend(["+TRACE2COV_ENABLE=1", "+IDV_TRACE2COV=1"]) + defineList.extend(["+define+ENABLE_RVVI_TRACE", "+define+FCOV"]) if args.gui: flagsList.append("--gui") if args.lockstep or args.lockstepverbose: flagsList.append("--lockstep") - if args.lockstep or args.lockstepverbose: prefix = lockstepSetup(args) defineList.extend(["+define+USE_IMPERAS_DV", "+define+ENABLE_RVVI_TRACE"]) if args.config == "breker": # Requires a license for the breker tool. See tests/breker/README.md for details diff --git a/sim/imperas-verbose.ic b/sim/imperas-verbose.ic index fca9e072c..7cd53e38e 100644 --- a/sim/imperas-verbose.ic +++ b/sim/imperas-verbose.ic @@ -1,4 +1,3 @@ # Add Imperas simulator application instruction tracing ---verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000 +--verbose --trace --tracechange --traceshowicount --tracemode --tracemem XSL --monitornetschange # --traceafter 300000000 --override cpu/debugflags=6 --override cpu/verbose=1 ---override cpu/show_c_prefix=T diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 22c0c8e68..ba9891c0d 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -113,16 +113,11 @@ if {[lcheck lst "--ccov"]} { if {[lcheck lst "--fcov"]} { set IMPERAS_HOME $::env(IMPERAS_HOME) set FunctCoverage 1 - # ImpProprietary is needed for trace2cov for now set FCvlog "+incdir+${FCRVVI}/unpriv \ +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \ +incdir+${FCRVVI}/common +incdir+${FCRVVI} \ +incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \ - +incdir+${IMPERAS_HOME}/ImpPublic/include/host \ - +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ - ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \ - ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv" - set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " + ${FCRVVI}/*.sv" } # if --lockstep found set flag and remove from list diff --git a/testbench/common/trace2riscvISACOV.sv b/testbench/common/trace2riscvISACOV.sv new file mode 100644 index 000000000..0f8d3f612 --- /dev/null +++ b/testbench/common/trace2riscvISACOV.sv @@ -0,0 +1,25 @@ +// trace2riscvISACOV.sv +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +`include "RISCV_coverage.svh" + +module trace2riscvISACOV(rvviTrace rvvi); + // Connect coverage class to RVVI trace interface + coverage #(rvvi.ILEN, rvvi.XLEN, rvvi.FLEN, rvvi.VLEN, rvvi.NHART, rvvi.RETIRE) riscvISACOV; + initial begin + riscvISACOV = new(rvvi); + $display("trace2riscvISACOV: coverage initialized"); + end + + // Dissassemble instruction from RVVI trace for processing by coverage model + string disass; + dissassembler #(rvvi.XLEN) dissassembler(rvvi.insn[0][0], disass); + + // Invoke the riscvISACOV sample function on each clock edge for the current Instruction + // If RVVI accepts more than one instruction or hart, iterate over all of them in the + // correct order of retirement (TODO: multiple instructions/harts not implemented) + always_ff @(posedge rvvi.clk) begin + riscvISACOV.sample(rvvi.trap[0][0], 0, 0, {$sformatf("%h ", rvvi.insn[0][0]), disass}); + $display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass); + end +endmodule diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 6ec35215d..faa3a98b8 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -742,6 +742,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); end always_ff @(posedge clk) begin + $display("wallyTracer: %b", rvvi.insn[0][0]); if(valid) begin if(`STD_LOG) begin $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 1366b9378..b5f63de67 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -738,8 +738,8 @@ end `endif // Functional coverage -`ifdef INCLUDE_TRACE2COV - trace2cov idv_trace2cov(rvvi); // needed for fcov as of now +`ifdef FCOV + trace2riscvISACOV trace2riscvISACOV(rvvi); `endif //////////////////////////////////////////////////////////////////////////////// @@ -756,8 +756,6 @@ end .CMP_CSR (1) ) idv_trace2api(rvvi); - // trace2log idv_trace2log(rvvi); // currently not used - string filename; initial begin // imperasDV requires the elffile be defined at the begining of the simulation. From 578441bfc325861194d1b4052fa5edf733b57dc6 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 8 Feb 2025 23:22:45 -0800 Subject: [PATCH 5/8] Only sample if rvvi is valid --- testbench/common/trace2riscvISACOV.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/testbench/common/trace2riscvISACOV.sv b/testbench/common/trace2riscvISACOV.sv index 0f8d3f612..d45bf70fb 100644 --- a/testbench/common/trace2riscvISACOV.sv +++ b/testbench/common/trace2riscvISACOV.sv @@ -19,7 +19,9 @@ module trace2riscvISACOV(rvviTrace rvvi); // If RVVI accepts more than one instruction or hart, iterate over all of them in the // correct order of retirement (TODO: multiple instructions/harts not implemented) always_ff @(posedge rvvi.clk) begin - riscvISACOV.sample(rvvi.trap[0][0], 0, 0, {$sformatf("%h ", rvvi.insn[0][0]), disass}); - $display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass); + if (rvvi.valid[0][0] == 1) begin + riscvISACOV.sample(rvvi.trap[0][0], 0, 0, {$sformatf("%h ", rvvi.insn[0][0]), disass}); + $display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass); + end end endmodule From 1db1b3bd1e082cc86c89f92c9ab4df2777dfec88 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 9 Feb 2025 12:36:28 -0800 Subject: [PATCH 6/8] Use defines instead of includes for each extension --- config/rv32gc/coverage.svh | 95 ++++++++++++++++++------------------ config/rv64gc/coverage.svh | 98 +++++++++++++++++++------------------- 2 files changed, 97 insertions(+), 96 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 50beb4b14..365b60e49 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -6,60 +6,61 @@ // It defines which extensions are enabled for that config. // Define XLEN, used in covergroups -`define XLEN32 1 +`define XLEN32 // Define relevant addresses `define ACCESS_FAULT_ADDRESS 32'h0000 `define CLINT_BASE 64'h02000000 // Unprivileged extensions -`include "I_coverage.svh" -`include "M_coverage.svh" -`include "F_coverage.svh" -`include "D_coverage.svh" -`include "Zba_coverage.svh" -`include "Zbb_coverage.svh" -`include "Zbc_coverage.svh" -`include "Zbs_coverage.svh" -`include "ZfaF_coverage.svh" -`include "ZfaD_coverage.svh" -`include "ZfaZfh_coverage.svh" -`include "Zfh_coverage.svh" -`include "ZfhD_coverage.svh" +`define I_COVERAGE +`define M_COVERAGE +`define F_COVERAGE +`define D_COVERAGE +`define ZBA_COVERAGE +`define ZBB_COVERAGE +`define ZBC_COVERAGE +`define ZBS_COVERAGE +`define ZFA_F_COVERAGE +`define ZFA_D_COVERAGE +`define ZFA_ZFH_COVERAGE +`define ZFA_ZFH_D_COVERAGE +`define ZFH_COVERAGE +`define ZFH_D_COVERAGE // Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled -`include "Zfhmin_coverage.svh" +`define ZFHMIN_coverage +`define ZFHMIN_D_COVERAGE // Note: Zmmul is a subset of M, so usually only one or the other would be used. -`include "Zmmul_coverage.svh" -`include "Zicond_coverage.svh" -`include "Zca_coverage.svh" -`include "Zcb_coverage.svh" -`include "ZcbM_coverage.svh" -`include "ZcbZbb_coverage.svh" -`include "Zcf_coverage.svh" -`include "Zcd_coverage.svh" -`include "Zicsr_coverage.svh" -`include "Zbkb_coverage.svh" -`include "Zbkc_coverage.svh" -`include "Zbkx_coverage.svh" -`include "Zknd_coverage.svh" -`include "Zkne_coverage.svh" -`include "Zknh_coverage.svh" -`include "Zaamo_coverage.svh" -`include "Zalrsc_coverage.svh" +`define ZMMUL_COVERAGE +`define ZICOND_COVERAGE +`define ZCA_COVERAGE +`define ZCB_COVERAGE +`define ZCB_M_COVERAGE +`define ZCB_ZBB_COVERAGE +`define ZCB_ZBA_COVERAGE +`define ZCF_COVERAGE +`define ZCD_COVERAGE +`define ZICSR_COVERAGE +`define ZBKB_COVERAGE +`define ZBKC_COVERAGE +`define ZBKX_COVERAGE +`define ZKND_COVERAGE +`define ZKNE_COVERAGE +`define ZKNH_COVERAGE +`define ZAAMO_COVERAGE +`define ZALRSC_COVERAGE // Privileged extensions -`include "ZicsrM_coverage.svh" -`include "ZicsrF_coverage.svh" -`include "ZicsrU_coverage.svh" -`include "RV32VM_coverage.svh" -`include "RV32VM_PMP_coverage.svh" -`include "EndianU_coverage.svh" -`include "EndianM_coverage.svh" -`include "EndianS_coverage.svh" -`include "ExceptionsM_coverage.svh" -`include "ExceptionsZc_coverage.svh" -`include "ZicntrU_coverage.svh" -`include "ZicntrS_coverage.svh" -`include "ZicntrM_coverage.svh" -`include "ZfaZfhD_coverage.svh" -`include "ZfhminD_coverage.svh" +`define RV32VM_COVERAGE +`define RV32VM_PMP_coverage +`define ZICSRM_COVERAGE +`define ZICSRF_COVERAGE +`define ZICSRU_COVERAGE +`define ENDIANU_COVERAGE +`define ENDIANS_COVERAGE +`define ENDIANM_COVERAGE +`define EXCEPTIONSM_COVERAGE +`define EXCEPTIONSZC_COVERAGE +`define ZICNTRU_COVERAGE +`define ZICNTRS_COVERAGE +`define ZICNTRM_COVERAGE diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 0ad16d7bc..ef6538116 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -6,63 +6,63 @@ // It defines which extensions are enabled for that config. // Define XLEN, used in covergroups -`define XLEN64 1 +`define XLEN64 // Define relevant addresses `define ACCESS_FAULT_ADDRESS 64'h00000000 `define CLINT_BASE 64'h02000000 // Unprivileged extensions -`include "I_coverage.svh" -`include "M_coverage.svh" -`include "F_coverage.svh" -`include "D_coverage.svh" -`include "Zba_coverage.svh" -`include "Zbb_coverage.svh" -`include "Zbc_coverage.svh" -`include "Zbs_coverage.svh" -`include "ZfaF_coverage.svh" -`include "ZfaD_coverage.svh" -`include "ZfaZfh_coverage.svh" -`include "ZfhD_coverage.svh" -`include "Zfh_coverage.svh" +`define I_COVERAGE +`define M_COVERAGE +`define F_COVERAGE +`define D_COVERAGE +`define ZBA_COVERAGE +`define ZBB_COVERAGE +`define ZBC_COVERAGE +`define ZBS_COVERAGE +`define ZFA_F_COVERAGE +`define ZFA_D_COVERAGE +`define ZFA_ZFH_COVERAGE +`define ZFA_ZFH_D_COVERAGE +`define ZFH_COVERAGE +`define ZFH_D_COVERAGE // Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled -`include "Zfhmin_coverage.svh" +`define ZFHMIN_coverage +`define ZFHMIN_D_COVERAGE // Note: Zmmul is a subset of M, so usually only one or the other would be used. -`include "Zmmul_coverage.svh" -`include "Zicond_coverage.svh" -`include "Zca_coverage.svh" -`include "Zcb_coverage.svh" -`include "ZcbM_coverage.svh" -`include "ZcbZbb_coverage.svh" -`include "ZcbZba_coverage.svh" -`include "Zcd_coverage.svh" -`include "Zicsr_coverage.svh" -`include "Zbkb_coverage.svh" -`include "Zbkc_coverage.svh" -`include "Zbkx_coverage.svh" -`include "Zknd_coverage.svh" -`include "Zkne_coverage.svh" -`include "Zknh_coverage.svh" -`include "Zaamo_coverage.svh" -`include "Zalrsc_coverage.svh" +`define ZMMUL_COVERAGE +`define ZICOND_COVERAGE +`define ZCA_COVERAGE +`define ZCB_COVERAGE +`define ZCB_M_COVERAGE +`define ZCB_ZBB_COVERAGE +`define ZCB_ZBA_COVERAGE +`define ZCD_COVERAGE +`define ZICSR_COVERAGE +`define ZBKB_COVERAGE +`define ZBKC_COVERAGE +`define ZBKX_COVERAGE +`define ZKND_COVERAGE +`define ZKNE_COVERAGE +`define ZKNH_COVERAGE +`define ZAAMO_COVERAGE +`define ZALRSC_COVERAGE // Privileged extensions -`include "RV64VM_coverage.svh" -`include "ZicsrM_coverage.svh" -`include "ZicsrF_coverage.svh" -`include "ZicsrU_coverage.svh" -`include "EndianU_coverage.svh" -`include "EndianM_coverage.svh" -`include "EndianS_coverage.svh" -`include "ExceptionsM_coverage.svh" -`include "ExceptionsZc_coverage.svh" -`include "ZicntrU_coverage.svh" -`include "ZicntrS_coverage.svh" -`include "ZicntrM_coverage.svh" -`include "ZfaZfhD_coverage.svh" -`include "ZfhminD_coverage.svh" +`define RV64VM_COVERAGE +`define ZICSRM_COVERAGE +`define ZICSRF_COVERAGE +`define ZICSRU_COVERAGE +`define ENDIANU_COVERAGE +`define ENDIANS_COVERAGE +`define ENDIANM_COVERAGE +`define EXCEPTIONSM_COVERAGE +`define EXCEPTIONSZC_COVERAGE +`define ZICNTRU_COVERAGE +`define ZICNTRS_COVERAGE +`define ZICNTRM_COVERAGE -// `include "RV64VM_PMP_coverage.svh" -// `include "RV64CBO_VM_coverage.svh" -// `include "RV64CBO_PMP_coverage.svh" +// `define RV64VM_PMP_COVERAGE +// `define RV64CBO_VM_COVERAGE +// `define RV64CBO_PMP_COVERAGE From 9e2a2ec31b517504321a9358f673277da5c41241 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 9 Feb 2025 12:36:41 -0800 Subject: [PATCH 7/8] Make disassemble a function instead of a module --- testbench/common/trace2riscvISACOV.sv | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/testbench/common/trace2riscvISACOV.sv b/testbench/common/trace2riscvISACOV.sv index d45bf70fb..307d0e8d5 100644 --- a/testbench/common/trace2riscvISACOV.sv +++ b/testbench/common/trace2riscvISACOV.sv @@ -1,9 +1,15 @@ // trace2riscvISACOV.sv // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Load which extensions are supported in this configuration (from $WALLY/config//coverage.svh) +`include "coverage.svh" +`include "disassemble.svh" + +// Load the coverage classes `include "RISCV_coverage.svh" module trace2riscvISACOV(rvviTrace rvvi); + string disass; // Connect coverage class to RVVI trace interface coverage #(rvvi.ILEN, rvvi.XLEN, rvvi.FLEN, rvvi.VLEN, rvvi.NHART, rvvi.RETIRE) riscvISACOV; initial begin @@ -11,17 +17,15 @@ module trace2riscvISACOV(rvviTrace rvvi); $display("trace2riscvISACOV: coverage initialized"); end - // Dissassemble instruction from RVVI trace for processing by coverage model - string disass; - dissassembler #(rvvi.XLEN) dissassembler(rvvi.insn[0][0], disass); - // Invoke the riscvISACOV sample function on each clock edge for the current Instruction // If RVVI accepts more than one instruction or hart, iterate over all of them in the // correct order of retirement (TODO: multiple instructions/harts not implemented) always_ff @(posedge rvvi.clk) begin if (rvvi.valid[0][0] == 1) begin + disass = disassemble(rvvi.insn[0][0]); riscvISACOV.sample(rvvi.trap[0][0], 0, 0, {$sformatf("%h ", rvvi.insn[0][0]), disass}); - $display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass); + // $display("trace2riscvISACOV: sample taken for instruction %h: %s", rvvi.insn[0][0], disass); + $display("0x%h: %s", rvvi.insn[0][0], disass); end end endmodule From a61ad1c6494012f159d6e07b2c89af7b2c0bbf9f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 9 Feb 2025 13:46:32 -0800 Subject: [PATCH 8/8] Fix rv32 coverage file --- config/rv32gc/coverage.svh | 1 - 1 file changed, 1 deletion(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 365b60e49..5e6ba871f 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -37,7 +37,6 @@ `define ZCB_COVERAGE `define ZCB_M_COVERAGE `define ZCB_ZBB_COVERAGE -`define ZCB_ZBA_COVERAGE `define ZCF_COVERAGE `define ZCD_COVERAGE `define ZICSR_COVERAGE