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made fixes to radix-2 divider testbench - divider doesn't pass

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This commit is contained in:
Katherine Parry 2022-06-20 23:01:53 +00:00
parent a0abfdefe6
commit 0c6d36bbb2
1 changed files with 5 additions and 3 deletions
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8
pipelined/srt/testbench.sv
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@ -7,7 +7,7 @@ module counter(input logic clk,
input logic req, input logic req,
output logic done); output logic done);
logic [5:0] count; logic [7:0] count;
// This block of control logic sequences the divider // This block of control logic sequences the divider
// through its iterations. You may modify it if you // through its iterations. You may modify it if you
@ -17,7 +17,7 @@ module counter(input logic clk,
always @(posedge clk) always @(posedge clk)
begin begin
if (count == 54) done <= #1 1; if (count == `DIVLEN+1) done <= #1 1;
else if (done | req) done <= #1 0; else if (done | req) done <= #1 0;
if (req) count <= #1 0; if (req) count <= #1 0;
else count <= #1 count+1; else count <= #1 count+1;
@ -110,12 +110,14 @@ module testbench;
always @(posedge clk) always @(posedge clk)
begin begin
r = Quot[`DIVLEN:`DIVLEN - 52];
rOTFC = QuotOTFC[`DIVLEN:`DIVLEN - 52];
if (done) if (done)
begin begin
req <= #5 1; req <= #5 1;
diffp = correctr[51:0] - r; diffp = correctr[51:0] - r;
diffn = r - correctr[51:0]; diffn = r - correctr[51:0];
if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
begin begin
errors = errors+1; errors = errors+1;
$display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp); $display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp);